package/boot/uboot-d1/patches/0081-mmc-sunxi-Hack-up-the-driver-for-the-D1.patch

   1 From 4df80766531bc35510981ebc5ea0bb07264beac9 Mon Sep 17 00:00:00 2001
   2 From: Samuel Holland <samuel@sholland.org>
   3 Date: Sun, 8 Aug 2021 19:31:20 -0500
   4 Subject: [PATCH 81/90] mmc: sunxi: Hack up the driver for the D1
   5
   6 Signed-off-by: Samuel Holland <samuel@sholland.org>
   7 ---
   8  arch/riscv/include/asm/io.h |  1 +
   9  drivers/mmc/sunxi_mmc.c     | 29 +++++++++++++++++++++++++----
  10  drivers/mmc/sunxi_mmc.h     |  2 --
  11  3 files changed, 26 insertions(+), 6 deletions(-)
  12
  13 --- a/arch/riscv/include/asm/io.h
  14 +++ b/arch/riscv/include/asm/io.h
  15 @@ -85,6 +85,7 @@ static inline u16 readw(const volatile v
  16         return val;
  17  }
  18
  19 +#define readl_relaxed readl
  20  static inline u32 readl(const volatile void __iomem *addr)
  21  {
  22         u32     val;
  23 --- a/drivers/mmc/sunxi_mmc.c
  24 +++ b/drivers/mmc/sunxi_mmc.c
  25 @@ -23,9 +23,9 @@
  26  #include <reset.h>
  27  #include <asm/gpio.h>
  28  #include <asm/io.h>
  29 +#if !CONFIG_IS_ENABLED(DM_MMC)
  30  #include <asm/arch/clock.h>
  31  #include <asm/arch/cpu.h>
  32 -#if !CONFIG_IS_ENABLED(DM_MMC)
  33  #include <asm/arch/mmc.h>
  34  #endif
  35  #include <linux/delay.h>
  36 @@ -36,6 +36,23 @@
  37  #define CCM_MMC_CTRL_MODE_SEL_NEW      0
  38  #endif
  39
  40 +#include "../../arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h"
  41 +
  42 +unsigned int clock_get_pll6(void)
  43 +{
  44 +       uint32_t rval = readl((void *)0x2001020);
  45 +
  46 +       int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
  47 +       int m = ((rval >> 1) & 0x1) + 1;
  48 +       int p0 = ((rval >> 16) & 0x7) + 1;
  49 +       /* The register defines PLL6-2X, not plain PLL6 */
  50 +       uint32_t freq = 24000000UL * n / m / p0;
  51 +
  52 +       printf("PLL reg = 0x%08x, freq = %d\n", rval, freq);
  53 +
  54 +       return freq;
  55 +}
  56 +
  57  struct sunxi_mmc_plat {
  58         struct mmc_config cfg;
  59         struct mmc mmc;
  60 @@ -60,7 +77,8 @@ static bool sunxi_mmc_can_calibrate(void
  61         return IS_ENABLED(CONFIG_MACH_SUN50I) ||
  62                IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
  63                IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
  64 -              IS_ENABLED(CONFIG_MACH_SUN8I_R40);
  65 +              IS_ENABLED(CONFIG_MACH_SUN8I_R40) ||
  66 +              IS_ENABLED(CONFIG_TARGET_SUN20I_D1);
  67  }
  68
  69  static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
  70 @@ -194,7 +212,7 @@ static int mmc_config_clock(struct sunxi
  71         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
  72         writel(rval, &priv->reg->clkcr);
  73
  74 -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
  75 +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_TARGET_SUN20I_D1)
  76         /* A64 supports calibration of delays on MMC controller and we
  77          * have to set delay of zero before starting calibration.
  78          * Allwinner BSP driver sets a delay only in the case of
  79 @@ -622,7 +640,8 @@ static unsigned get_mclk_offset(void)
  80         if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
  81                 return 0x410;
  82
  83 -       if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
  84 +       if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
  85 +           IS_ENABLED(CONFIG_TARGET_SUN20I_D1))
  86                 return 0x830;
  87
  88         return 0x88;
  89 @@ -662,6 +681,7 @@ static int sunxi_mmc_probe(struct udevic
  90                 return ret;
  91         ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
  92
  93 +#define SUNXI_MMC0_BASE 0x4020000
  94         priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
  95         priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
  96
  97 @@ -703,6 +723,7 @@ static const struct udevice_id sunxi_mmc
  98         { .compatible = "allwinner,sun7i-a20-mmc" },
  99         { .compatible = "allwinner,sun8i-a83t-emmc" },
 100         { .compatible = "allwinner,sun9i-a80-mmc" },
 101 +       { .compatible = "allwinner,sun20i-d1-mmc" },
 102         { .compatible = "allwinner,sun50i-a64-mmc" },
 103         { .compatible = "allwinner,sun50i-a64-emmc" },
 104         { .compatible = "allwinner,sun50i-h6-mmc" },
 105 --- a/drivers/mmc/sunxi_mmc.h
 106 +++ b/drivers/mmc/sunxi_mmc.h
 107 @@ -45,11 +45,9 @@ struct sunxi_mmc {
 108         u32 chda;               /* 0x90 */
 109         u32 cbda;               /* 0x94 */
 110         u32 res2[26];
 111 -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
 112         u32 res3[17];
 113         u32 samp_dl;
 114         u32 res4[46];
 115 -#endif
 116         u32 fifo;               /* 0x100 / 0x200 FIFO access address */
 117  };
 118