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uboot-d1: add bootloader for upcoming d1 target
[openwrt/staging/mans0n.git] / package / boot / uboot-d1 / patches / 0078-riscv-Add-Allwinner-D1-devicetrees.patch
1 From ce792f7abd4294ebba76f76d9d7aa90c7970de8e Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Thu, 4 Aug 2022 23:35:09 -0500
4 Subject: [PATCH 78/90] riscv: Add Allwinner D1 devicetrees
5
6 Signed-off-by: Samuel Holland <samuel@sholland.org>
7 ---
8 arch/riscv/dts/Makefile | 9 +
9 .../riscv/dts/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
10 .../dts/sun20i-d1-common-regulators.dtsi | 51 +
11 arch/riscv/dts/sun20i-d1-devterm-v3.14.dts | 37 +
12 .../dts/sun20i-d1-dongshan-nezha-stu.dts | 114 +++
13 .../dts/sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
14 .../dts/sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
15 .../dts/sun20i-d1-lichee-rv-86-panel.dtsi | 92 ++
16 arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts | 74 ++
17 arch/riscv/dts/sun20i-d1-lichee-rv.dts | 84 ++
18 arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts | 128 +++
19 arch/riscv/dts/sun20i-d1-nezha.dts | 171 ++++
20 arch/riscv/dts/sun20i-d1.dtsi | 900 ++++++++++++++++++
21 arch/riscv/dts/sunxi-u-boot.dtsi | 68 ++
22 include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 +
23 include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 +
24 16 files changed, 2044 insertions(+)
25 create mode 100644 arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
26 create mode 100644 arch/riscv/dts/sun20i-d1-common-regulators.dtsi
27 create mode 100644 arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
28 create mode 100644 arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
29 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
30 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-720p.dts
31 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
32 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
33 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv.dts
34 create mode 100644 arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
35 create mode 100644 arch/riscv/dts/sun20i-d1-nezha.dts
36 create mode 100644 arch/riscv/dts/sun20i-d1.dtsi
37 create mode 100644 arch/riscv/dts/sunxi-u-boot.dtsi
38 create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h
39 create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h
40
41 --- a/arch/riscv/dts/Makefile
42 +++ b/arch/riscv/dts/Makefile
43 @@ -7,6 +7,15 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) +
44 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
45 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
46 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
47 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-clockworkpi-v3.14.dtb
48 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-devterm-v3.14.dtb
49 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-dongshan-nezha-stu.dtb
50 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-86-panel-480p.dtb
51 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-86-panel-720p.dtb
52 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-dock.dtb
53 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv.dtb
54 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-mangopi-mq-pro.dtb
55 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-nezha.dtb
56
57 include $(srctree)/scripts/Makefile.dts
58
59 --- /dev/null
60 +++ b/arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
61 @@ -0,0 +1,242 @@
62 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
63 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
64 +
65 +/dts-v1/;
66 +
67 +#include <dt-bindings/gpio/gpio.h>
68 +
69 +#include "sun20i-d1.dtsi"
70 +#include "sun20i-d1-common-regulators.dtsi"
71 +
72 +/ {
73 + model = "ClockworkPi v3.14 (R-01)";
74 + compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
75 +
76 + aliases {
77 + ethernet0 = &ap6256;
78 + mmc0 = &mmc0;
79 + serial0 = &uart0;
80 + };
81 +
82 + chosen {
83 + stdout-path = "serial0:115200n8";
84 + };
85 +
86 + /*
87 + * This regulator is PWM-controlled, but the PWM controller is not
88 + * yet supported, so fix the regulator to its default voltage.
89 + */
90 + reg_vdd_cpu: vdd-cpu {
91 + compatible = "regulator-fixed";
92 + regulator-name = "vdd-cpu";
93 + regulator-min-microvolt = <1100000>;
94 + regulator-max-microvolt = <1100000>;
95 + vin-supply = <&reg_vcc>;
96 + };
97 +
98 + wifi_pwrseq: wifi-pwrseq {
99 + compatible = "mmc-pwrseq-simple";
100 + reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
101 + };
102 +};
103 +
104 +&cpu0 {
105 + cpu-supply = <&reg_vdd_cpu>;
106 +};
107 +
108 +&ehci1 {
109 + status = "okay";
110 +};
111 +
112 +&i2c0 {
113 + pinctrl-0 = <&i2c0_pb10_pins>;
114 + pinctrl-names = "default";
115 + status = "okay";
116 +
117 + axp221: pmic@34 {
118 + compatible = "x-powers,axp228", "x-powers,axp221";
119 + reg = <0x34>;
120 + interrupt-parent = <&pio>;
121 + interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
122 + interrupt-controller;
123 + #interrupt-cells = <1>;
124 +
125 + ac_power_supply: ac-power {
126 + compatible = "x-powers,axp221-ac-power-supply";
127 + };
128 +
129 + axp_adc: adc {
130 + compatible = "x-powers,axp221-adc";
131 + #io-channel-cells = <1>;
132 + };
133 +
134 + battery_power_supply: battery-power {
135 + compatible = "x-powers,axp221-battery-power-supply";
136 + };
137 +
138 + regulators {
139 + x-powers,dcdc-freq = <3000>;
140 +
141 + reg_dcdc1: dcdc1 {
142 + regulator-name = "sys-3v3";
143 + regulator-always-on;
144 + regulator-min-microvolt = <3300000>;
145 + regulator-max-microvolt = <3300000>;
146 + };
147 +
148 + reg_dcdc3: dcdc3 {
149 + regulator-name = "sys-1v8";
150 + regulator-always-on;
151 + regulator-min-microvolt = <1800000>;
152 + regulator-max-microvolt = <1800000>;
153 + };
154 +
155 + reg_aldo1: aldo1 {
156 + regulator-name = "aud-3v3";
157 + regulator-min-microvolt = <3300000>;
158 + regulator-max-microvolt = <3300000>;
159 + };
160 +
161 + reg_aldo2: aldo2 {
162 + regulator-name = "disp-3v3";
163 + regulator-always-on;
164 + regulator-min-microvolt = <3300000>;
165 + regulator-max-microvolt = <3300000>;
166 + };
167 +
168 + reg_aldo3: aldo3 {
169 + regulator-name = "vdd-wifi";
170 + regulator-min-microvolt = <1800000>;
171 + regulator-max-microvolt = <1800000>;
172 + };
173 +
174 + /* DLDO1 and ELDO1-3 are connected in parallel. */
175 + reg_dldo1: dldo1 {
176 + regulator-name = "vbat-wifi-a";
177 + regulator-always-on;
178 + regulator-min-microvolt = <3300000>;
179 + regulator-max-microvolt = <3300000>;
180 + };
181 +
182 + /* DLDO2-DLDO4 are connected in parallel. */
183 + reg_dldo2: dldo2 {
184 + regulator-name = "vcc-3v3-ext-a";
185 + regulator-always-on;
186 + regulator-min-microvolt = <3300000>;
187 + regulator-max-microvolt = <3300000>;
188 + };
189 +
190 + reg_dldo3: dldo3 {
191 + regulator-name = "vcc-3v3-ext-b";
192 + regulator-always-on;
193 + regulator-min-microvolt = <3300000>;
194 + regulator-max-microvolt = <3300000>;
195 + };
196 +
197 + reg_dldo4: dldo4 {
198 + regulator-name = "vcc-3v3-ext-c";
199 + regulator-always-on;
200 + regulator-min-microvolt = <3300000>;
201 + regulator-max-microvolt = <3300000>;
202 + };
203 +
204 + reg_eldo1: eldo1 {
205 + regulator-name = "vbat-wifi-b";
206 + regulator-always-on;
207 + regulator-min-microvolt = <3300000>;
208 + regulator-max-microvolt = <3300000>;
209 + };
210 +
211 + reg_eldo2: eldo2 {
212 + regulator-name = "vbat-wifi-c";
213 + regulator-always-on;
214 + regulator-min-microvolt = <3300000>;
215 + regulator-max-microvolt = <3300000>;
216 + };
217 +
218 + reg_eldo3: eldo3 {
219 + regulator-name = "vbat-wifi-d";
220 + regulator-always-on;
221 + regulator-min-microvolt = <3300000>;
222 + regulator-max-microvolt = <3300000>;
223 + };
224 + };
225 +
226 + usb_power_supply: usb-power {
227 + compatible = "x-powers,axp221-usb-power-supply";
228 + status = "disabled";
229 + };
230 + };
231 +};
232 +
233 +&mmc0 {
234 + broken-cd;
235 + bus-width = <4>;
236 + disable-wp;
237 + vmmc-supply = <&reg_dcdc1>;
238 + vqmmc-supply = <&reg_vcc_3v3>;
239 + pinctrl-0 = <&mmc0_pins>;
240 + pinctrl-names = "default";
241 + status = "okay";
242 +};
243 +
244 +&mmc1 {
245 + bus-width = <4>;
246 + mmc-pwrseq = <&wifi_pwrseq>;
247 + non-removable;
248 + vmmc-supply = <&reg_dldo1>;
249 + vqmmc-supply = <&reg_aldo3>;
250 + pinctrl-0 = <&mmc1_pins>;
251 + pinctrl-names = "default";
252 + status = "okay";
253 +
254 + ap6256: wifi@1 {
255 + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
256 + reg = <1>;
257 + interrupt-parent = <&pio>;
258 + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
259 + interrupt-names = "host-wake";
260 + };
261 +};
262 +
263 +&ohci1 {
264 + status = "okay";
265 +};
266 +
267 +&pio {
268 + vcc-pg-supply = <&reg_ldoa>;
269 +};
270 +
271 +&uart0 {
272 + pinctrl-0 = <&uart0_pb8_pins>;
273 + pinctrl-names = "default";
274 + status = "okay";
275 +};
276 +
277 +&uart1 {
278 + uart-has-rtscts;
279 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
280 + pinctrl-names = "default";
281 + status = "okay";
282 +
283 + bluetooth {
284 + compatible = "brcm,bcm4345c5";
285 + interrupt-parent = <&pio>;
286 + interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
287 + device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
288 + shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
289 + max-speed = <1500000>;
290 + vbat-supply = <&reg_dldo1>;
291 + vddio-supply = <&reg_aldo3>;
292 + };
293 +};
294 +
295 +&usb_otg {
296 + dr_mode = "peripheral";
297 + status = "okay";
298 +};
299 +
300 +&usbphy {
301 + usb0_vbus_power-supply = <&ac_power_supply>;
302 + status = "okay";
303 +};
304 --- /dev/null
305 +++ b/arch/riscv/dts/sun20i-d1-common-regulators.dtsi
306 @@ -0,0 +1,51 @@
307 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
308 +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
309 +
310 +/ {
311 + reg_vcc: vcc {
312 + compatible = "regulator-fixed";
313 + regulator-name = "vcc";
314 + regulator-min-microvolt = <5000000>;
315 + regulator-max-microvolt = <5000000>;
316 + };
317 +
318 + reg_vcc_3v3: vcc-3v3 {
319 + compatible = "regulator-fixed";
320 + regulator-name = "vcc-3v3";
321 + regulator-min-microvolt = <3300000>;
322 + regulator-max-microvolt = <3300000>;
323 + vin-supply = <&reg_vcc>;
324 + };
325 +};
326 +
327 +&lradc {
328 + vref-supply = <&reg_aldo>;
329 +};
330 +
331 +&pio {
332 + vcc-pb-supply = <&reg_vcc_3v3>;
333 + vcc-pc-supply = <&reg_vcc_3v3>;
334 + vcc-pd-supply = <&reg_vcc_3v3>;
335 + vcc-pe-supply = <&reg_vcc_3v3>;
336 + vcc-pf-supply = <&reg_vcc_3v3>;
337 + vcc-pg-supply = <&reg_vcc_3v3>;
338 +};
339 +
340 +&reg_aldo {
341 + regulator-min-microvolt = <1800000>;
342 + regulator-max-microvolt = <1800000>;
343 + vdd33-supply = <&reg_vcc_3v3>;
344 +};
345 +
346 +&reg_hpldo {
347 + regulator-min-microvolt = <1800000>;
348 + regulator-max-microvolt = <1800000>;
349 + hpldoin-supply = <&reg_vcc_3v3>;
350 +};
351 +
352 +&reg_ldoa {
353 + regulator-always-on;
354 + regulator-min-microvolt = <1800000>;
355 + regulator-max-microvolt = <1800000>;
356 + ldo-in-supply = <&reg_vcc_3v3>;
357 +};
358 --- /dev/null
359 +++ b/arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
360 @@ -0,0 +1,37 @@
361 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
362 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
363 +
364 +/dts-v1/;
365 +
366 +#include "sun20i-d1-clockworkpi-v3.14.dts"
367 +
368 +/ {
369 + model = "Clockwork DevTerm (R-01)";
370 + compatible = "clockwork,r-01-devterm-v3.14",
371 + "clockwork,r-01-clockworkpi-v3.14",
372 + "allwinner,sun20i-d1";
373 +
374 + fan {
375 + compatible = "gpio-fan";
376 + gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
377 + gpio-fan,speed-map = <0 0>,
378 + <6000 1>;
379 + #cooling-cells = <2>;
380 + };
381 +
382 + i2c-gpio-0 {
383 + compatible = "i2c-gpio";
384 + sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
385 + scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
386 + #address-cells = <1>;
387 + #size-cells = <0>;
388 +
389 + adc@54 {
390 + compatible = "ti,adc101c";
391 + reg = <0x54>;
392 + interrupt-parent = <&pio>;
393 + interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
394 + vref-supply = <&reg_dldo2>;
395 + };
396 + };
397 +};
398 --- /dev/null
399 +++ b/arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
400 @@ -0,0 +1,114 @@
401 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
402 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
403 +
404 +/dts-v1/;
405 +
406 +#include <dt-bindings/gpio/gpio.h>
407 +#include <dt-bindings/leds/common.h>
408 +
409 +#include "sun20i-d1.dtsi"
410 +#include "sun20i-d1-common-regulators.dtsi"
411 +
412 +/ {
413 + model = "Dongshan Nezha STU";
414 + compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
415 +
416 + aliases {
417 + ethernet0 = &emac;
418 + mmc0 = &mmc0;
419 + serial0 = &uart0;
420 + };
421 +
422 + chosen {
423 + stdout-path = "serial0:115200n8";
424 + };
425 +
426 + leds {
427 + compatible = "gpio-leds";
428 +
429 + led-0 {
430 + color = <LED_COLOR_ID_GREEN>;
431 + function = LED_FUNCTION_STATUS;
432 + gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
433 + };
434 + };
435 +
436 + reg_usbvbus: usbvbus {
437 + compatible = "regulator-fixed";
438 + regulator-name = "usbvbus";
439 + regulator-min-microvolt = <5000000>;
440 + regulator-max-microvolt = <5000000>;
441 + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
442 + enable-active-high;
443 + vin-supply = <&reg_vcc>;
444 + };
445 +
446 + /*
447 + * This regulator is PWM-controlled, but the PWM controller is not
448 + * yet supported, so fix the regulator to its default voltage.
449 + */
450 + reg_vdd_cpu: vdd-cpu {
451 + compatible = "regulator-fixed";
452 + regulator-name = "vdd-cpu";
453 + regulator-min-microvolt = <1100000>;
454 + regulator-max-microvolt = <1100000>;
455 + vin-supply = <&reg_vcc>;
456 + };
457 +};
458 +
459 +&cpu0 {
460 + cpu-supply = <&reg_vdd_cpu>;
461 +};
462 +
463 +&ehci0 {
464 + status = "okay";
465 +};
466 +
467 +&emac {
468 + pinctrl-0 = <&rgmii_pe_pins>;
469 + pinctrl-names = "default";
470 + phy-handle = <&ext_rgmii_phy>;
471 + phy-mode = "rgmii-id";
472 + phy-supply = <&reg_vcc_3v3>;
473 + status = "okay";
474 +};
475 +
476 +&mdio {
477 + ext_rgmii_phy: ethernet-phy@1 {
478 + compatible = "ethernet-phy-ieee802.3-c22";
479 + reg = <1>;
480 + };
481 +};
482 +
483 +&mmc0 {
484 + broken-cd;
485 + bus-width = <4>;
486 + disable-wp;
487 + vmmc-supply = <&reg_vcc_3v3>;
488 + vqmmc-supply = <&reg_vcc_3v3>;
489 + pinctrl-0 = <&mmc0_pins>;
490 + pinctrl-names = "default";
491 + status = "okay";
492 +};
493 +
494 +&ohci0 {
495 + status = "okay";
496 +};
497 +
498 +&uart0 {
499 + pinctrl-0 = <&uart0_pb8_pins>;
500 + pinctrl-names = "default";
501 + status = "okay";
502 +};
503 +
504 +&usb_otg {
505 + dr_mode = "otg";
506 + status = "okay";
507 +};
508 +
509 +&usbphy {
510 + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
511 + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
512 + usb0_vbus-supply = <&reg_usbvbus>;
513 + status = "okay";
514 +};
515 --- /dev/null
516 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
517 @@ -0,0 +1,29 @@
518 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
519 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
520 +
521 +#include "sun20i-d1-lichee-rv-86-panel.dtsi"
522 +
523 +/ {
524 + model = "Sipeed Lichee RV 86 Panel (480p)";
525 + compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
526 + "allwinner,sun20i-d1";
527 +};
528 +
529 +&i2c2 {
530 + pinctrl-0 = <&i2c2_pb0_pins>;
531 + pinctrl-names = "default";
532 + status = "okay";
533 +
534 + touchscreen@48 {
535 + compatible = "focaltech,ft6236";
536 + reg = <0x48>;
537 + interrupt-parent = <&pio>;
538 + interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
539 + iovcc-supply = <&reg_vcc_3v3>;
540 + reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
541 + touchscreen-size-x = <480>;
542 + touchscreen-size-y = <480>;
543 + vcc-supply = <&reg_vcc_3v3>;
544 + wakeup-source;
545 + };
546 +};
547 --- /dev/null
548 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-720p.dts
549 @@ -0,0 +1,10 @@
550 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
551 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
552 +
553 +#include "sun20i-d1-lichee-rv-86-panel.dtsi"
554 +
555 +/ {
556 + model = "Sipeed Lichee RV 86 Panel (720p)";
557 + compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
558 + "allwinner,sun20i-d1";
559 +};
560 --- /dev/null
561 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
562 @@ -0,0 +1,92 @@
563 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
564 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
565 +
566 +#include "sun20i-d1-lichee-rv.dts"
567 +
568 +/ {
569 + aliases {
570 + ethernet0 = &emac;
571 + ethernet1 = &xr829;
572 + };
573 +
574 + /* PC1 is repurposed as BT_WAKE_AP */
575 + /delete-node/ leds;
576 +
577 + wifi_pwrseq: wifi-pwrseq {
578 + compatible = "mmc-pwrseq-simple";
579 + clocks = <&ccu CLK_FANOUT1>;
580 + clock-names = "ext_clock";
581 + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
582 + assigned-clocks = <&ccu CLK_FANOUT1>;
583 + assigned-clock-rates = <32768>;
584 + pinctrl-0 = <&clk_pg11_pin>;
585 + pinctrl-names = "default";
586 + };
587 +};
588 +
589 +&ehci1 {
590 + status = "okay";
591 +};
592 +
593 +&emac {
594 + pinctrl-0 = <&rmii_pe_pins>;
595 + pinctrl-names = "default";
596 + phy-handle = <&ext_rmii_phy>;
597 + phy-mode = "rmii";
598 + phy-supply = <&reg_vcc_3v3>;
599 + status = "okay";
600 +};
601 +
602 +&mdio {
603 + ext_rmii_phy: ethernet-phy@1 {
604 + compatible = "ethernet-phy-ieee802.3-c22";
605 + reg = <1>;
606 + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
607 + };
608 +};
609 +
610 +&mmc1 {
611 + bus-width = <4>;
612 + mmc-pwrseq = <&wifi_pwrseq>;
613 + non-removable;
614 + vmmc-supply = <&reg_vcc_3v3>;
615 + vqmmc-supply = <&reg_vcc_3v3>;
616 + pinctrl-0 = <&mmc1_pins>;
617 + pinctrl-names = "default";
618 + status = "okay";
619 +
620 + xr829: wifi@1 {
621 + reg = <1>;
622 + };
623 +};
624 +
625 +&ohci1 {
626 + status = "okay";
627 +};
628 +
629 +&pio {
630 + clk_pg11_pin: clk-pg11-pin {
631 + pins = "PG11";
632 + function = "clk";
633 + };
634 +};
635 +
636 +&uart1 {
637 + uart-has-rtscts;
638 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
639 + pinctrl-names = "default";
640 + status = "okay";
641 +
642 + /* XR829 bluetooth is connected here */
643 +};
644 +
645 +&usb_otg {
646 + status = "disabled";
647 +};
648 +
649 +&usbphy {
650 + /* PD20 and PD21 are repurposed for the LCD panel */
651 + /delete-property/ usb0_id_det-gpios;
652 + /delete-property/ usb0_vbus_det-gpios;
653 + usb1_vbus-supply = <&reg_vcc>;
654 +};
655 --- /dev/null
656 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
657 @@ -0,0 +1,74 @@
658 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
659 +// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
660 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
661 +
662 +#include <dt-bindings/input/input.h>
663 +
664 +#include "sun20i-d1-lichee-rv.dts"
665 +
666 +/ {
667 + model = "Sipeed Lichee RV Dock";
668 + compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
669 + "allwinner,sun20i-d1";
670 +
671 + aliases {
672 + ethernet1 = &rtl8723ds;
673 + };
674 +
675 + wifi_pwrseq: wifi-pwrseq {
676 + compatible = "mmc-pwrseq-simple";
677 + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
678 + };
679 +};
680 +
681 +&ehci1 {
682 + status = "okay";
683 +};
684 +
685 +&lradc {
686 + status = "okay";
687 +
688 + button-220 {
689 + label = "OK";
690 + linux,code = <KEY_OK>;
691 + channel = <0>;
692 + voltage = <220000>;
693 + };
694 +};
695 +
696 +&mmc1 {
697 + bus-width = <4>;
698 + mmc-pwrseq = <&wifi_pwrseq>;
699 + non-removable;
700 + vmmc-supply = <&reg_vcc_3v3>;
701 + vqmmc-supply = <&reg_vcc_3v3>;
702 + pinctrl-0 = <&mmc1_pins>;
703 + pinctrl-names = "default";
704 + status = "okay";
705 +
706 + rtl8723ds: wifi@1 {
707 + reg = <1>;
708 + };
709 +};
710 +
711 +&ohci1 {
712 + status = "okay";
713 +};
714 +
715 +&uart1 {
716 + uart-has-rtscts;
717 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
718 + pinctrl-names = "default";
719 + status = "okay";
720 +
721 + bluetooth {
722 + compatible = "realtek,rtl8723ds-bt";
723 + device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
724 + enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
725 + host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
726 + };
727 +};
728 +
729 +&usbphy {
730 + usb1_vbus-supply = <&reg_vcc>;
731 +};
732 --- /dev/null
733 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv.dts
734 @@ -0,0 +1,84 @@
735 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
736 +// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
737 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
738 +
739 +/dts-v1/;
740 +
741 +#include <dt-bindings/gpio/gpio.h>
742 +#include <dt-bindings/leds/common.h>
743 +
744 +#include "sun20i-d1.dtsi"
745 +#include "sun20i-d1-common-regulators.dtsi"
746 +
747 +/ {
748 + model = "Sipeed Lichee RV";
749 + compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
750 +
751 + aliases {
752 + mmc0 = &mmc0;
753 + serial0 = &uart0;
754 + };
755 +
756 + chosen {
757 + stdout-path = "serial0:115200n8";
758 + };
759 +
760 + leds {
761 + compatible = "gpio-leds";
762 +
763 + led-0 {
764 + color = <LED_COLOR_ID_GREEN>;
765 + function = LED_FUNCTION_STATUS;
766 + gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
767 + };
768 + };
769 +
770 + reg_vdd_cpu: vdd-cpu {
771 + compatible = "regulator-fixed";
772 + regulator-name = "vdd-cpu";
773 + regulator-min-microvolt = <900000>;
774 + regulator-max-microvolt = <900000>;
775 + vin-supply = <&reg_vcc>;
776 + };
777 +};
778 +
779 +&cpu0 {
780 + cpu-supply = <&reg_vdd_cpu>;
781 +};
782 +
783 +&ehci0 {
784 + status = "okay";
785 +};
786 +
787 +&mmc0 {
788 + broken-cd;
789 + bus-width = <4>;
790 + disable-wp;
791 + vmmc-supply = <&reg_vcc_3v3>;
792 + vqmmc-supply = <&reg_vcc_3v3>;
793 + pinctrl-0 = <&mmc0_pins>;
794 + pinctrl-names = "default";
795 + status = "okay";
796 +};
797 +
798 +&ohci0 {
799 + status = "okay";
800 +};
801 +
802 +&uart0 {
803 + pinctrl-0 = <&uart0_pb8_pins>;
804 + pinctrl-names = "default";
805 + status = "okay";
806 +};
807 +
808 +&usb_otg {
809 + dr_mode = "otg";
810 + status = "okay";
811 +};
812 +
813 +&usbphy {
814 + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
815 + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
816 + usb0_vbus-supply = <&reg_vcc>;
817 + status = "okay";
818 +};
819 --- /dev/null
820 +++ b/arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
821 @@ -0,0 +1,128 @@
822 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
823 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
824 +
825 +/dts-v1/;
826 +
827 +#include <dt-bindings/gpio/gpio.h>
828 +
829 +#include "sun20i-d1.dtsi"
830 +#include "sun20i-d1-common-regulators.dtsi"
831 +
832 +/ {
833 + model = "MangoPi MQ Pro";
834 + compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
835 +
836 + aliases {
837 + ethernet0 = &rtl8723ds;
838 + mmc0 = &mmc0;
839 + serial0 = &uart0;
840 + };
841 +
842 + chosen {
843 + stdout-path = "serial0:115200n8";
844 + };
845 +
846 + reg_avdd2v8: avdd2v8 {
847 + compatible = "regulator-fixed";
848 + regulator-name = "avdd2v8";
849 + regulator-min-microvolt = <2800000>;
850 + regulator-max-microvolt = <2800000>;
851 + vin-supply = <&reg_vcc_3v3>;
852 + };
853 +
854 + reg_dvdd: dvdd {
855 + compatible = "regulator-fixed";
856 + regulator-name = "dvdd";
857 + regulator-min-microvolt = <1200000>;
858 + regulator-max-microvolt = <1200000>;
859 + vin-supply = <&reg_vcc_3v3>;
860 + };
861 +
862 + reg_vdd_cpu: vdd-cpu {
863 + compatible = "regulator-fixed";
864 + regulator-name = "vdd-cpu";
865 + regulator-min-microvolt = <1100000>;
866 + regulator-max-microvolt = <1100000>;
867 + vin-supply = <&reg_vcc>;
868 + };
869 +
870 + wifi_pwrseq: wifi-pwrseq {
871 + compatible = "mmc-pwrseq-simple";
872 + reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
873 + };
874 +};
875 +
876 +&cpu0 {
877 + cpu-supply = <&reg_vdd_cpu>;
878 +};
879 +
880 +&ehci1 {
881 + status = "okay";
882 +};
883 +
884 +&mmc0 {
885 + bus-width = <4>;
886 + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
887 + disable-wp;
888 + vmmc-supply = <&reg_vcc_3v3>;
889 + vqmmc-supply = <&reg_vcc_3v3>;
890 + pinctrl-0 = <&mmc0_pins>;
891 + pinctrl-names = "default";
892 + status = "okay";
893 +};
894 +
895 +&mmc1 {
896 + bus-width = <4>;
897 + mmc-pwrseq = <&wifi_pwrseq>;
898 + non-removable;
899 + vmmc-supply = <&reg_vcc_3v3>;
900 + vqmmc-supply = <&reg_vcc_3v3>;
901 + pinctrl-0 = <&mmc1_pins>;
902 + pinctrl-names = "default";
903 + status = "okay";
904 +
905 + rtl8723ds: wifi@1 {
906 + reg = <1>;
907 + interrupt-parent = <&pio>;
908 + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
909 + interrupt-names = "host-wake";
910 + };
911 +};
912 +
913 +&ohci1 {
914 + status = "okay";
915 +};
916 +
917 +&pio {
918 + vcc-pe-supply = <&reg_avdd2v8>;
919 +};
920 +
921 +&uart0 {
922 + pinctrl-0 = <&uart0_pb8_pins>;
923 + pinctrl-names = "default";
924 + status = "okay";
925 +};
926 +
927 +&uart1 {
928 + uart-has-rtscts;
929 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
930 + pinctrl-names = "default";
931 + status = "okay";
932 +
933 + bluetooth {
934 + compatible = "realtek,rtl8723ds-bt";
935 + device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
936 + enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
937 + host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
938 + };
939 +};
940 +
941 +&usb_otg {
942 + dr_mode = "peripheral";
943 + status = "okay";
944 +};
945 +
946 +&usbphy {
947 + usb0_vbus-supply = <&reg_vcc>;
948 + status = "okay";
949 +};
950 --- /dev/null
951 +++ b/arch/riscv/dts/sun20i-d1-nezha.dts
952 @@ -0,0 +1,171 @@
953 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
954 +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
955 +
956 +/dts-v1/;
957 +
958 +#include <dt-bindings/gpio/gpio.h>
959 +#include <dt-bindings/input/input.h>
960 +
961 +#include "sun20i-d1.dtsi"
962 +#include "sun20i-d1-common-regulators.dtsi"
963 +
964 +/ {
965 + model = "Allwinner D1 Nezha";
966 + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
967 +
968 + aliases {
969 + ethernet0 = &emac;
970 + ethernet1 = &xr829;
971 + mmc0 = &mmc0;
972 + serial0 = &uart0;
973 + };
974 +
975 + chosen {
976 + stdout-path = "serial0:115200n8";
977 + };
978 +
979 + reg_usbvbus: usbvbus {
980 + compatible = "regulator-fixed";
981 + regulator-name = "usbvbus";
982 + regulator-min-microvolt = <5000000>;
983 + regulator-max-microvolt = <5000000>;
984 + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
985 + enable-active-high;
986 + vin-supply = <&reg_vcc>;
987 + };
988 +
989 + /*
990 + * This regulator is PWM-controlled, but the PWM controller is not
991 + * yet supported, so fix the regulator to its default voltage.
992 + */
993 + reg_vdd_cpu: vdd-cpu {
994 + compatible = "regulator-fixed";
995 + regulator-name = "vdd-cpu";
996 + regulator-min-microvolt = <1100000>;
997 + regulator-max-microvolt = <1100000>;
998 + vin-supply = <&reg_vcc>;
999 + };
1000 +
1001 + wifi_pwrseq: wifi-pwrseq {
1002 + compatible = "mmc-pwrseq-simple";
1003 + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
1004 + };
1005 +};
1006 +
1007 +&cpu0 {
1008 + cpu-supply = <&reg_vdd_cpu>;
1009 +};
1010 +
1011 +&ehci0 {
1012 + status = "okay";
1013 +};
1014 +
1015 +&ehci1 {
1016 + status = "okay";
1017 +};
1018 +
1019 +&emac {
1020 + pinctrl-0 = <&rgmii_pe_pins>;
1021 + pinctrl-names = "default";
1022 + phy-handle = <&ext_rgmii_phy>;
1023 + phy-mode = "rgmii-id";
1024 + phy-supply = <&reg_vcc_3v3>;
1025 + status = "okay";
1026 +};
1027 +
1028 +&i2c2 {
1029 + pinctrl-0 = <&i2c2_pb0_pins>;
1030 + pinctrl-names = "default";
1031 + status = "okay";
1032 +
1033 + pcf8574a: gpio@38 {
1034 + compatible = "nxp,pcf8574a";
1035 + reg = <0x38>;
1036 + interrupt-parent = <&pio>;
1037 + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
1038 + interrupt-controller;
1039 + gpio-controller;
1040 + #gpio-cells = <2>;
1041 + #interrupt-cells = <2>;
1042 + };
1043 +};
1044 +
1045 +&lradc {
1046 + status = "okay";
1047 +
1048 + button-160 {
1049 + label = "OK";
1050 + linux,code = <KEY_OK>;
1051 + channel = <0>;
1052 + voltage = <160000>;
1053 + };
1054 +};
1055 +
1056 +&mdio {
1057 + ext_rgmii_phy: ethernet-phy@1 {
1058 + compatible = "ethernet-phy-ieee802.3-c22";
1059 + reg = <1>;
1060 + };
1061 +};
1062 +
1063 +&mmc0 {
1064 + bus-width = <4>;
1065 + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
1066 + disable-wp;
1067 + vmmc-supply = <&reg_vcc_3v3>;
1068 + vqmmc-supply = <&reg_vcc_3v3>;
1069 + pinctrl-0 = <&mmc0_pins>;
1070 + pinctrl-names = "default";
1071 + status = "okay";
1072 +};
1073 +
1074 +&mmc1 {
1075 + bus-width = <4>;
1076 + mmc-pwrseq = <&wifi_pwrseq>;
1077 + non-removable;
1078 + vmmc-supply = <&reg_vcc_3v3>;
1079 + vqmmc-supply = <&reg_vcc_3v3>;
1080 + pinctrl-0 = <&mmc1_pins>;
1081 + pinctrl-names = "default";
1082 + status = "okay";
1083 +
1084 + xr829: wifi@1 {
1085 + reg = <1>;
1086 + };
1087 +};
1088 +
1089 +&ohci0 {
1090 + status = "okay";
1091 +};
1092 +
1093 +&ohci1 {
1094 + status = "okay";
1095 +};
1096 +
1097 +&uart0 {
1098 + pinctrl-0 = <&uart0_pb8_pins>;
1099 + pinctrl-names = "default";
1100 + status = "okay";
1101 +};
1102 +
1103 +&uart1 {
1104 + uart-has-rtscts;
1105 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
1106 + pinctrl-names = "default";
1107 + status = "okay";
1108 +
1109 + /* XR829 bluetooth is connected here */
1110 +};
1111 +
1112 +&usb_otg {
1113 + dr_mode = "otg";
1114 + status = "okay";
1115 +};
1116 +
1117 +&usbphy {
1118 + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
1119 + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
1120 + usb0_vbus-supply = <&reg_usbvbus>;
1121 + usb1_vbus-supply = <&reg_vcc>;
1122 + status = "okay";
1123 +};
1124 --- /dev/null
1125 +++ b/arch/riscv/dts/sun20i-d1.dtsi
1126 @@ -0,0 +1,900 @@
1127 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
1128 +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
1129 +
1130 +#include <dt-bindings/clock/sun6i-rtc.h>
1131 +#include <dt-bindings/clock/sun8i-de2.h>
1132 +#include <dt-bindings/clock/sun8i-tcon-top.h>
1133 +#include <dt-bindings/clock/sun20i-d1-ccu.h>
1134 +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
1135 +#include <dt-bindings/interrupt-controller/irq.h>
1136 +#include <dt-bindings/reset/sun8i-de2.h>
1137 +#include <dt-bindings/reset/sun20i-d1-ccu.h>
1138 +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
1139 +#include <dt-bindings/thermal/thermal.h>
1140 +
1141 +/ {
1142 + #address-cells = <1>;
1143 + #size-cells = <1>;
1144 +
1145 + cpus {
1146 + timebase-frequency = <24000000>;
1147 + #address-cells = <1>;
1148 + #size-cells = <0>;
1149 +
1150 + cpu0: cpu@0 {
1151 + compatible = "thead,c906", "riscv";
1152 + device_type = "cpu";
1153 + reg = <0>;
1154 + clocks = <&ccu CLK_RISCV>;
1155 + clock-frequency = <24000000>;
1156 + d-cache-block-size = <64>;
1157 + d-cache-sets = <256>;
1158 + d-cache-size = <32768>;
1159 + i-cache-block-size = <64>;
1160 + i-cache-sets = <128>;
1161 + i-cache-size = <32768>;
1162 + mmu-type = "riscv,sv39";
1163 + riscv,isa = "rv64imafdc";
1164 + #cooling-cells = <2>;
1165 +
1166 + cpu0_intc: interrupt-controller {
1167 + compatible = "riscv,cpu-intc";
1168 + interrupt-controller;
1169 + #address-cells = <0>;
1170 + #interrupt-cells = <1>;
1171 + };
1172 + };
1173 + };
1174 +
1175 + de: display-engine {
1176 + compatible = "allwinner,sun20i-d1-display-engine";
1177 + allwinner,pipelines = <&mixer0>, <&mixer1>;
1178 + status = "disabled";
1179 + };
1180 +
1181 + osc24M: osc24M-clk {
1182 + compatible = "fixed-clock";
1183 + clock-frequency = <24000000>;
1184 + clock-output-names = "osc24M";
1185 + #clock-cells = <0>;
1186 + };
1187 +
1188 + soc {
1189 + compatible = "simple-bus";
1190 + ranges;
1191 + interrupt-parent = <&plic>;
1192 + dma-noncoherent;
1193 + #address-cells = <1>;
1194 + #size-cells = <1>;
1195 +
1196 + dsp_wdt: watchdog@1700400 {
1197 + compatible = "allwinner,sun20i-d1-wdt";
1198 + reg = <0x1700400 0x20>;
1199 + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
1200 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
1201 + clock-names = "hosc", "losc";
1202 + status = "reserved";
1203 + };
1204 +
1205 + pio: pinctrl@2000000 {
1206 + compatible = "allwinner,sun20i-d1-pinctrl";
1207 + reg = <0x2000000 0x800>;
1208 + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
1209 + <87 IRQ_TYPE_LEVEL_HIGH>,
1210 + <89 IRQ_TYPE_LEVEL_HIGH>,
1211 + <91 IRQ_TYPE_LEVEL_HIGH>,
1212 + <93 IRQ_TYPE_LEVEL_HIGH>,
1213 + <95 IRQ_TYPE_LEVEL_HIGH>;
1214 + clocks = <&ccu CLK_APB0>,
1215 + <&osc24M>,
1216 + <&rtc CLK_OSC32K>;
1217 + clock-names = "apb", "hosc", "losc";
1218 + gpio-controller;
1219 + interrupt-controller;
1220 + #gpio-cells = <3>;
1221 + #interrupt-cells = <3>;
1222 +
1223 + /omit-if-no-ref/
1224 + i2c0_pb10_pins: i2c0-pb10-pins {
1225 + pins = "PB10", "PB11";
1226 + function = "i2c0";
1227 + };
1228 +
1229 + /omit-if-no-ref/
1230 + i2c2_pb0_pins: i2c2-pb0-pins {
1231 + pins = "PB0", "PB1";
1232 + function = "i2c2";
1233 + };
1234 +
1235 + /omit-if-no-ref/
1236 + lcd_rgb666_pins: lcd-rgb666-pins {
1237 + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
1238 + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
1239 + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
1240 + "PD18", "PD19", "PD20", "PD21";
1241 + function = "lcd0";
1242 + };
1243 +
1244 + /omit-if-no-ref/
1245 + mmc0_pins: mmc0-pins {
1246 + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
1247 + function = "mmc0";
1248 + };
1249 +
1250 + /omit-if-no-ref/
1251 + mmc1_pins: mmc1-pins {
1252 + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
1253 + function = "mmc1";
1254 + };
1255 +
1256 + /omit-if-no-ref/
1257 + mmc2_pins: mmc2-pins {
1258 + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
1259 + function = "mmc2";
1260 + };
1261 +
1262 + /omit-if-no-ref/
1263 + rgmii_pe_pins: rgmii-pe-pins {
1264 + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
1265 + "PE5", "PE6", "PE7", "PE8", "PE9",
1266 + "PE11", "PE12", "PE13", "PE14", "PE15";
1267 + function = "emac";
1268 + };
1269 +
1270 + /omit-if-no-ref/
1271 + rmii_pe_pins: rmii-pe-pins {
1272 + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
1273 + "PE5", "PE6", "PE7", "PE8", "PE9";
1274 + function = "emac";
1275 + };
1276 +
1277 + /omit-if-no-ref/
1278 + uart0_pb8_pins: uart0-pb8-pins {
1279 + pins = "PB8", "PB9";
1280 + function = "uart0";
1281 + };
1282 +
1283 + /omit-if-no-ref/
1284 + uart1_pg6_pins: uart1-pg6-pins {
1285 + pins = "PG6", "PG7";
1286 + function = "uart1";
1287 + };
1288 +
1289 + /omit-if-no-ref/
1290 + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
1291 + pins = "PG8", "PG9";
1292 + function = "uart1";
1293 + };
1294 + };
1295 +
1296 + ccu: clock-controller@2001000 {
1297 + compatible = "allwinner,sun20i-d1-ccu";
1298 + reg = <0x2001000 0x1000>;
1299 + clocks = <&osc24M>,
1300 + <&rtc CLK_OSC32K>,
1301 + <&rtc CLK_IOSC>;
1302 + clock-names = "hosc", "losc", "iosc";
1303 + #clock-cells = <1>;
1304 + #reset-cells = <1>;
1305 + };
1306 +
1307 + lradc: keys@2009800 {
1308 + compatible = "allwinner,sun20i-d1-lradc",
1309 + "allwinner,sun50i-r329-lradc";
1310 + reg = <0x2009800 0x400>;
1311 + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
1312 + clocks = <&ccu CLK_BUS_LRADC>;
1313 + resets = <&ccu RST_BUS_LRADC>;
1314 + status = "disabled";
1315 + };
1316 +
1317 + codec: audio-codec@2030000 {
1318 + compatible = "simple-mfd", "syscon";
1319 + reg = <0x2030000 0x1000>;
1320 + #address-cells = <1>;
1321 + #size-cells = <1>;
1322 +
1323 + regulators@2030348 {
1324 + compatible = "allwinner,sun20i-d1-analog-ldos";
1325 + reg = <0x2030348 0x4>;
1326 + nvmem-cells = <&bg_trim>;
1327 + nvmem-cell-names = "bg_trim";
1328 +
1329 + reg_aldo: aldo {
1330 + };
1331 +
1332 + reg_hpldo: hpldo {
1333 + };
1334 + };
1335 + };
1336 +
1337 + i2s0: i2s@2032000 {
1338 + compatible = "allwinner,sun20i-d1-i2s",
1339 + "allwinner,sun50i-r329-i2s";
1340 + reg = <0x2032000 0x1000>;
1341 + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
1342 + clocks = <&ccu CLK_BUS_I2S0>,
1343 + <&ccu CLK_I2S0>;
1344 + clock-names = "apb", "mod";
1345 + resets = <&ccu RST_BUS_I2S0>;
1346 + dmas = <&dma 3>, <&dma 3>;
1347 + dma-names = "rx", "tx";
1348 + status = "disabled";
1349 + #sound-dai-cells = <0>;
1350 + };
1351 +
1352 + i2s1: i2s@2033000 {
1353 + compatible = "allwinner,sun20i-d1-i2s",
1354 + "allwinner,sun50i-r329-i2s";
1355 + reg = <0x2033000 0x1000>;
1356 + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
1357 + clocks = <&ccu CLK_BUS_I2S1>,
1358 + <&ccu CLK_I2S1>;
1359 + clock-names = "apb", "mod";
1360 + resets = <&ccu RST_BUS_I2S1>;
1361 + dmas = <&dma 4>, <&dma 4>;
1362 + dma-names = "rx", "tx";
1363 + status = "disabled";
1364 + #sound-dai-cells = <0>;
1365 + };
1366 +
1367 + i2s2: i2s@2034000 {
1368 + compatible = "allwinner,sun20i-d1-i2s",
1369 + "allwinner,sun50i-r329-i2s";
1370 + reg = <0x2034000 0x1000>;
1371 + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
1372 + clocks = <&ccu CLK_BUS_I2S2>,
1373 + <&ccu CLK_I2S2>;
1374 + clock-names = "apb", "mod";
1375 + resets = <&ccu RST_BUS_I2S2>;
1376 + dmas = <&dma 5>, <&dma 5>;
1377 + dma-names = "rx", "tx";
1378 + status = "disabled";
1379 + #sound-dai-cells = <0>;
1380 + };
1381 +
1382 + timer: timer@2050000 {
1383 + compatible = "allwinner,sun20i-d1-timer",
1384 + "allwinner,sun8i-a23-timer";
1385 + reg = <0x2050000 0xa0>;
1386 + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
1387 + <76 IRQ_TYPE_LEVEL_HIGH>;
1388 + clocks = <&osc24M>;
1389 + };
1390 +
1391 + wdt: watchdog@20500a0 {
1392 + compatible = "allwinner,sun20i-d1-wdt-reset",
1393 + "allwinner,sun20i-d1-wdt";
1394 + reg = <0x20500a0 0x20>;
1395 + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
1396 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
1397 + clock-names = "hosc", "losc";
1398 + status = "reserved";
1399 + };
1400 +
1401 + uart0: serial@2500000 {
1402 + compatible = "snps,dw-apb-uart";
1403 + reg = <0x2500000 0x400>;
1404 + reg-io-width = <4>;
1405 + reg-shift = <2>;
1406 + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
1407 + clocks = <&ccu CLK_BUS_UART0>;
1408 + resets = <&ccu RST_BUS_UART0>;
1409 + dmas = <&dma 14>, <&dma 14>;
1410 + dma-names = "rx", "tx";
1411 + status = "disabled";
1412 + };
1413 +
1414 + uart1: serial@2500400 {
1415 + compatible = "snps,dw-apb-uart";
1416 + reg = <0x2500400 0x400>;
1417 + reg-io-width = <4>;
1418 + reg-shift = <2>;
1419 + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
1420 + clocks = <&ccu CLK_BUS_UART1>;
1421 + resets = <&ccu RST_BUS_UART1>;
1422 + dmas = <&dma 15>, <&dma 15>;
1423 + dma-names = "rx", "tx";
1424 + status = "disabled";
1425 + };
1426 +
1427 + uart2: serial@2500800 {
1428 + compatible = "snps,dw-apb-uart";
1429 + reg = <0x2500800 0x400>;
1430 + reg-io-width = <4>;
1431 + reg-shift = <2>;
1432 + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
1433 + clocks = <&ccu CLK_BUS_UART2>;
1434 + resets = <&ccu RST_BUS_UART2>;
1435 + dmas = <&dma 16>, <&dma 16>;
1436 + dma-names = "rx", "tx";
1437 + status = "disabled";
1438 + };
1439 +
1440 + uart3: serial@2500c00 {
1441 + compatible = "snps,dw-apb-uart";
1442 + reg = <0x2500c00 0x400>;
1443 + reg-io-width = <4>;
1444 + reg-shift = <2>;
1445 + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
1446 + clocks = <&ccu CLK_BUS_UART3>;
1447 + resets = <&ccu RST_BUS_UART3>;
1448 + dmas = <&dma 17>, <&dma 17>;
1449 + dma-names = "rx", "tx";
1450 + status = "disabled";
1451 + };
1452 +
1453 + uart4: serial@2501000 {
1454 + compatible = "snps,dw-apb-uart";
1455 + reg = <0x2501000 0x400>;
1456 + reg-io-width = <4>;
1457 + reg-shift = <2>;
1458 + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
1459 + clocks = <&ccu CLK_BUS_UART4>;
1460 + resets = <&ccu RST_BUS_UART4>;
1461 + dmas = <&dma 18>, <&dma 18>;
1462 + dma-names = "rx", "tx";
1463 + status = "disabled";
1464 + };
1465 +
1466 + uart5: serial@2501400 {
1467 + compatible = "snps,dw-apb-uart";
1468 + reg = <0x2501400 0x400>;
1469 + reg-io-width = <4>;
1470 + reg-shift = <2>;
1471 + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
1472 + clocks = <&ccu CLK_BUS_UART5>;
1473 + resets = <&ccu RST_BUS_UART5>;
1474 + dmas = <&dma 19>, <&dma 19>;
1475 + dma-names = "rx", "tx";
1476 + status = "disabled";
1477 + };
1478 +
1479 + i2c0: i2c@2502000 {
1480 + compatible = "allwinner,sun20i-d1-i2c",
1481 + "allwinner,sun8i-v536-i2c",
1482 + "allwinner,sun6i-a31-i2c";
1483 + reg = <0x2502000 0x400>;
1484 + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
1485 + clocks = <&ccu CLK_BUS_I2C0>;
1486 + resets = <&ccu RST_BUS_I2C0>;
1487 + dmas = <&dma 43>, <&dma 43>;
1488 + dma-names = "rx", "tx";
1489 + status = "disabled";
1490 + #address-cells = <1>;
1491 + #size-cells = <0>;
1492 + };
1493 +
1494 + i2c1: i2c@2502400 {
1495 + compatible = "allwinner,sun20i-d1-i2c",
1496 + "allwinner,sun8i-v536-i2c",
1497 + "allwinner,sun6i-a31-i2c";
1498 + reg = <0x2502400 0x400>;
1499 + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
1500 + clocks = <&ccu CLK_BUS_I2C1>;
1501 + resets = <&ccu RST_BUS_I2C1>;
1502 + dmas = <&dma 44>, <&dma 44>;
1503 + dma-names = "rx", "tx";
1504 + status = "disabled";
1505 + #address-cells = <1>;
1506 + #size-cells = <0>;
1507 + };
1508 +
1509 + i2c2: i2c@2502800 {
1510 + compatible = "allwinner,sun20i-d1-i2c",
1511 + "allwinner,sun8i-v536-i2c",
1512 + "allwinner,sun6i-a31-i2c";
1513 + reg = <0x2502800 0x400>;
1514 + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
1515 + clocks = <&ccu CLK_BUS_I2C2>;
1516 + resets = <&ccu RST_BUS_I2C2>;
1517 + dmas = <&dma 45>, <&dma 45>;
1518 + dma-names = "rx", "tx";
1519 + status = "disabled";
1520 + #address-cells = <1>;
1521 + #size-cells = <0>;
1522 + };
1523 +
1524 + i2c3: i2c@2502c00 {
1525 + compatible = "allwinner,sun20i-d1-i2c",
1526 + "allwinner,sun8i-v536-i2c",
1527 + "allwinner,sun6i-a31-i2c";
1528 + reg = <0x2502c00 0x400>;
1529 + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
1530 + clocks = <&ccu CLK_BUS_I2C3>;
1531 + resets = <&ccu RST_BUS_I2C3>;
1532 + dmas = <&dma 46>, <&dma 46>;
1533 + dma-names = "rx", "tx";
1534 + status = "disabled";
1535 + #address-cells = <1>;
1536 + #size-cells = <0>;
1537 + };
1538 +
1539 + syscon: syscon@3000000 {
1540 + compatible = "allwinner,sun20i-d1-system-control";
1541 + reg = <0x3000000 0x1000>;
1542 + ranges;
1543 + #address-cells = <1>;
1544 + #size-cells = <1>;
1545 +
1546 + regulators@3000150 {
1547 + compatible = "allwinner,sun20i-d1-system-ldos";
1548 + reg = <0x3000150 0x4>;
1549 +
1550 + reg_ldoa: ldoa {
1551 + };
1552 +
1553 + reg_ldob: ldob {
1554 + };
1555 + };
1556 + };
1557 +
1558 + dma: dma-controller@3002000 {
1559 + compatible = "allwinner,sun20i-d1-dma";
1560 + reg = <0x3002000 0x1000>;
1561 + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
1562 + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
1563 + clock-names = "bus", "mbus";
1564 + resets = <&ccu RST_BUS_DMA>;
1565 + dma-channels = <16>;
1566 + dma-requests = <48>;
1567 + #dma-cells = <1>;
1568 + };
1569 +
1570 + sid: efuse@3006000 {
1571 + compatible = "allwinner,sun20i-d1-sid";
1572 + reg = <0x3006000 0x1000>;
1573 + #address-cells = <1>;
1574 + #size-cells = <1>;
1575 +
1576 + ths_calib: ths-calib@14 {
1577 + reg = <0x14 0x4>;
1578 + };
1579 +
1580 + bg_trim: bg-trim@28 {
1581 + reg = <0x28 0x4>;
1582 + bits = <16 8>;
1583 + };
1584 + };
1585 +
1586 + mbus: dram-controller@3102000 {
1587 + compatible = "allwinner,sun20i-d1-mbus";
1588 + reg = <0x3102000 0x1000>,
1589 + <0x3103000 0x1000>;
1590 + reg-names = "mbus", "dram";
1591 + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
1592 + clocks = <&ccu CLK_MBUS>,
1593 + <&ccu CLK_DRAM>,
1594 + <&ccu CLK_BUS_DRAM>;
1595 + clock-names = "mbus", "dram", "bus";
1596 + dma-ranges = <0 0x40000000 0x80000000>;
1597 + #address-cells = <1>;
1598 + #size-cells = <1>;
1599 + #interconnect-cells = <1>;
1600 + };
1601 +
1602 + mmc0: mmc@4020000 {
1603 + compatible = "allwinner,sun20i-d1-mmc";
1604 + reg = <0x4020000 0x1000>;
1605 + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
1606 + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
1607 + clock-names = "ahb", "mmc";
1608 + resets = <&ccu RST_BUS_MMC0>;
1609 + reset-names = "ahb";
1610 + cap-sd-highspeed;
1611 + max-frequency = <150000000>;
1612 + no-mmc;
1613 + status = "disabled";
1614 + #address-cells = <1>;
1615 + #size-cells = <0>;
1616 + };
1617 +
1618 + mmc1: mmc@4021000 {
1619 + compatible = "allwinner,sun20i-d1-mmc";
1620 + reg = <0x4021000 0x1000>;
1621 + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
1622 + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
1623 + clock-names = "ahb", "mmc";
1624 + resets = <&ccu RST_BUS_MMC1>;
1625 + reset-names = "ahb";
1626 + cap-sd-highspeed;
1627 + max-frequency = <150000000>;
1628 + no-mmc;
1629 + status = "disabled";
1630 + #address-cells = <1>;
1631 + #size-cells = <0>;
1632 + };
1633 +
1634 + mmc2: mmc@4022000 {
1635 + compatible = "allwinner,sun20i-d1-emmc",
1636 + "allwinner,sun50i-a100-emmc";
1637 + reg = <0x4022000 0x1000>;
1638 + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
1639 + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
1640 + clock-names = "ahb", "mmc";
1641 + resets = <&ccu RST_BUS_MMC2>;
1642 + reset-names = "ahb";
1643 + cap-mmc-highspeed;
1644 + max-frequency = <150000000>;
1645 + mmc-ddr-1_8v;
1646 + mmc-ddr-3_3v;
1647 + no-sd;
1648 + no-sdio;
1649 + status = "disabled";
1650 + #address-cells = <1>;
1651 + #size-cells = <0>;
1652 + };
1653 +
1654 + usb_otg: usb@4100000 {
1655 + compatible = "allwinner,sun20i-d1-musb",
1656 + "allwinner,sun8i-a33-musb";
1657 + reg = <0x4100000 0x400>;
1658 + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
1659 + interrupt-names = "mc";
1660 + clocks = <&ccu CLK_BUS_OTG>;
1661 + resets = <&ccu RST_BUS_OTG>;
1662 + extcon = <&usbphy 0>;
1663 + phys = <&usbphy 0>;
1664 + phy-names = "usb";
1665 + status = "disabled";
1666 + };
1667 +
1668 + usbphy: phy@4100400 {
1669 + compatible = "allwinner,sun20i-d1-usb-phy";
1670 + reg = <0x4100400 0x100>,
1671 + <0x4101800 0x100>,
1672 + <0x4200800 0x100>;
1673 + reg-names = "phy_ctrl",
1674 + "pmu0",
1675 + "pmu1";
1676 + clocks = <&osc24M>,
1677 + <&osc24M>;
1678 + clock-names = "usb0_phy",
1679 + "usb1_phy";
1680 + resets = <&ccu RST_USB_PHY0>,
1681 + <&ccu RST_USB_PHY1>;
1682 + reset-names = "usb0_reset",
1683 + "usb1_reset";
1684 + status = "disabled";
1685 + #phy-cells = <1>;
1686 + };
1687 +
1688 + ehci0: usb@4101000 {
1689 + compatible = "allwinner,sun20i-d1-ehci",
1690 + "generic-ehci";
1691 + reg = <0x4101000 0x100>;
1692 + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
1693 + clocks = <&ccu CLK_BUS_OHCI0>,
1694 + <&ccu CLK_BUS_EHCI0>,
1695 + <&ccu CLK_USB_OHCI0>;
1696 + resets = <&ccu RST_BUS_OHCI0>,
1697 + <&ccu RST_BUS_EHCI0>;
1698 + phys = <&usbphy 0>;
1699 + phy-names = "usb";
1700 + status = "disabled";
1701 + };
1702 +
1703 + ohci0: usb@4101400 {
1704 + compatible = "allwinner,sun20i-d1-ohci",
1705 + "generic-ohci";
1706 + reg = <0x4101400 0x100>;
1707 + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
1708 + clocks = <&ccu CLK_BUS_OHCI0>,
1709 + <&ccu CLK_USB_OHCI0>;
1710 + resets = <&ccu RST_BUS_OHCI0>;
1711 + phys = <&usbphy 0>;
1712 + phy-names = "usb";
1713 + status = "disabled";
1714 + };
1715 +
1716 + ehci1: usb@4200000 {
1717 + compatible = "allwinner,sun20i-d1-ehci",
1718 + "generic-ehci";
1719 + reg = <0x4200000 0x100>;
1720 + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
1721 + clocks = <&ccu CLK_BUS_OHCI1>,
1722 + <&ccu CLK_BUS_EHCI1>,
1723 + <&ccu CLK_USB_OHCI1>;
1724 + resets = <&ccu RST_BUS_OHCI1>,
1725 + <&ccu RST_BUS_EHCI1>;
1726 + phys = <&usbphy 1>;
1727 + phy-names = "usb";
1728 + status = "disabled";
1729 + };
1730 +
1731 + ohci1: usb@4200400 {
1732 + compatible = "allwinner,sun20i-d1-ohci",
1733 + "generic-ohci";
1734 + reg = <0x4200400 0x100>;
1735 + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
1736 + clocks = <&ccu CLK_BUS_OHCI1>,
1737 + <&ccu CLK_USB_OHCI1>;
1738 + resets = <&ccu RST_BUS_OHCI1>;
1739 + phys = <&usbphy 1>;
1740 + phy-names = "usb";
1741 + status = "disabled";
1742 + };
1743 +
1744 + emac: ethernet@4500000 {
1745 + compatible = "allwinner,sun20i-d1-emac",
1746 + "allwinner,sun50i-a64-emac";
1747 + reg = <0x4500000 0x10000>;
1748 + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
1749 + interrupt-names = "macirq";
1750 + clocks = <&ccu CLK_BUS_EMAC>;
1751 + clock-names = "stmmaceth";
1752 + resets = <&ccu RST_BUS_EMAC>;
1753 + reset-names = "stmmaceth";
1754 + syscon = <&syscon>;
1755 + status = "disabled";
1756 +
1757 + mdio: mdio {
1758 + compatible = "snps,dwmac-mdio";
1759 + #address-cells = <1>;
1760 + #size-cells = <0>;
1761 + };
1762 + };
1763 +
1764 + display_clocks: clock-controller@5000000 {
1765 + compatible = "allwinner,sun20i-d1-de2-clk",
1766 + "allwinner,sun50i-h5-de2-clk";
1767 + reg = <0x5000000 0x10000>;
1768 + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
1769 + clock-names = "bus", "mod";
1770 + resets = <&ccu RST_BUS_DE>;
1771 + #clock-cells = <1>;
1772 + #reset-cells = <1>;
1773 + };
1774 +
1775 + mixer0: mixer@5100000 {
1776 + compatible = "allwinner,sun20i-d1-de2-mixer-0";
1777 + reg = <0x5100000 0x100000>;
1778 + clocks = <&display_clocks CLK_BUS_MIXER0>,
1779 + <&display_clocks CLK_MIXER0>;
1780 + clock-names = "bus", "mod";
1781 + resets = <&display_clocks RST_MIXER0>;
1782 +
1783 + ports {
1784 + #address-cells = <1>;
1785 + #size-cells = <0>;
1786 +
1787 + mixer0_out: port@1 {
1788 + reg = <1>;
1789 +
1790 + mixer0_out_tcon_top_mixer0: endpoint {
1791 + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
1792 + };
1793 + };
1794 + };
1795 + };
1796 +
1797 + mixer1: mixer@5200000 {
1798 + compatible = "allwinner,sun20i-d1-de2-mixer-1";
1799 + reg = <0x5200000 0x100000>;
1800 + clocks = <&display_clocks CLK_BUS_MIXER1>,
1801 + <&display_clocks CLK_MIXER1>;
1802 + clock-names = "bus", "mod";
1803 + resets = <&display_clocks RST_MIXER1>;
1804 +
1805 + ports {
1806 + #address-cells = <1>;
1807 + #size-cells = <0>;
1808 +
1809 + mixer1_out: port@1 {
1810 + reg = <1>;
1811 +
1812 + mixer1_out_tcon_top_mixer1: endpoint {
1813 + remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
1814 + };
1815 + };
1816 + };
1817 + };
1818 +
1819 + tcon_top: tcon-top@5460000 {
1820 + compatible = "allwinner,sun20i-d1-tcon-top";
1821 + reg = <0x5460000 0x1000>;
1822 + clocks = <&ccu CLK_BUS_DPSS_TOP>,
1823 + <&ccu CLK_TCON_TV>,
1824 + <&ccu CLK_TVE>,
1825 + <&ccu CLK_TCON_LCD0>;
1826 + clock-names = "bus", "tcon-tv0", "tve0", "dsi";
1827 + clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
1828 + resets = <&ccu RST_BUS_DPSS_TOP>;
1829 + #clock-cells = <1>;
1830 +
1831 + ports {
1832 + #address-cells = <1>;
1833 + #size-cells = <0>;
1834 +
1835 + tcon_top_mixer0_in: port@0 {
1836 + reg = <0>;
1837 + #address-cells = <1>;
1838 + #size-cells = <0>;
1839 +
1840 + tcon_top_mixer0_in_mixer0: endpoint@0 {
1841 + reg = <0>;
1842 + remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
1843 + };
1844 + };
1845 +
1846 + tcon_top_mixer0_out: port@1 {
1847 + reg = <1>;
1848 + #address-cells = <1>;
1849 + #size-cells = <0>;
1850 +
1851 + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
1852 + reg = <0>;
1853 + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
1854 + };
1855 +
1856 + tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
1857 + reg = <2>;
1858 + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
1859 + };
1860 + };
1861 +
1862 + tcon_top_mixer1_in: port@2 {
1863 + reg = <2>;
1864 + #address-cells = <1>;
1865 + #size-cells = <0>;
1866 +
1867 + tcon_top_mixer1_in_mixer1: endpoint@1 {
1868 + reg = <1>;
1869 + remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
1870 + };
1871 + };
1872 +
1873 + tcon_top_mixer1_out: port@3 {
1874 + reg = <3>;
1875 + #address-cells = <1>;
1876 + #size-cells = <0>;
1877 +
1878 + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1879 + reg = <0>;
1880 + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
1881 + };
1882 +
1883 + tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
1884 + reg = <2>;
1885 + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
1886 + };
1887 + };
1888 +
1889 + tcon_top_hdmi_in: port@4 {
1890 + reg = <4>;
1891 +
1892 + tcon_top_hdmi_in_tcon_tv0: endpoint {
1893 + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
1894 + };
1895 + };
1896 +
1897 + tcon_top_hdmi_out: port@5 {
1898 + reg = <5>;
1899 + };
1900 + };
1901 + };
1902 +
1903 + tcon_lcd0: lcd-controller@5461000 {
1904 + compatible = "allwinner,sun20i-d1-tcon-lcd";
1905 + reg = <0x5461000 0x1000>;
1906 + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
1907 + clocks = <&ccu CLK_BUS_TCON_LCD0>,
1908 + <&ccu CLK_TCON_LCD0>;
1909 + clock-names = "ahb", "tcon-ch0";
1910 + clock-output-names = "tcon-pixel-clock";
1911 + resets = <&ccu RST_BUS_TCON_LCD0>,
1912 + <&ccu RST_BUS_LVDS0>;
1913 + reset-names = "lcd", "lvds";
1914 + #clock-cells = <0>;
1915 +
1916 + ports {
1917 + #address-cells = <1>;
1918 + #size-cells = <0>;
1919 +
1920 + tcon_lcd0_in: port@0 {
1921 + reg = <0>;
1922 + #address-cells = <1>;
1923 + #size-cells = <0>;
1924 +
1925 + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
1926 + reg = <0>;
1927 + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
1928 + };
1929 +
1930 + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
1931 + reg = <1>;
1932 + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
1933 + };
1934 + };
1935 +
1936 + tcon_lcd0_out: port@1 {
1937 + reg = <1>;
1938 + };
1939 + };
1940 + };
1941 +
1942 + tcon_tv0: lcd-controller@5470000 {
1943 + compatible = "allwinner,sun20i-d1-tcon-tv";
1944 + reg = <0x5470000 0x1000>;
1945 + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
1946 + clocks = <&ccu CLK_BUS_TCON_TV>,
1947 + <&tcon_top CLK_TCON_TOP_TV0>;
1948 + clock-names = "ahb", "tcon-ch1";
1949 + resets = <&ccu RST_BUS_TCON_TV>;
1950 + reset-names = "lcd";
1951 +
1952 + ports {
1953 + #address-cells = <1>;
1954 + #size-cells = <0>;
1955 +
1956 + tcon_tv0_in: port@0 {
1957 + reg = <0>;
1958 + #address-cells = <1>;
1959 + #size-cells = <0>;
1960 +
1961 + tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1962 + reg = <0>;
1963 + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
1964 + };
1965 +
1966 + tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
1967 + reg = <1>;
1968 + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
1969 + };
1970 + };
1971 +
1972 + tcon_tv0_out: port@1 {
1973 + reg = <1>;
1974 +
1975 + tcon_tv0_out_tcon_top_hdmi: endpoint {
1976 + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
1977 + };
1978 + };
1979 + };
1980 + };
1981 +
1982 + riscv_wdt: watchdog@6011000 {
1983 + compatible = "allwinner,sun20i-d1-wdt";
1984 + reg = <0x6011000 0x20>;
1985 + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
1986 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
1987 + clock-names = "hosc", "losc";
1988 + };
1989 +
1990 + r_ccu: clock-controller@7010000 {
1991 + compatible = "allwinner,sun20i-d1-r-ccu";
1992 + reg = <0x7010000 0x400>;
1993 + clocks = <&osc24M>,
1994 + <&rtc CLK_OSC32K>,
1995 + <&rtc CLK_IOSC>,
1996 + <&ccu CLK_PLL_PERIPH0_DIV3>;
1997 + clock-names = "hosc", "losc", "iosc", "pll-periph";
1998 + #clock-cells = <1>;
1999 + #reset-cells = <1>;
2000 + };
2001 +
2002 + rtc: rtc@7090000 {
2003 + compatible = "allwinner,sun20i-d1-rtc",
2004 + "allwinner,sun50i-r329-rtc";
2005 + reg = <0x7090000 0x400>;
2006 + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
2007 + clocks = <&r_ccu CLK_BUS_R_RTC>,
2008 + <&osc24M>,
2009 + <&r_ccu CLK_R_AHB>;
2010 + clock-names = "bus", "hosc", "ahb";
2011 + #clock-cells = <1>;
2012 + };
2013 +
2014 + plic: interrupt-controller@10000000 {
2015 + compatible = "allwinner,sun20i-d1-plic",
2016 + "thead,c900-plic";
2017 + reg = <0x10000000 0x4000000>;
2018 + interrupts-extended = <&cpu0_intc 11>,
2019 + <&cpu0_intc 9>;
2020 + interrupt-controller;
2021 + riscv,ndev = <176>;
2022 + #address-cells = <0>;
2023 + #interrupt-cells = <2>;
2024 + };
2025 + };
2026 +};
2027 --- /dev/null
2028 +++ b/arch/riscv/dts/sunxi-u-boot.dtsi
2029 @@ -0,0 +1,68 @@
2030 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2031 +
2032 +#include "binman.dtsi"
2033 +
2034 +/ {
2035 + cpus {
2036 + u-boot,dm-spl;
2037 + };
2038 +
2039 + soc {
2040 + u-boot,dm-spl;
2041 + };
2042 +};
2043 +
2044 +&binman {
2045 + u-boot-sunxi-with-spl {
2046 + filename = "u-boot-sunxi-with-spl.bin";
2047 + pad-byte = <0xff>;
2048 +
2049 + blob@0 {
2050 + filename = "spl/sunxi-spl.bin";
2051 + };
2052 +
2053 + blob@1 {
2054 + filename = "u-boot.itb";
2055 + };
2056 + };
2057 +};
2058 +
2059 +&ccu {
2060 + u-boot,dm-spl;
2061 +};
2062 +
2063 +&cpu0 {
2064 + u-boot,dm-spl;
2065 +};
2066 +
2067 +&mbus {
2068 + u-boot,dm-spl;
2069 +};
2070 +
2071 +&mmc0 {
2072 + u-boot,dm-spl;
2073 +};
2074 +
2075 +&mmc0_pins {
2076 + u-boot,dm-spl;
2077 +};
2078 +
2079 +&osc24M {
2080 + u-boot,dm-spl;
2081 +};
2082 +
2083 +&pio {
2084 + u-boot,dm-spl;
2085 +};
2086 +
2087 +&rtc {
2088 + u-boot,dm-spl;
2089 +};
2090 +
2091 +&uart0 {
2092 + u-boot,dm-spl;
2093 +};
2094 +
2095 +&uart0_pb8_pins {
2096 + u-boot,dm-spl;
2097 +};
2098 --- /dev/null
2099 +++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h
2100 @@ -0,0 +1,19 @@
2101 +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2102 +/*
2103 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
2104 + */
2105 +
2106 +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
2107 +#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
2108 +
2109 +#define CLK_R_AHB 0
2110 +
2111 +#define CLK_BUS_R_TIMER 2
2112 +#define CLK_BUS_R_TWD 3
2113 +#define CLK_BUS_R_PPU 4
2114 +#define CLK_R_IR_RX 5
2115 +#define CLK_BUS_R_IR_RX 6
2116 +#define CLK_BUS_R_RTC 7
2117 +#define CLK_BUS_R_CPUCFG 8
2118 +
2119 +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
2120 --- /dev/null
2121 +++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
2122 @@ -0,0 +1,16 @@
2123 +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2124 +/*
2125 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
2126 + */
2127 +
2128 +#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
2129 +#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
2130 +
2131 +#define RST_BUS_R_TIMER 0
2132 +#define RST_BUS_R_TWD 1
2133 +#define RST_BUS_R_PPU 2
2134 +#define RST_BUS_R_IR_RX 3
2135 +#define RST_BUS_R_RTC 4
2136 +#define RST_BUS_R_CPUCFG 5
2137 +
2138 +#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */
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