kernel/rockchip: Restore kernel files for v6.1
[openwrt/staging/nbd.git] / target / linux / rockchip / patches-6.1 / 007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch
1 From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001
2 From: Chukun Pan <amadeus@jmu.edu.cn>
3 Date: Sat, 3 Dec 2022 15:41:49 +0800
4 Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
5
6 Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
7
8 This device is similar to the NanoPi R2S, and has a 16MB
9 SPI NOR (mx25l12805d). The reset button is changed to
10 directly reset the power supply, another detail is that
11 both network ports have independent MAC addresses.
12
13 Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
14 Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn
15 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
16 ---
17 arch/arm64/boot/dts/rockchip/Makefile | 1 +
18 .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
19 2 files changed, 374 insertions(+)
20 create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
21
22 --- a/arch/arm64/boot/dts/rockchip/Makefile
23 +++ b/arch/arm64/boot/dts/rockchip/Makefile
24 @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
25 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
26 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
27 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
28 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
29 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
30 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
31 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
32 --- /dev/null
33 +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
34 @@ -0,0 +1,373 @@
35 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
36 +/*
37 + * Based on rk3328-nanopi-r2s.dts, which is:
38 + * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
39 + */
40 +
41 +/dts-v1/;
42 +
43 +#include <dt-bindings/gpio/gpio.h>
44 +#include <dt-bindings/leds/common.h>
45 +#include "rk3328.dtsi"
46 +
47 +/ {
48 + model = "Xunlong Orange Pi R1 Plus";
49 + compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
50 +
51 + aliases {
52 + ethernet1 = &rtl8153;
53 + mmc0 = &sdmmc;
54 + };
55 +
56 + chosen {
57 + stdout-path = "serial2:1500000n8";
58 + };
59 +
60 + gmac_clk: gmac-clock {
61 + compatible = "fixed-clock";
62 + clock-frequency = <125000000>;
63 + clock-output-names = "gmac_clkin";
64 + #clock-cells = <0>;
65 + };
66 +
67 + leds {
68 + compatible = "gpio-leds";
69 + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
70 + pinctrl-names = "default";
71 +
72 + led-0 {
73 + function = LED_FUNCTION_LAN;
74 + color = <LED_COLOR_ID_GREEN>;
75 + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
76 + };
77 +
78 + led-1 {
79 + function = LED_FUNCTION_STATUS;
80 + color = <LED_COLOR_ID_RED>;
81 + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
82 + linux,default-trigger = "heartbeat";
83 + };
84 +
85 + led-2 {
86 + function = LED_FUNCTION_WAN;
87 + color = <LED_COLOR_ID_GREEN>;
88 + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
89 + };
90 + };
91 +
92 + vcc_sd: sdmmc-regulator {
93 + compatible = "regulator-fixed";
94 + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
95 + pinctrl-0 = <&sdmmc0m1_pin>;
96 + pinctrl-names = "default";
97 + regulator-name = "vcc_sd";
98 + regulator-boot-on;
99 + vin-supply = <&vcc_io>;
100 + };
101 +
102 + vcc_sys: vcc-sys-regulator {
103 + compatible = "regulator-fixed";
104 + regulator-name = "vcc_sys";
105 + regulator-always-on;
106 + regulator-boot-on;
107 + regulator-min-microvolt = <5000000>;
108 + regulator-max-microvolt = <5000000>;
109 + };
110 +
111 + vdd_5v_lan: vdd-5v-lan-regulator {
112 + compatible = "regulator-fixed";
113 + enable-active-high;
114 + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
115 + pinctrl-0 = <&lan_vdd_pin>;
116 + pinctrl-names = "default";
117 + regulator-name = "vdd_5v_lan";
118 + regulator-always-on;
119 + regulator-boot-on;
120 + vin-supply = <&vcc_sys>;
121 + };
122 +};
123 +
124 +&cpu0 {
125 + cpu-supply = <&vdd_arm>;
126 +};
127 +
128 +&cpu1 {
129 + cpu-supply = <&vdd_arm>;
130 +};
131 +
132 +&cpu2 {
133 + cpu-supply = <&vdd_arm>;
134 +};
135 +
136 +&cpu3 {
137 + cpu-supply = <&vdd_arm>;
138 +};
139 +
140 +&display_subsystem {
141 + status = "disabled";
142 +};
143 +
144 +&gmac2io {
145 + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
146 + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
147 + clock_in_out = "input";
148 + phy-handle = <&rtl8211e>;
149 + phy-mode = "rgmii";
150 + phy-supply = <&vcc_io>;
151 + pinctrl-0 = <&rgmiim1_pins>;
152 + pinctrl-names = "default";
153 + snps,aal;
154 + rx_delay = <0x18>;
155 + tx_delay = <0x24>;
156 + status = "okay";
157 +
158 + mdio {
159 + compatible = "snps,dwmac-mdio";
160 + #address-cells = <1>;
161 + #size-cells = <0>;
162 +
163 + rtl8211e: ethernet-phy@1 {
164 + reg = <1>;
165 + pinctrl-0 = <&eth_phy_reset_pin>;
166 + pinctrl-names = "default";
167 + reset-assert-us = <10000>;
168 + reset-deassert-us = <50000>;
169 + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
170 + };
171 + };
172 +};
173 +
174 +&i2c1 {
175 + status = "okay";
176 +
177 + rk805: pmic@18 {
178 + compatible = "rockchip,rk805";
179 + reg = <0x18>;
180 + interrupt-parent = <&gpio1>;
181 + interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
182 + #clock-cells = <1>;
183 + clock-output-names = "xin32k", "rk805-clkout2";
184 + gpio-controller;
185 + #gpio-cells = <2>;
186 + pinctrl-0 = <&pmic_int_l>;
187 + pinctrl-names = "default";
188 + rockchip,system-power-controller;
189 + wakeup-source;
190 +
191 + vcc1-supply = <&vcc_sys>;
192 + vcc2-supply = <&vcc_sys>;
193 + vcc3-supply = <&vcc_sys>;
194 + vcc4-supply = <&vcc_sys>;
195 + vcc5-supply = <&vcc_io>;
196 + vcc6-supply = <&vcc_sys>;
197 +
198 + regulators {
199 + vdd_log: DCDC_REG1 {
200 + regulator-name = "vdd_log";
201 + regulator-always-on;
202 + regulator-boot-on;
203 + regulator-min-microvolt = <712500>;
204 + regulator-max-microvolt = <1450000>;
205 + regulator-ramp-delay = <12500>;
206 +
207 + regulator-state-mem {
208 + regulator-on-in-suspend;
209 + regulator-suspend-microvolt = <1000000>;
210 + };
211 + };
212 +
213 + vdd_arm: DCDC_REG2 {
214 + regulator-name = "vdd_arm";
215 + regulator-always-on;
216 + regulator-boot-on;
217 + regulator-min-microvolt = <712500>;
218 + regulator-max-microvolt = <1450000>;
219 + regulator-ramp-delay = <12500>;
220 +
221 + regulator-state-mem {
222 + regulator-on-in-suspend;
223 + regulator-suspend-microvolt = <950000>;
224 + };
225 + };
226 +
227 + vcc_ddr: DCDC_REG3 {
228 + regulator-name = "vcc_ddr";
229 + regulator-always-on;
230 + regulator-boot-on;
231 +
232 + regulator-state-mem {
233 + regulator-on-in-suspend;
234 + };
235 + };
236 +
237 + vcc_io: DCDC_REG4 {
238 + regulator-name = "vcc_io";
239 + regulator-always-on;
240 + regulator-boot-on;
241 + regulator-min-microvolt = <3300000>;
242 + regulator-max-microvolt = <3300000>;
243 +
244 + regulator-state-mem {
245 + regulator-on-in-suspend;
246 + regulator-suspend-microvolt = <3300000>;
247 + };
248 + };
249 +
250 + vcc_18: LDO_REG1 {
251 + regulator-name = "vcc_18";
252 + regulator-always-on;
253 + regulator-boot-on;
254 + regulator-min-microvolt = <1800000>;
255 + regulator-max-microvolt = <1800000>;
256 +
257 + regulator-state-mem {
258 + regulator-on-in-suspend;
259 + regulator-suspend-microvolt = <1800000>;
260 + };
261 + };
262 +
263 + vcc18_emmc: LDO_REG2 {
264 + regulator-name = "vcc18_emmc";
265 + regulator-always-on;
266 + regulator-boot-on;
267 + regulator-min-microvolt = <1800000>;
268 + regulator-max-microvolt = <1800000>;
269 +
270 + regulator-state-mem {
271 + regulator-on-in-suspend;
272 + regulator-suspend-microvolt = <1800000>;
273 + };
274 + };
275 +
276 + vdd_10: LDO_REG3 {
277 + regulator-name = "vdd_10";
278 + regulator-always-on;
279 + regulator-boot-on;
280 + regulator-min-microvolt = <1000000>;
281 + regulator-max-microvolt = <1000000>;
282 +
283 + regulator-state-mem {
284 + regulator-on-in-suspend;
285 + regulator-suspend-microvolt = <1000000>;
286 + };
287 + };
288 + };
289 + };
290 +};
291 +
292 +&io_domains {
293 + pmuio-supply = <&vcc_io>;
294 + vccio1-supply = <&vcc_io>;
295 + vccio2-supply = <&vcc18_emmc>;
296 + vccio3-supply = <&vcc_io>;
297 + vccio4-supply = <&vcc_io>;
298 + vccio5-supply = <&vcc_io>;
299 + vccio6-supply = <&vcc_io>;
300 + status = "okay";
301 +};
302 +
303 +&pinctrl {
304 + gmac2io {
305 + eth_phy_reset_pin: eth-phy-reset-pin {
306 + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
307 + };
308 + };
309 +
310 + leds {
311 + lan_led_pin: lan-led-pin {
312 + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
313 + };
314 +
315 + sys_led_pin: sys-led-pin {
316 + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
317 + };
318 +
319 + wan_led_pin: wan-led-pin {
320 + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
321 + };
322 + };
323 +
324 + lan {
325 + lan_vdd_pin: lan-vdd-pin {
326 + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
327 + };
328 + };
329 +
330 + pmic {
331 + pmic_int_l: pmic-int-l {
332 + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
333 + };
334 + };
335 +};
336 +
337 +&pwm2 {
338 + status = "okay";
339 +};
340 +
341 +&sdmmc {
342 + bus-width = <4>;
343 + cap-sd-highspeed;
344 + disable-wp;
345 + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
346 + pinctrl-names = "default";
347 + vmmc-supply = <&vcc_sd>;
348 + status = "okay";
349 +};
350 +
351 +&spi0 {
352 + status = "okay";
353 +
354 + flash@0 {
355 + compatible = "jedec,spi-nor";
356 + reg = <0>;
357 + spi-max-frequency = <50000000>;
358 + };
359 +};
360 +
361 +&tsadc {
362 + rockchip,hw-tshut-mode = <0>;
363 + rockchip,hw-tshut-polarity = <0>;
364 + status = "okay";
365 +};
366 +
367 +&u2phy {
368 + status = "okay";
369 +};
370 +
371 +&u2phy_host {
372 + status = "okay";
373 +};
374 +
375 +&u2phy_otg {
376 + status = "okay";
377 +};
378 +
379 +&uart2 {
380 + status = "okay";
381 +};
382 +
383 +&usb20_otg {
384 + dr_mode = "host";
385 + status = "okay";
386 +};
387 +
388 +&usbdrd3 {
389 + dr_mode = "host";
390 + status = "okay";
391 + #address-cells = <1>;
392 + #size-cells = <0>;
393 +
394 + /* Second port is for USB 3.0 */
395 + rtl8153: device@2 {
396 + compatible = "usbbda,8153";
397 + reg = <2>;
398 + };
399 +};
400 +
401 +&usb_host0_ehci {
402 + status = "okay";
403 +};
404 +
405 +&usb_host0_ohci {
406 + status = "okay";
407 +};