target/linux/d1/patches-6.1/0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch

   1 From 8fc2a02d1d2e98a01a2dad3bf3da8e33366725eb Mon Sep 17 00:00:00 2001
   2 From: Samuel Holland <samuel@sholland.org>
   3 Date: Sun, 7 Aug 2022 19:17:35 -0500
   4 Subject: [PATCH 111/117] drm: panel: cwd686: Use vendor panel init sequence
   5
   6 Signed-off-by: Samuel Holland <samuel@sholland.org>
   7 ---
   8  .../gpu/drm/panel/panel-clockwork-cwd686.c    | 142 ++++--------------
   9  1 file changed, 32 insertions(+), 110 deletions(-)
  10
  11 --- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
  12 +++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
  13 @@ -47,10 +47,12 @@ static inline struct cwd686 *panel_to_cw
  14         return container_of(panel, struct cwd686, panel);
  15  }
  16
  17 -#define ICNL9707_DCS(seq...)                              \
  18 +#define dcs_write_seq(seq...)                              \
  19  ({                                                              \
  20         static const u8 d[] = { seq };                          \
  21 -       mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));        \
  22 +       ssize_t r = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));    \
  23 +       if (r < 0) \
  24 +               return r; \
  25  })
  26
  27  #define ICNL9707_CMD_CGOUTL 0xB3
  28 @@ -128,115 +130,35 @@ static inline struct cwd686 *panel_to_cw
  29  static int cwd686_init_sequence(struct cwd686 *ctx)
  30  {
  31         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  32 -       int err;
  33
  34 -       /* Enable access to Level 2 registers */
  35 -       ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
  36 -                    ICNL9707_P_PASSWORD1_ENABLE_LVL2,
  37 -                    ICNL9707_P_PASSWORD1_ENABLE_LVL2);
  38 -       ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
  39 -                    ICNL9707_P_PASSWORD2_ENABLE_LVL2,
  40 -                    ICNL9707_P_PASSWORD2_ENABLE_LVL2);
  41 -
  42 -       /* Set PWRCON_VCOM (-0.495V, -0.495V) */
  43 -       ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
  44 -                    ICNL9707_P_PWRCON_VCOM_0495V,
  45 -                    ICNL9707_P_PWRCON_VCOM_0495V);
  46 -
  47 -       /* Map ASG output signals */
  48 -       ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
  49 -                    ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
  50 -                    ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
  51 -                    ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
  52 -                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
  53 -                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
  54 -                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
  55 -                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
  56 -                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
  57 -                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
  58 -                    ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
  59 -       ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
  60 -                    ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
  61 -                    ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
  62 -                    ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
  63 -                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
  64 -                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
  65 -                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
  66 -                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
  67 -                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
  68 -                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
  69 -                    ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
  70 -
  71 -       /* Undocumented commands provided by the vendor */
  72 -       ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
  73 -       ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
  74 -       ICNL9707_DCS(0xB2, 0x73);
  75 -
  76 -       ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
  77 -                    0x4E, 0x0E, 0x50, 0x50, 0x26,
  78 -                    0x1D, 0x00, 0x14, 0x42, 0x03);
  79 -       ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
  80 -                    0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
  81 -                    0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
  82 -                    0x00, 0x00, 0x02, 0xFF, 0x3C);
  83 -       ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
  84 -
  85 -       /* Disable abnormal power-off flag */
  86 -       ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
  87 -
  88 -       ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
  89 -
  90 -       /* Set VBP, VFP, VSW, HBP, HFP, HSW */
  91 -       ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
  92 -
  93 -       /* Set resolution */
  94 -       ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
  95 -
  96 -       /* Set frame blanking */
  97 -       ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
  98 -
  99 -       ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
 100 -
 101 -       /* Another undocumented command */
 102 -       ICNL9707_DCS(0xC5, 0x00);
 103 -
 104 -       ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
 105 -
 106 -       /* Another set of undocumented commands */
 107 -       ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
 108 -       ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
 109 -
 110 -       /* Set Gamma to 2.2 */
 111 -       ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
 112 -                    0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
 113 -                    0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
 114 -                    0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
 115 -                    0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
 116 -                    0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
 117 -                    0x3B, 0x2A, 0x06);
 118 -
 119 -       ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
 120 -
 121 -       /* Another undocumented command */
 122 -       ICNL9707_DCS(0xF4, 0x08, 0x77);
 123 -
 124 -       ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
 125 -                    ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
 126 -
 127 -       /* Enable tearing mode at VBLANK */
 128 -       err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
 129 -       if (err) {
 130 -               dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
 131 -               return err;
 132 -       }
 133 -
 134 -       /* Disable access to Level 2 registers */
 135 -       ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
 136 -                    ICNL9707_P_PASSWORD2_DEFAULT,
 137 -                    ICNL9707_P_PASSWORD2_DEFAULT);
 138 -       ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
 139 -                    ICNL9707_P_PASSWORD1_DEFAULT,
 140 -                    ICNL9707_P_PASSWORD1_DEFAULT);
 141 +       dcs_write_seq(0xF0,0x5A,0x5A);
 142 +       dcs_write_seq(0xF1,0xA5,0xA5);
 143 +       dcs_write_seq(0xB6,0x0D,0x0D);
 144 +       dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
 145 +       dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
 146 +       dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
 147 +       dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
 148 +       dcs_write_seq(0xB2,0x73);
 149 +       dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
 150 +       dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
 151 +       dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
 152 +       dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
 153 +       dcs_write_seq(0xBA,0x12,0x63);
 154 +       dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
 155 +       dcs_write_seq(0xC2,0x11,0x41);
 156 +       dcs_write_seq(0xC3,0x22,0x31,0x04);
 157 +       dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
 158 +       dcs_write_seq(0xC5,0x00);
 159 +       dcs_write_seq(0xD0,0x37,0xFF,0xFF);
 160 +       dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
 161 +       dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
 162 +       dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
 163 +       dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
 164 +       dcs_write_seq(0xF4,0x08,0x77);
 165 +       dcs_write_seq(0x36,0x14);
 166 +       dcs_write_seq(0x35,0x00);
 167 +       dcs_write_seq(0xF1,0x5A,0x5A);
 168 +       dcs_write_seq(0xF0,0xA5,0xA5);
 169
 170         return 0;
 171  }