d1: add new target
[openwrt/staging/mans0n.git] / target / linux / d1 / patches-6.1 / 0059-pwm-sun8i-v536-document-device-tree-bindings.patch
1 From effa2ef8717b0390e8fb0648e16df1b43610af53 Mon Sep 17 00:00:00 2001
2 From: Ban Tao <fengzheng923@gmail.com>
3 Date: Tue, 2 Mar 2021 20:40:23 +0800
4 Subject: [PATCH 059/117] pwm: sun8i-v536: document device tree bindings
5
6 This adds binding documentation for sun8i-v536 SoC PWM driver.
7
8 Signed-off-by: Ban Tao <fengzheng923@gmail.com>
9 ---
10 .../bindings/pwm/pwm-sun8i-v536.txt | 24 +++++++++++++++++++
11 1 file changed, 24 insertions(+)
12 create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
13
14 --- /dev/null
15 +++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
16 @@ -0,0 +1,24 @@
17 +Allwinner sun8i-v536 SoC PWM controller
18 +
19 +Required properties:
20 + - compatible: should be "allwinner,<name>-pwm"
21 + "allwinner,sun8i-v833-pwm"
22 + "allwinner,sun8i-v536-pwm"
23 + "allwinner,sun50i-r818-pwm"
24 + "allwinner,sun50i-a133-pwm"
25 + "allwinner,sun50i-r329-pwm"
26 + - reg: physical base address and length of the controller's registers
27 + - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
28 + the cells format.
29 + - clocks: From common clock binding, handle to the parent clock.
30 + - resets: From reset clock binding, handle to the parent clock.
31 +
32 +Example:
33 +
34 + pwm: pwm@300a0000 {
35 + compatible = "allwinner,sun50i-r818-pwm";
36 + reg = <0x0300a000 0x3ff>;
37 + clocks = <&ccu CLK_BUS_PWM>;
38 + resets = <&ccu RST_BUS_PWM>;
39 + #pwm-cells = <3>;
40 + };