target/linux/d1/patches-6.1/0025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch

   1 From 4ae663dbc373f5690581cee16d3667693eb9d73e Mon Sep 17 00:00:00 2001
   2 From: Samuel Holland <samuel@sholland.org>
   3 Date: Sun, 16 May 2021 14:05:17 -0500
   4 Subject: [PATCH 025/117] dt-bindings: riscv: Add T-HEAD C906 and C910
   5  compatibles
   6
   7 The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
   8 Notably, the C906 core is used in the Allwinner D1 SoC.
   9
  10 Acked-by: Rob Herring <robh@kernel.org>
  11 Reviewed-by: Heiko Stuebner <heiko@sntech.de>
  12 Signed-off-by: Samuel Holland <samuel@sholland.org>
  13 ---
  14  Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
  15  1 file changed, 2 insertions(+)
  16
  17 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
  18 +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
  19 @@ -39,6 +39,8 @@ properties:
  20                - sifive,u5
  21                - sifive,u7
  22                - canaan,k210
  23 +              - thead,c906
  24 +              - thead,c910
  25            - const: riscv
  26        - items:
  27            - enum: