arm: dts: am33xx: Sync dts with Linux 4.20.0
authorFelix Brack <fb@ltec.ch>
Wed, 5 Dec 2018 13:53:42 +0000 (14:53 +0100)
committerTom Rini <trini@konsulko.com>
Fri, 7 Dec 2018 13:13:51 +0000 (08:13 -0500)
This patch synchronizes the am33xx SoC specific files with those from
Linux 4.20.0. Hence all board maintainers of am33xx based boards are
on the cc list.
The main purpose of this patch is to prevent further diverging of the
dts files from U-Boot and those from Linux. It aims to set the stage
for the synchronization of board specific dts files. Example: I'm the
maintainer of the PDU001 board: once this patch is applied successfully
I will make changes to the board specific dts file in Linux only and
then post a patch with a copy of this exact dts file to U-Boot. This
will make U-Boot and Linux remain in sync.
The stumbling block of https://patchwork.ozlabs.org/patch/943627 was
removed by the patch https://patchwork.ozlabs.org/patch/962428 from
Lokesh Vutla (many thanks!). This omap-serial driver allows using the
Linux am33xx.dtsi file in U-Boot.
Other changes to dts and dtsi files made by this patch are mainly to
prevent _new_ warnings during the build process. Especially the warning
at pinmux@800 stating 'unnecessary #address-cells/#size-cells without
"ranges" or child "reg"' was not removed. This warning is a good example
showing the benefit of the synchronization: if it needs to be fixed it
will be fixed in Linux and ported back to U-Boot.
Buildman reports all 46 am33xx SoC based boards to build fine, with
warnings of course. Nevertheless this patch should be tested thoroughly
on as many boards as possible to prevent any collateral damage.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/dts/am335x-evm.dts
arch/arm/dts/am335x-evmsk.dts
arch/arm/dts/am335x-pxm2.dtsi
arch/arm/dts/am335x-rut.dts
arch/arm/dts/am33xx-clocks.dtsi
arch/arm/dts/am33xx.dtsi
arch/arm/dts/am4372.dtsi
arch/arm/dts/am437x-idk-evm.dts
arch/arm/dts/dm816x.dtsi
include/dt-bindings/clock/am3.h [new file with mode: 0644]

index a6f20af648abe005c5a36dc5634434b4b407e81e..fe272075887158965473d433e601f55516277e9d 100644 (file)
@@ -80,8 +80,6 @@
 
        gpio_keys: volume_keys@0 {
                compatible = "gpio-keys";
-               #address-cells = <1>;
-               #size-cells = <0>;
                autorepeat;
 
                switch@9 {
 &mmc3 {
        /* these are on the crossbar and are outlined in the
           xbar-event-map element */
-       dmas = <&edma 12
-               &edma 13>;
+       dmas = <&edma 12 0
+               &edma 13 0>;
        dma-names = "tx", "rx";
        status = "okay";
        vmmc-supply = <&wlan_en_reg>;
index b3e9b61baeb547574c248598c03965eecd0e27af..0767578aeeb872ecd39053c6b5e1ba5d6deff172 100644 (file)
 
        gpio_buttons: gpio_buttons@0 {
                compatible = "gpio-keys";
-               #address-cells = <1>;
-               #size-cells = <0>;
 
                switch@1 {
                        label = "button0";
index 8d58cd4c917d3beebf6013b742a087958f65ecfd..d9243d5d3d96dc757eb001d5e801195971ea9d9e 100644 (file)
@@ -50,8 +50,6 @@
 
        gpio_keys: restart-keys {
                compatible = "gpio-keys";
-               #address-cells = <1>;
-               #size-cells = <0>;
                autorepeat;
 
                restart0 {
index c6cfbb8033e8cc38e494444effd72c61d43c6ecd..a5716a929f6683933f2cde0c3879a34da84748e4 100644 (file)
@@ -36,8 +36,6 @@
 
        gpio_keys: powerfail-keys {
                compatible = "gpio-keys";
-               #address-cells = <1>;
-               #size-cells = <0>;
                autorepeat;
 
                pwr-fail0 {
 
 &epwmss1 {
        status = "okay";
-
-       ehrpwm1: ehrpwm@48302200 {
-               status = "okay";
-               pinctrl-names = "default";
-               pinctrl-0 = <&epwmss1_pins>;
-       };
+       pinctrl-names = "default";
+       pinctrl-0 = <&epwmss1_pins>;
 };
 
 &gpmc {
index afb4b3a7bab47b5e426e4e9a25f1a6dd4ec4f360..95d5c9d136c5b2f5e318fc00fbfc0cf425c8e004 100644 (file)
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &scm_clocks {
-       sys_clkin_ck: sys_clkin_ck {
+       sys_clkin_ck: sys_clkin_ck@40 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
                clock-frequency = <12000000>;
        };
 
-       dpll_core_ck: dpll_core_ck {
+       dpll_core_ck: dpll_core_ck@490 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-core-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                clocks = <&dpll_core_ck>;
        };
 
-       dpll_core_m4_ck: dpll_core_m4_ck {
+       dpll_core_m4_ck: dpll_core_m4_ck@480 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,index-starts-at-one;
        };
 
-       dpll_core_m5_ck: dpll_core_m5_ck {
+       dpll_core_m5_ck: dpll_core_m5_ck@484 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,index-starts-at-one;
        };
 
-       dpll_core_m6_ck: dpll_core_m6_ck {
+       dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,index-starts-at-one;
        };
 
-       dpll_mpu_ck: dpll_mpu_ck {
+       dpll_mpu_ck: dpll_mpu_ck@488 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x0488>, <0x0420>, <0x042c>;
        };
 
-       dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+       dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_mpu_ck>;
                ti,index-starts-at-one;
        };
 
-       dpll_ddr_ck: dpll_ddr_ck {
+       dpll_ddr_ck: dpll_ddr_ck@494 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x0494>, <0x0434>, <0x0440>;
        };
 
-       dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+       dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_ddr_ck>;
                clock-div = <2>;
        };
 
-       dpll_disp_ck: dpll_disp_ck {
+       dpll_disp_ck: dpll_disp_ck@498 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x0498>, <0x0448>, <0x0454>;
        };
 
-       dpll_disp_m2_ck: dpll_disp_m2_ck {
+       dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_disp_ck>;
                ti,set-rate-parent;
        };
 
-       dpll_per_ck: dpll_per_ck {
+       dpll_per_ck: dpll_per_ck@48c {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-j-type-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x048c>, <0x0470>, <0x049c>;
        };
 
-       dpll_per_m2_ck: dpll_per_m2_ck {
+       dpll_per_m2_ck: dpll_per_m2_ck@4ac {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_ck>;
                clock-div = <4>;
        };
 
-       cefuse_fck: cefuse_fck {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&sys_clkin_ck>;
-               ti,bit-shift = <1>;
-               reg = <0x0a20>;
-       };
-
        clk_24mhz: clk_24mhz {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clock-div = <732>;
        };
 
-       clkdiv32k_ick: clkdiv32k_ick {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&clkdiv32k_ck>;
-               ti,bit-shift = <1>;
-               reg = <0x014c>;
-       };
-
        l3_gclk: l3_gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clock-div = <1>;
        };
 
-       pruss_ocp_gclk: pruss_ocp_gclk {
+       pruss_ocp_gclk: pruss_ocp_gclk@530 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
                reg = <0x0530>;
        };
 
-       mmu_fck: mmu_fck {
+       mmu_fck: mmu_fck@914 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll_core_m4_ck>;
                reg = <0x0914>;
        };
 
-       timer1_fck: timer1_fck {
+       timer1_fck: timer1_fck@528 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+               clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
                reg = <0x0528>;
        };
 
-       timer2_fck: timer2_fck {
+       timer2_fck: timer2_fck@508 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0508>;
        };
 
-       timer3_fck: timer3_fck {
+       timer3_fck: timer3_fck@50c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x050c>;
        };
 
-       timer4_fck: timer4_fck {
+       timer4_fck: timer4_fck@510 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0510>;
        };
 
-       timer5_fck: timer5_fck {
+       timer5_fck: timer5_fck@518 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0518>;
        };
 
-       timer6_fck: timer6_fck {
+       timer6_fck: timer6_fck@51c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x051c>;
        };
 
-       timer7_fck: timer7_fck {
+       timer7_fck: timer7_fck@504 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0504>;
        };
 
-       usbotg_fck: usbotg_fck {
+       usbotg_fck: usbotg_fck@47c {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll_per_ck>;
                clock-div = <2>;
        };
 
-       ieee5000_fck: ieee5000_fck {
+       ieee5000_fck: ieee5000_fck@e4 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll_core_m4_div2_ck>;
                reg = <0x00e4>;
        };
 
-       wdt1_fck: wdt1_fck {
+       wdt1_fck: wdt1_fck@538 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+               clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0538>;
        };
 
                clock-div = <2>;
        };
 
-       cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+       cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
                reg = <0x0520>;
        };
 
-       gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+       gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+               clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x053c>;
        };
 
-       gpio0_dbclk: gpio0_dbclk {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&gpio0_dbclk_mux_ck>;
-               ti,bit-shift = <18>;
-               reg = <0x0408>;
-       };
-
-       gpio1_dbclk: gpio1_dbclk {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&clkdiv32k_ick>;
-               ti,bit-shift = <18>;
-               reg = <0x00ac>;
-       };
-
-       gpio2_dbclk: gpio2_dbclk {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&clkdiv32k_ick>;
-               ti,bit-shift = <18>;
-               reg = <0x00b0>;
-       };
-
-       gpio3_dbclk: gpio3_dbclk {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&clkdiv32k_ick>;
-               ti,bit-shift = <18>;
-               reg = <0x00b4>;
-       };
-
-       lcd_gclk: lcd_gclk {
+       lcd_gclk: lcd_gclk@534 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
                clock-div = <2>;
        };
 
-       gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+       gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
                reg = <0x052c>;
        };
 
-       gfx_fck_div_ck: gfx_fck_div_ck {
+       gfx_fck_div_ck: gfx_fck_div_ck@52c {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&gfx_fclk_clksel_ck>;
                ti,max-div = <2>;
        };
 
-       sysclkout_pre_ck: sysclkout_pre_ck {
+       sysclkout_pre_ck: sysclkout_pre_ck@700 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
                reg = <0x0700>;
        };
 
-       clkout2_div_ck: clkout2_div_ck {
+       clkout2_div_ck: clkout2_div_ck@700 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&sysclkout_pre_ck>;
                reg = <0x0700>;
        };
 
-       dbg_sysclk_ck: dbg_sysclk_ck {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&sys_clkin_ck>;
-               ti,bit-shift = <19>;
-               reg = <0x0414>;
-       };
-
-       dbg_clka_ck: dbg_clka_ck {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&dpll_core_m4_ck>;
-               ti,bit-shift = <30>;
-               reg = <0x0414>;
-       };
-
-       stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
-               ti,bit-shift = <22>;
-               reg = <0x0414>;
-       };
-
-       trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
-               ti,bit-shift = <20>;
-               reg = <0x0414>;
-       };
-
-       stm_clk_div_ck: stm_clk_div_ck {
-               #clock-cells = <0>;
-               compatible = "ti,divider-clock";
-               clocks = <&stm_pmd_clock_mux_ck>;
-               ti,bit-shift = <27>;
-               ti,max-div = <64>;
-               reg = <0x0414>;
-               ti,index-power-of-two;
-       };
-
-       trace_clk_div_ck: trace_clk_div_ck {
-               #clock-cells = <0>;
-               compatible = "ti,divider-clock";
-               clocks = <&trace_pmd_clk_mux_ck>;
-               ti,bit-shift = <24>;
-               ti,max-div = <64>;
-               reg = <0x0414>;
-               ti,index-power-of-two;
-       };
-
-       clkout2_ck: clkout2_ck {
+       clkout2_ck: clkout2_ck@700 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&clkout2_div_ck>;
        };
 };
 
-&prcm_clockdomains {
-       clk_24mhz_clkdm: clk_24mhz_clkdm {
-               compatible = "ti,clockdomain";
-               clocks = <&clkdiv32k_ick>;
+&prcm {
+       l4_per_cm: l4_per_cm@0 {
+               compatible = "ti,omap4-cm";
+               reg = <0x0 0x200>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x0 0x200>;
+
+               l4_per_clkctrl: clk@14 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x14 0x13c>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       l4_wkup_cm: l4_wkup_cm@400 {
+               compatible = "ti,omap4-cm";
+               reg = <0x400 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x400 0x100>;
+
+               l4_wkup_clkctrl: clk@4 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x4 0xd4>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       mpu_cm: mpu_cm@600 {
+               compatible = "ti,omap4-cm";
+               reg = <0x600 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x600 0x100>;
+
+               mpu_clkctrl: clk@4 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x4 0x4>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       l4_rtc_cm: l4_rtc_cm@800 {
+               compatible = "ti,omap4-cm";
+               reg = <0x800 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x800 0x100>;
+
+               l4_rtc_clkctrl: clk@0 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x0 0x4>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       gfx_l3_cm: gfx_l3_cm@900 {
+               compatible = "ti,omap4-cm";
+               reg = <0x900 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x900 0x100>;
+
+               gfx_l3_clkctrl: clk@4 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x4 0x4>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       l4_cefuse_cm: l4_cefuse_cm@a00 {
+               compatible = "ti,omap4-cm";
+               reg = <0xa00 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0xa00 0x100>;
+
+               l4_cefuse_clkctrl: clk@20 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x20 0x4>;
+                       #clock-cells = <2>;
+               };
        };
 };
index 42345375e684088187ebe2569125a27df1530e0a..d3dd6a16e70a706f214bf5ab54bdff396ed2c2bc 100644 (file)
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/am33xx.h>
-
-#include "skeleton.dtsi"
+#include <dt-bindings/clock/am3.h>
 
 / {
        compatible = "ti,am33xx";
        interrupt-parent = <&intc>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+       chosen { };
 
        aliases {
                i2c0 = &i2c0;
                serial3 = &uart3;
                serial4 = &uart4;
                serial5 = &uart5;
-               d_can0 = &dcan0;
-               d_can1 = &dcan1;
+               d-can0 = &dcan0;
+               d-can1 = &dcan1;
                usb0 = &usb0;
                usb1 = &usb1;
                phy0 = &usb0_phy;
                phy1 = &usb1_phy;
                ethernet0 = &cpsw_emac0;
                ethernet1 = &cpsw_emac1;
+               spi0 = &spi0;
+               spi1 = &spi1;
        };
 
        cpus {
                        device_type = "cpu";
                        reg = <0>;
 
-                       /*
-                        * To consider voltage drop between PMIC and SoC,
-                        * tolerance value is reduced to 2% from 4% and
-                        * voltage value is increased as a precaution.
-                        */
-                       operating-points = <
-                               /* kHz    uV */
-                               720000  1285000
-                               600000  1225000
-                               500000  1125000
-                               275000  1125000
-                       >;
-                       voltage-tolerance = <2>; /* 2 percentage */
+                       operating-points-v2 = <&cpu0_opp_table>;
 
                        clocks = <&dpll_mpu_ck>;
                        clock-names = "cpu";
                };
        };
 
-       pmu {
+       cpu0_opp_table: opp-table {
+               compatible = "operating-points-v2-ti-cpu";
+               syscon = <&scm_conf>;
+
+               /*
+                * The three following nodes are marked with opp-suspend
+                * because the can not be enabled simultaneously on a
+                * single SoC.
+                */
+               opp50-300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-microvolt = <950000 931000 969000>;
+                       opp-supported-hw = <0x06 0x0010>;
+                       opp-suspend;
+               };
+
+               opp100-275000000 {
+                       opp-hz = /bits/ 64 <275000000>;
+                       opp-microvolt = <1100000 1078000 1122000>;
+                       opp-supported-hw = <0x01 0x00FF>;
+                       opp-suspend;
+               };
+
+               opp100-300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-microvolt = <1100000 1078000 1122000>;
+                       opp-supported-hw = <0x06 0x0020>;
+                       opp-suspend;
+               };
+
+               opp100-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <1100000 1078000 1122000>;
+                       opp-supported-hw = <0x01 0xFFFF>;
+               };
+
+               opp100-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1100000 1078000 1122000>;
+                       opp-supported-hw = <0x06 0x0040>;
+               };
+
+               opp120-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1200000 1176000 1224000>;
+                       opp-supported-hw = <0x01 0xFFFF>;
+               };
+
+               opp120-720000000 {
+                       opp-hz = /bits/ 64 <720000000>;
+                       opp-microvolt = <1200000 1176000 1224000>;
+                       opp-supported-hw = <0x06 0x0080>;
+               };
+
+               oppturbo-720000000 {
+                       opp-hz = /bits/ 64 <720000000>;
+                       opp-microvolt = <1260000 1234800 1285200>;
+                       opp-supported-hw = <0x01 0xFFFF>;
+               };
+
+               oppturbo-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <1260000 1234800 1285200>;
+                       opp-supported-hw = <0x06 0x0100>;
+               };
+
+               oppnitro-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <1325000 1298500 1351500>;
+                       opp-supported-hw = <0x04 0x0200>;
+               };
+       };
+
+       pmu@4b000000 {
                compatible = "arm,cortex-a8-pmu";
                interrupts = <3>;
+               reg = <0x4b000000 0x1000000>;
+               ti,hwmods = "debugss";
        };
 
        /*
                mpu {
                        compatible = "ti,omap3-mpu";
                        ti,hwmods = "mpu";
+                       pm-sram = <&pm_sram_code
+                                  &pm_sram_data>;
                };
        };
 
         * the whole bus hierarchy.
         */
        ocp {
-               u-boot,dm-spl;
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0 0x44c00000 0x280000>;
 
+                       wkup_m3: wkup_m3@100000 {
+                               compatible = "ti,am3352-wkup-m3";
+                               reg = <0x100000 0x4000>,
+                                     <0x180000 0x2000>;
+                               reg-names = "umem", "dmem";
+                               ti,hwmods = "wkup_m3";
+                               ti,pm-firmware = "am335x-pm-firmware.elf";
+                       };
+
                        prcm: prcm@200000 {
-                               compatible = "ti,am3-prcm";
+                               compatible = "ti,am3-prcm", "simple-bus";
                                reg = <0x200000 0x4000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x200000 0x4000>;
 
                                prcm_clocks: clocks {
                                        #address-cells = <1>;
                                reg = <0x210000 0x2000>;
                                #address-cells = <1>;
                                #size-cells = <1>;
+                               #pinctrl-cells = <1>;
                                ranges = <0 0x210000 0x2000>;
 
                                am33xx_pinmux: pinmux@800 {
                                        reg = <0x800 0x238>;
                                        #address-cells = <1>;
                                        #size-cells = <0>;
+                                       #pinctrl-cells = <1>;
                                        pinctrl-single,register-width = <32>;
                                        pinctrl-single,function-mask = <0x7f>;
                                };
 
                                scm_conf: scm_conf@0 {
-                                       compatible = "syscon";
+                                       compatible = "syscon", "simple-bus";
                                        reg = <0x0 0x800>;
                                        #address-cells = <1>;
                                        #size-cells = <1>;
+                                       ranges = <0 0 0x800>;
 
                                        scm_clocks: clocks {
                                                #address-cells = <1>;
                                        };
                                };
 
+                               wkup_m3_ipc: wkup_m3_ipc@1324 {
+                                       compatible = "ti,am3352-wkup-m3-ipc";
+                                       reg = <0x1324 0x24>;
+                                       interrupts = <78>;
+                                       ti,rproc = <&wkup_m3>;
+                                       mboxes = <&mailbox &mbox_wkupm3>;
+                               };
+
+                               edma_xbar: dma-router@f90 {
+                                       compatible = "ti,am335x-edma-crossbar";
+                                       reg = <0xf90 0x40>;
+                                       #dma-cells = <3>;
+                                       dma-requests = <32>;
+                                       dma-masters = <&edma>;
+                               };
+
                                scm_clockdomains: clockdomains {
                                };
                        };
                };
 
                edma: edma@49000000 {
-                       compatible = "ti,edma3";
-                       ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
-                       reg =   <0x49000000 0x10000>,
-                               <0x44e10f90 0x40>;
+                       compatible = "ti,edma3-tpcc";
+                       ti,hwmods = "tpcc";
+                       reg =   <0x49000000 0x10000>;
+                       reg-names = "edma3_cc";
                        interrupts = <12 13 14>;
-                       #dma-cells = <1>;
+                       interrupt-names = "edma3_ccint", "edma3_mperr",
+                                         "edma3_ccerrint";
+                       dma-requests = <64>;
+                       #dma-cells = <2>;
+
+                       ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
+                                  <&edma_tptc2 0>;
+
+                       ti,edma-memcpy-channels = <20 21>;
+               };
+
+               edma_tptc0: tptc@49800000 {
+                       compatible = "ti,edma3-tptc";
+                       ti,hwmods = "tptc0";
+                       reg =   <0x49800000 0x100000>;
+                       interrupts = <112>;
+                       interrupt-names = "edma3_tcerrint";
+               };
+
+               edma_tptc1: tptc@49900000 {
+                       compatible = "ti,edma3-tptc";
+                       ti,hwmods = "tptc1";
+                       reg =   <0x49900000 0x100000>;
+                       interrupts = <113>;
+                       interrupt-names = "edma3_tcerrint";
+               };
+
+               edma_tptc2: tptc@49a00000 {
+                       compatible = "ti,edma3-tptc";
+                       ti,hwmods = "tptc2";
+                       reg =   <0x49a00000 0x100000>;
+                       interrupts = <114>;
+                       interrupt-names = "edma3_tcerrint";
                };
 
                gpio0: gpio@44e07000 {
                };
 
                uart0: serial@44e09000 {
-                       compatible = "ti,omap3-uart";
+                       compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                        reg = <0x44e09000 0x2000>;
-                       reg-shift = <2>;
                        interrupts = <72>;
                        status = "disabled";
-                       dmas = <&edma 26>, <&edma 27>;
+                       dmas = <&edma 26 0>, <&edma 27 0>;
                        dma-names = "tx", "rx";
                };
 
                uart1: serial@48022000 {
-                       compatible = "ti,omap3-uart";
+                       compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                        reg = <0x48022000 0x2000>;
-                       reg-shift = <2>;
                        interrupts = <73>;
                        status = "disabled";
-                       dmas = <&edma 28>, <&edma 29>;
+                       dmas = <&edma 28 0>, <&edma 29 0>;
                        dma-names = "tx", "rx";
                };
 
                uart2: serial@48024000 {
-                       compatible = "ti,omap3-uart";
+                       compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                        reg = <0x48024000 0x2000>;
-                       reg-shift = <2>;
                        interrupts = <74>;
                        status = "disabled";
-                       dmas = <&edma 30>, <&edma 31>;
+                       dmas = <&edma 30 0>, <&edma 31 0>;
                        dma-names = "tx", "rx";
                };
 
                uart3: serial@481a6000 {
-                       compatible = "ti,omap3-uart";
+                       compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                        reg = <0x481a6000 0x2000>;
-                       reg-shift = <2>;
                        interrupts = <44>;
                        status = "disabled";
                };
 
                uart4: serial@481a8000 {
-                       compatible = "ti,omap3-uart";
+                       compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
                        reg = <0x481a8000 0x2000>;
-                       reg-shift = <2>;
                        interrupts = <45>;
                        status = "disabled";
                };
 
                uart5: serial@481aa000 {
-                       compatible = "ti,omap3-uart";
+                       compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
                        reg = <0x481aa000 0x2000>;
-                       reg-shift = <2>;
                        interrupts = <46>;
                        status = "disabled";
                };
                        ti,dual-volt;
                        ti,needs-special-reset;
                        ti,needs-special-hs-handling;
-                       dmas = <&edma 24
-                               &edma 25>;
+                       dmas = <&edma_xbar 24 0 0
+                               &edma_xbar 25 0 0>;
                        dma-names = "tx", "rx";
                        interrupts = <64>;
                        reg = <0x48060000 0x1000>;
                        compatible = "ti,omap4-hsmmc";
                        ti,hwmods = "mmc2";
                        ti,needs-special-reset;
-                       dmas = <&edma 2
-                               &edma 3>;
+                       dmas = <&edma 2 0
+                               &edma 3 0>;
                        dma-names = "tx", "rx";
                        interrupts = <28>;
                        reg = <0x481d8000 0x1000>;
                        status = "disabled";
                };
 
-               mailbox: mailbox@480C8000 {
+               mailbox: mailbox@480c8000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x480C8000 0x200>;
                        interrupts = <77>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <8>;
                        mbox_wkupm3: wkup_m3 {
+                               ti,mbox-send-noirq;
                                ti,mbox-tx = <0 0 0>;
                                ti,mbox-rx = <0 0 3>;
                        };
                        interrupts = <67>;
                        ti,hwmods = "timer1";
                        ti,timer-alwon;
+                       clocks = <&timer1_fck>;
+                       clock-names = "fck";
                };
 
                timer2: timer@48040000 {
                        reg = <0x48040000 0x400>;
                        interrupts = <68>;
                        ti,hwmods = "timer2";
+                       clocks = <&timer2_fck>;
+                       clock-names = "fck";
                };
 
                timer3: timer@48042000 {
                        interrupts = <75
                                      76>;
                        ti,hwmods = "rtc";
+                       clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+                       clock-names = "int-clk";
                };
 
                spi0: spi@48030000 {
                        interrupts = <65>;
                        ti,spi-num-cs = <2>;
                        ti,hwmods = "spi0";
-                       dmas = <&edma 16
-                               &edma 17
-                               &edma 18
-                               &edma 19>;
+                       dmas = <&edma 16 0
+                               &edma 17 0
+                               &edma 18 0
+                               &edma 19 0>;
                        dma-names = "tx0", "rx0", "tx1", "rx1";
                        status = "disabled";
                };
                        interrupts = <125>;
                        ti,spi-num-cs = <2>;
                        ti,hwmods = "spi1";
-                       dmas = <&edma 42
-                               &edma 43
-                               &edma 44
-                               &edma 45>;
+                       dmas = <&edma 42 0
+                               &edma 43 0
+                               &edma 44 0
+                               &edma 45 0>;
                        dma-names = "tx0", "rx0", "tx1", "rx1";
                        status = "disabled";
                };
                                reg-names = "phy";
                                status = "disabled";
                                ti,ctrl_mod = <&usb_ctrl_mod>;
+                               #phy-cells = <0>;
                        };
 
                        usb0: usb@47401000 {
                                reg-names = "phy";
                                status = "disabled";
                                ti,ctrl_mod = <&usb_ctrl_mod>;
+                               #phy-cells = <0>;
                        };
 
                        usb1: usb@47401800 {
                                  0x48300200 0x48300200 0x80>; /* EHRPWM */
 
                        ecap0: ecap@48300100 {
-                               compatible = "ti,am33xx-ecap";
+                               compatible = "ti,am3352-ecap",
+                                            "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48300100 0x80>;
+                               clocks = <&l4ls_gclk>;
+                               clock-names = "fck";
                                interrupts = <31>;
                                interrupt-names = "ecap0";
-                               ti,hwmods = "ecap0";
                                status = "disabled";
                        };
 
-                       ehrpwm0: ehrpwm@48300200 {
-                               compatible = "ti,am33xx-ehrpwm";
+                       ehrpwm0: pwm@48300200 {
+                               compatible = "ti,am3352-ehrpwm",
+                                            "ti,am33xx-ehrpwm";
                                #pwm-cells = <3>;
                                reg = <0x48300200 0x80>;
-                               ti,hwmods = "ehrpwm0";
+                               clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+                               clock-names = "tbclk", "fck";
                                status = "disabled";
                        };
                };
                                  0x48302200 0x48302200 0x80>; /* EHRPWM */
 
                        ecap1: ecap@48302100 {
-                               compatible = "ti,am33xx-ecap";
+                               compatible = "ti,am3352-ecap",
+                                            "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48302100 0x80>;
+                               clocks = <&l4ls_gclk>;
+                               clock-names = "fck";
                                interrupts = <47>;
                                interrupt-names = "ecap1";
-                               ti,hwmods = "ecap1";
                                status = "disabled";
                        };
 
-                       ehrpwm1: ehrpwm@48302200 {
-                               compatible = "ti,am33xx-ehrpwm";
+                       ehrpwm1: pwm@48302200 {
+                               compatible = "ti,am3352-ehrpwm",
+                                            "ti,am33xx-ehrpwm";
                                #pwm-cells = <3>;
                                reg = <0x48302200 0x80>;
-                               ti,hwmods = "ehrpwm1";
+                               clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
+                               clock-names = "tbclk", "fck";
                                status = "disabled";
                        };
                };
                                  0x48304200 0x48304200 0x80>; /* EHRPWM */
 
                        ecap2: ecap@48304100 {
-                               compatible = "ti,am33xx-ecap";
+                               compatible = "ti,am3352-ecap",
+                                            "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48304100 0x80>;
+                               clocks = <&l4ls_gclk>;
+                               clock-names = "fck";
                                interrupts = <61>;
                                interrupt-names = "ecap2";
-                               ti,hwmods = "ecap2";
                                status = "disabled";
                        };
 
-                       ehrpwm2: ehrpwm@48304200 {
-                               compatible = "ti,am33xx-ehrpwm";
+                       ehrpwm2: pwm@48304200 {
+                               compatible = "ti,am3352-ehrpwm",
+                                            "ti,am33xx-ehrpwm";
                                #pwm-cells = <3>;
                                reg = <0x48304200 0x80>;
-                               ti,hwmods = "ehrpwm2";
+                               clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
+                               clock-names = "tbclk", "fck";
                                status = "disabled";
                        };
                };
 
                mac: ethernet@4a100000 {
-                       compatible = "ti,cpsw";
+                       compatible = "ti,am335x-cpsw","ti,cpsw";
                        ti,hwmods = "cpgmac0";
                        clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
                        clock-names = "fck", "cpts";
                        cpdma_channels = <8>;
                        ale_entries = <1024>;
                        bd_ram_size = <0x2000>;
-                       no_bd_ram = <0>;
-                       rx_descs = <64>;
                        mac_control = <0x20>;
                        slaves = <2>;
                        active_slave = <0>;
                        status = "disabled";
 
                        davinci_mdio: mdio@4a101000 {
-                               compatible = "ti,davinci_mdio";
+                               compatible = "ti,cpsw-mdio","ti,davinci_mdio";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                ti,hwmods = "davinci_mdio";
                ocmcram: ocmcram@40300000 {
                        compatible = "mmio-sram";
                        reg = <0x40300000 0x10000>; /* 64k */
-               };
+                       ranges = <0x0 0x40300000 0x10000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
 
-               wkup_m3: wkup_m3@44d00000 {
-                       compatible = "ti,am3353-wkup-m3";
-                       reg = <0x44d00000 0x4000        /* M3 UMEM */
-                              0x44d80000 0x2000>;      /* M3 DMEM */
-                       ti,hwmods = "wkup_m3";
-                       ti,no-reset-on-init;
+                       pm_sram_code: pm-sram-code@0 {
+                               compatible = "ti,sram";
+                               reg = <0x0 0x1000>;
+                               protect-exec;
+                       };
+
+                       pm_sram_data: pm-sram-data@1000 {
+                               compatible = "ti,sram";
+                               reg = <0x1000 0x1000>;
+                               pool;
+                       };
                };
 
                elm: elm@48080000 {
                        interrupts = <16>;
                        ti,hwmods = "adc_tsc";
                        status = "disabled";
+                       dmas = <&edma 53 0>, <&edma 57 0>;
+                       dma-names = "fifo0", "fifo1";
 
                        tsc {
                                compatible = "ti,am3359-tsc";
                        };
                };
 
+               emif: emif@4c000000 {
+                       compatible = "ti,emif-am3352";
+                       reg = <0x4c000000 0x1000000>;
+                       ti,hwmods = "emif";
+                       interrupts = <101>;
+                       sram = <&pm_sram_code
+                               &pm_sram_data>;
+                       ti,no-idle;
+               };
+
                gpmc: gpmc@50000000 {
                        compatible = "ti,am3352-gpmc";
                        ti,hwmods = "gpmc";
                        ti,no-idle-on-init;
                        reg = <0x50000000 0x2000>;
                        interrupts = <100>;
+                       dmas = <&edma 52 0>;
+                       dma-names = "rxtx";
                        gpmc,num-cs = <7>;
                        gpmc,num-waitpins = <2>;
                        #address-cells = <2>;
                        #size-cells = <1>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
                        status = "disabled";
                };
 
                        ti,hwmods = "sham";
                        reg = <0x53100000 0x200>;
                        interrupts = <109>;
-                       dmas = <&edma 36>;
+                       dmas = <&edma 36 0>;
                        dma-names = "rx";
                };
 
                        ti,hwmods = "aes";
                        reg = <0x53500000 0xa0>;
                        interrupts = <103>;
-                       dmas = <&edma 6>,
-                              <&edma 5>;
+                       dmas = <&edma 6 0>,
+                              <&edma 5 0>;
                        dma-names = "tx", "rx";
                };
 
                        interrupts = <80>, <81>;
                        interrupt-names = "tx", "rx";
                        status = "disabled";
-                       dmas = <&edma 8>,
-                               <&edma 9>;
+                       dmas = <&edma 8 2>,
+                               <&edma 9 2>;
                        dma-names = "tx", "rx";
                };
 
-               mcasp1: mcasp@4803C000 {
+               mcasp1: mcasp@4803c000 {
                        compatible = "ti,am33xx-mcasp-audio";
                        ti,hwmods = "mcasp1";
                        reg = <0x4803C000 0x2000>,
                        interrupts = <82>, <83>;
                        interrupt-names = "tx", "rx";
                        status = "disabled";
-                       dmas = <&edma 10>,
-                               <&edma 11>;
+                       dmas = <&edma 10 2>,
+                               <&edma 11 2>;
                        dma-names = "tx", "rx";
                };
 
        };
 };
 
-/include/ "am33xx-clocks.dtsi"
+#include "am33xx-clocks.dtsi"
index 3ffa8e016e08b830718b06747b7c8ed022b28111..6f60a32999a1fab66af183cbe61128f40ba15eb1 100644 (file)
                                        compatible = "ti,am437-padconf",
                                                     "pinctrl-single";
                                        reg = <0x800 0x31c>;
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        #interrupt-cells = <1>;
                                        interrupt-controller;
                                        pinctrl-single,register-width = <32>;
                                scm_conf: scm_conf@0 {
                                        compatible = "syscon";
                                        reg = <0x0 0x800>;
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
 
                                        scm_clocks: clocks {
                                                #address-cells = <1>;
                        reg = <0x48038000 0x2000>,
                              <0x46000000 0x400000>;
                        reg-names = "mpu", "dat";
-                       interrupts = <80>, <81>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "tx", "rx";
                        status = "disabled";
                        dmas = <&edma 8>,
                        reg = <0x4803C000 0x2000>,
                              <0x46400000 0x400000>;
                        reg-names = "mpu", "dat";
-                       interrupts = <82>, <83>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "tx", "rx";
                        status = "disabled";
                        dmas = <&edma 10>,
                        gpmc,num-waitpins = <2>;
                        #address-cells = <2>;
                        #size-cells = <1>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
                        status = "disabled";
                };
 
index e454647165498a4c23f933e2e2c45d089a04c117..28e3e1ba32a8de33ba8ca10f3f9e8f5b2a8e68fd 100644 (file)
                compatible = "gpio-keys";
                pinctrl-names = "default";
                pinctrl-0 = <&gpio_keys_pins_default>;
-               #address-cells = <1>;
-               #size-cells = <0>;
 
                switch@0 {
                        label = "power-button";
index 276211e1ee533af0fe345047ab6d006a785f84a8..fe58faf2f785bb46a58e39d3585aaa15b0cac9f4 100644 (file)
@@ -90,8 +90,6 @@
                        dm816x_pinmux: pinmux@800 {
                                compatible = "pinctrl-single";
                                reg = <0x800 0x50a>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;
                                #pinctrl-cells = <1>;
                                pinctrl-single,register-width = <16>;
                                pinctrl-single,function-mask = <0xf>;
                        };
 
                        scrm_clocks: clocks {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
                        };
 
                        scrm_clockdomains: clockdomains {
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
new file mode 100644 (file)
index 0000000..86a8806
--- /dev/null
@@ -0,0 +1,227 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM3_H
+#define __DT_BINDINGS_CLK_AM3_H
+
+#define AM3_CLKCTRL_OFFSET     0x0
+#define AM3_CLKCTRL_INDEX(offset)      ((offset) - AM3_CLKCTRL_OFFSET)
+
+/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
+
+/* l4_per clocks */
+#define AM3_L4_PER_CLKCTRL_OFFSET      0x14
+#define AM3_L4_PER_CLKCTRL_INDEX(offset)       ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
+#define AM3_CPGMAC0_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0x14)
+#define AM3_LCDC_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x18)
+#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
+#define AM3_TPTC0_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x24)
+#define AM3_EMIF_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x28)
+#define AM3_OCMCRAM_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0x2c)
+#define AM3_GPMC_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x30)
+#define AM3_MCASP0_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x34)
+#define AM3_UART6_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x38)
+#define AM3_MMC1_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x3c)
+#define AM3_ELM_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x40)
+#define AM3_I2C3_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x44)
+#define AM3_I2C2_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x48)
+#define AM3_SPI0_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x4c)
+#define AM3_SPI1_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x50)
+#define AM3_L4_LS_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x60)
+#define AM3_MCASP1_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x68)
+#define AM3_UART2_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x6c)
+#define AM3_UART3_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x70)
+#define AM3_UART4_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x74)
+#define AM3_UART5_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x78)
+#define AM3_TIMER7_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x7c)
+#define AM3_TIMER2_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x80)
+#define AM3_TIMER3_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x84)
+#define AM3_TIMER4_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x88)
+#define AM3_RNG_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x90)
+#define AM3_AES_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x94)
+#define AM3_SHAM_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xa0)
+#define AM3_GPIO2_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xac)
+#define AM3_GPIO3_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xb0)
+#define AM3_GPIO4_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xb4)
+#define AM3_TPCC_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xbc)
+#define AM3_D_CAN0_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0xc0)
+#define AM3_D_CAN1_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0xc4)
+#define AM3_EPWMSS1_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0xcc)
+#define AM3_EPWMSS0_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0xd4)
+#define AM3_EPWMSS2_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0xd8)
+#define AM3_L3_INSTR_CLKCTRL   AM3_L4_PER_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_MAIN_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0xe0)
+#define AM3_PRUSS_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xe8)
+#define AM3_TIMER5_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0xec)
+#define AM3_TIMER6_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0xf0)
+#define AM3_MMC2_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xf4)
+#define AM3_MMC3_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xf8)
+#define AM3_TPTC1_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xfc)
+#define AM3_TPTC2_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x100)
+#define AM3_SPINLOCK_CLKCTRL   AM3_L4_PER_CLKCTRL_INDEX(0x10c)
+#define AM3_MAILBOX_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0x110)
+#define AM3_L4_HS_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x120)
+#define AM3_OCPWP_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x130)
+#define AM3_CLKDIV32K_CLKCTRL  AM3_L4_PER_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CLKCTRL_OFFSET     0x4
+#define AM3_L4_WKUP_CLKCTRL_INDEX(offset)      ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
+#define AM3_CONTROL_CLKCTRL    AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
+#define AM3_GPIO1_CLKCTRL      AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_CLKCTRL    AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
+#define AM3_DEBUGSS_CLKCTRL    AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
+#define AM3_WKUP_M3_CLKCTRL    AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
+#define AM3_UART1_CLKCTRL      AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
+#define AM3_I2C1_CLKCTRL       AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
+#define AM3_ADC_TSC_CLKCTRL    AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
+#define AM3_SMARTREFLEX0_CLKCTRL       AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
+#define AM3_TIMER1_CLKCTRL     AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
+#define AM3_SMARTREFLEX1_CLKCTRL       AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
+#define AM3_WD_TIMER2_CLKCTRL  AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
+
+/* mpu clocks */
+#define AM3_MPU_CLKCTRL_OFFSET 0x4
+#define AM3_MPU_CLKCTRL_INDEX(offset)  ((offset) - AM3_MPU_CLKCTRL_OFFSET)
+#define AM3_MPU_CLKCTRL        AM3_MPU_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_RTC_CLKCTRL        AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_CLKCTRL_OFFSET      0x4
+#define AM3_GFX_L3_CLKCTRL_INDEX(offset)       ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
+#define AM3_GFX_CLKCTRL        AM3_GFX_L3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CLKCTRL_OFFSET   0x20
+#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset)    ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
+#define AM3_CEFUSE_CLKCTRL     AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
+
+/* XXX: Compatibility part end */
+
+/* l4ls clocks */
+#define AM3_L4LS_CLKCTRL_OFFSET        0x38
+#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
+#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
+#define AM3_L4LS_MMC1_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x3c)
+#define AM3_L4LS_ELM_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x40)
+#define AM3_L4LS_I2C3_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x44)
+#define AM3_L4LS_I2C2_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x48)
+#define AM3_L4LS_SPI0_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x4c)
+#define AM3_L4LS_SPI1_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x50)
+#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
+#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c)
+#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70)
+#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74)
+#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78)
+#define AM3_L4LS_TIMER7_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0x7c)
+#define AM3_L4LS_TIMER2_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0x80)
+#define AM3_L4LS_TIMER3_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0x84)
+#define AM3_L4LS_TIMER4_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0x88)
+#define AM3_L4LS_RNG_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x90)
+#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac)
+#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0)
+#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4)
+#define AM3_L4LS_D_CAN0_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xc0)
+#define AM3_L4LS_D_CAN1_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xc4)
+#define AM3_L4LS_EPWMSS1_CLKCTRL       AM3_L4LS_CLKCTRL_INDEX(0xcc)
+#define AM3_L4LS_EPWMSS0_CLKCTRL       AM3_L4LS_CLKCTRL_INDEX(0xd4)
+#define AM3_L4LS_EPWMSS2_CLKCTRL       AM3_L4LS_CLKCTRL_INDEX(0xd8)
+#define AM3_L4LS_TIMER5_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xec)
+#define AM3_L4LS_TIMER6_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xf0)
+#define AM3_L4LS_MMC2_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xf4)
+#define AM3_L4LS_SPINLOCK_CLKCTRL      AM3_L4LS_CLKCTRL_INDEX(0x10c)
+#define AM3_L4LS_MAILBOX_CLKCTRL       AM3_L4LS_CLKCTRL_INDEX(0x110)
+#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130)
+
+/* l3s clocks */
+#define AM3_L3S_CLKCTRL_OFFSET 0x1c
+#define AM3_L3S_CLKCTRL_INDEX(offset)  ((offset) - AM3_L3S_CLKCTRL_OFFSET)
+#define AM3_L3S_USB_OTG_HS_CLKCTRL     AM3_L3S_CLKCTRL_INDEX(0x1c)
+#define AM3_L3S_GPMC_CLKCTRL   AM3_L3S_CLKCTRL_INDEX(0x30)
+#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34)
+#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68)
+#define AM3_L3S_MMC3_CLKCTRL   AM3_L3S_CLKCTRL_INDEX(0xf8)
+
+/* l3 clocks */
+#define AM3_L3_CLKCTRL_OFFSET  0x24
+#define AM3_L3_CLKCTRL_INDEX(offset)   ((offset) - AM3_L3_CLKCTRL_OFFSET)
+#define AM3_L3_TPTC0_CLKCTRL   AM3_L3_CLKCTRL_INDEX(0x24)
+#define AM3_L3_EMIF_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0x28)
+#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c)
+#define AM3_L3_AES_CLKCTRL     AM3_L3_CLKCTRL_INDEX(0x94)
+#define AM3_L3_SHAM_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0xa0)
+#define AM3_L3_TPCC_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0xbc)
+#define AM3_L3_L3_INSTR_CLKCTRL        AM3_L3_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0)
+#define AM3_L3_TPTC1_CLKCTRL   AM3_L3_CLKCTRL_INDEX(0xfc)
+#define AM3_L3_TPTC2_CLKCTRL   AM3_L3_CLKCTRL_INDEX(0x100)
+
+/* l4hs clocks */
+#define AM3_L4HS_CLKCTRL_OFFSET        0x120
+#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
+#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
+
+/* pruss_ocp clocks */
+#define AM3_PRUSS_OCP_CLKCTRL_OFFSET   0xe8
+#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset)    ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
+#define AM3_PRUSS_OCP_PRUSS_CLKCTRL    AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
+
+/* cpsw_125mhz clocks */
+#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL        AM3_CLKCTRL_INDEX(0x14)
+
+/* lcdc clocks */
+#define AM3_LCDC_CLKCTRL_OFFSET        0x18
+#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
+#define AM3_LCDC_LCDC_CLKCTRL  AM3_LCDC_CLKCTRL_INDEX(0x18)
+
+/* clk_24mhz clocks */
+#define AM3_CLK_24MHZ_CLKCTRL_OFFSET   0x14c
+#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset)    ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
+#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL        AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CONTROL_CLKCTRL    AM3_CLKCTRL_INDEX(0x4)
+#define AM3_L4_WKUP_GPIO1_CLKCTRL      AM3_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_L4_WKUP_CLKCTRL    AM3_CLKCTRL_INDEX(0xc)
+#define AM3_L4_WKUP_UART1_CLKCTRL      AM3_CLKCTRL_INDEX(0xb4)
+#define AM3_L4_WKUP_I2C1_CLKCTRL       AM3_CLKCTRL_INDEX(0xb8)
+#define AM3_L4_WKUP_ADC_TSC_CLKCTRL    AM3_CLKCTRL_INDEX(0xbc)
+#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL       AM3_CLKCTRL_INDEX(0xc0)
+#define AM3_L4_WKUP_TIMER1_CLKCTRL     AM3_CLKCTRL_INDEX(0xc4)
+#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL       AM3_CLKCTRL_INDEX(0xc8)
+#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL  AM3_CLKCTRL_INDEX(0xd4)
+
+/* l3_aon clocks */
+#define AM3_L3_AON_CLKCTRL_OFFSET      0x14
+#define AM3_L3_AON_CLKCTRL_INDEX(offset)       ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
+#define AM3_L3_AON_DEBUGSS_CLKCTRL     AM3_L3_AON_CLKCTRL_INDEX(0x14)
+
+/* l4_wkup_aon clocks */
+#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0
+#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)  ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
+#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL        AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
+
+/* mpu clocks */
+#define AM3_MPU_MPU_CLKCTRL    AM3_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL   AM3_CLKCTRL_INDEX(0x20)
+
+#endif