target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch

   1 From patchwork Sat Nov 12 14:10:58 2022
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   5 X-Patchwork-Submitter: Aurelien Jarno <aurelien@aurel32.net>
   6 X-Patchwork-Id: 13041222
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   8  <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
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  11 From: Aurelien Jarno <aurelien@aurel32.net>
  12 To: Olivia Mackall <olivia@selenic.com>,
  13         Herbert Xu <herbert@gondor.apana.org.au>,
  14         Rob Herring <robh+dt@kernel.org>,
  15         Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
  16         Heiko Stuebner <heiko@sntech.de>,
  17         Philipp Zabel <p.zabel@pengutronix.de>,
  18         Lin Jinhan <troy.lin@rock-chips.com>
  19 Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR
  20  CORE),
  21         devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE
  22  BINDINGS),
  23         linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC
  24  support),
  25         linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support),
  26         linux-kernel@vger.kernel.org (open list),
  27         Aurelien Jarno <aurelien@aurel32.net>
  28 Subject: [PATCH v1 2/3] hwrng: add Rockchip SoC hwrng driver
  29 Date: Sat, 12 Nov 2022 15:10:58 +0100
  30 Message-Id: <20221112141059.3802506-3-aurelien@aurel32.net>
  31 In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net>
  32 References: <20221112141059.3802506-1-aurelien@aurel32.net>
  33 MIME-Version: 1.0
  34 List-Id: <linux-arm-kernel.lists.infradead.org>
  35
  36 Rockchip SoCs used to have a random number generator as part of their
  37 crypto device, and support for it has to be added to the corresponding
  38 driver. However newer Rockchip SoCs like the RK356x have an independent
  39 True Random Number Generator device. This patch adds a driver for it,
  40 greatly inspired from the downstream driver.
  41
  42 The TRNG device does not seem to have a signal conditionner and the FIPS
  43 140-2 test returns a lot of failures. They can be reduced by increasing
  44 RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value
  45 has been adjusted to get ~90% of successes and the quality value has
  46 been set accordingly.
  47
  48 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
  49 ---
  50  drivers/char/hw_random/Kconfig        |  14 ++
  51  drivers/char/hw_random/Makefile       |   1 +
  52  drivers/char/hw_random/rockchip-rng.c | 251 ++++++++++++++++++++++++++
  53  3 files changed, 266 insertions(+)
  54  create mode 100644 drivers/char/hw_random/rockchip-rng.c
  55
  56 --- a/drivers/char/hw_random/Kconfig
  57 +++ b/drivers/char/hw_random/Kconfig
  58 @@ -549,6 +549,20 @@ config HW_RANDOM_CN10K
  59          To compile this driver as a module, choose M here.
  60          The module will be called cn10k_rng. If unsure, say Y.
  61
  62 +config HW_RANDOM_ROCKCHIP
  63 +        tristate "Rockchip True Random Number Generator"
  64 +        depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
  65 +        depends on HAS_IOMEM
  66 +        default HW_RANDOM
  67 +        help
  68 +          This driver provides kernel-side support for the True Random Number
  69 +          Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
  70 +
  71 +          To compile this driver as a module, choose M here: the
  72 +          module will be called rockchip-rng.
  73 +
  74 +          If unsure, say Y.
  75 +
  76  endif # HW_RANDOM
  77
  78  config UML_RANDOM
  79 --- a/drivers/char/hw_random/Makefile
  80 +++ b/drivers/char/hw_random/Makefile
  81 @@ -47,3 +47,4 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
  82  obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
  83  obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
  84  obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
  85 +obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
  86 --- /dev/null
  87 +++ b/drivers/char/hw_random/rockchip-rng.c
  88 @@ -0,0 +1,251 @@
  89 +// SPDX-License-Identifier: GPL-2.0
  90 +/*
  91 + * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
  92 + *
  93 + * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
  94 + * Copyright (c) 2022, Aurelien Jarno
  95 + * Authors:
  96 + *  Lin Jinhan <troy.lin@rock-chips.com>
  97 + *  Aurelien Jarno <aurelien@aurel32.net>
  98 + */
  99 +#include <linux/clk.h>
 100 +#include <linux/hw_random.h>
 101 +#include <linux/io.h>
 102 +#include <linux/iopoll.h>
 103 +#include <linux/kernel.h>
 104 +#include <linux/module.h>
 105 +#include <linux/of_platform.h>
 106 +#include <linux/pm_runtime.h>
 107 +#include <linux/reset.h>
 108 +#include <linux/slab.h>
 109 +
 110 +#define RK_RNG_AUTOSUSPEND_DELAY       100
 111 +#define RK_RNG_MAX_BYTE                        32
 112 +#define RK_RNG_POLL_PERIOD_US          100
 113 +#define RK_RNG_POLL_TIMEOUT_US         10000
 114 +
 115 +/*
 116 + * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
 117 + * a tradeoff between speed and quality and has been adjusted to get a quality
 118 + * of ~900 (~90% of FIPS 140-2 successes).
 119 + */
 120 +#define RK_RNG_SAMPLE_CNT              1000
 121 +
 122 +/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
 123 +#define TRNG_RST_CTL                   0x0004
 124 +#define TRNG_RNG_CTL                   0x0400
 125 +#define TRNG_RNG_CTL_LEN_64_BIT                (0x00 << 4)
 126 +#define TRNG_RNG_CTL_LEN_128_BIT       (0x01 << 4)
 127 +#define TRNG_RNG_CTL_LEN_192_BIT       (0x02 << 4)
 128 +#define TRNG_RNG_CTL_LEN_256_BIT       (0x03 << 4)
 129 +#define TRNG_RNG_CTL_OSC_RING_SPEED_0  (0x00 << 2)
 130 +#define TRNG_RNG_CTL_OSC_RING_SPEED_1  (0x01 << 2)
 131 +#define TRNG_RNG_CTL_OSC_RING_SPEED_2  (0x02 << 2)
 132 +#define TRNG_RNG_CTL_OSC_RING_SPEED_3  (0x03 << 2)
 133 +#define TRNG_RNG_CTL_ENABLE            BIT(1)
 134 +#define TRNG_RNG_CTL_START             BIT(0)
 135 +#define TRNG_RNG_SAMPLE_CNT            0x0404
 136 +#define TRNG_RNG_DOUT_0                        0x0410
 137 +#define TRNG_RNG_DOUT_1                        0x0414
 138 +#define TRNG_RNG_DOUT_2                        0x0418
 139 +#define TRNG_RNG_DOUT_3                        0x041c
 140 +#define TRNG_RNG_DOUT_4                        0x0420
 141 +#define TRNG_RNG_DOUT_5                        0x0424
 142 +#define TRNG_RNG_DOUT_6                        0x0428
 143 +#define TRNG_RNG_DOUT_7                        0x042c
 144 +
 145 +struct rk_rng {
 146 +       struct hwrng rng;
 147 +       void __iomem *base;
 148 +       struct reset_control *rst;
 149 +       int clk_num;
 150 +       struct clk_bulk_data *clk_bulks;
 151 +};
 152 +
 153 +/* The mask determine the bits that are updated */
 154 +static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
 155 +{
 156 +       writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL);
 157 +}
 158 +
 159 +static int rk_rng_init(struct hwrng *rng)
 160 +{
 161 +       struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
 162 +       u32 reg;
 163 +       int ret;
 164 +
 165 +       /* start clocks */
 166 +       ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
 167 +       if (ret < 0) {
 168 +               dev_err((struct device *) rk_rng->rng.priv,
 169 +                       "Failed to enable clks %d\n", ret);
 170 +               return ret;
 171 +       }
 172 +
 173 +       /* set the sample period */
 174 +       writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
 175 +
 176 +       /* set osc ring speed and enable it */
 177 +       reg = TRNG_RNG_CTL_LEN_256_BIT |
 178 +                  TRNG_RNG_CTL_OSC_RING_SPEED_0 |
 179 +                  TRNG_RNG_CTL_ENABLE;
 180 +       rk_rng_write_ctl(rk_rng, reg, 0xffff);
 181 +
 182 +       return 0;
 183 +}
 184 +
 185 +static void rk_rng_cleanup(struct hwrng *rng)
 186 +{
 187 +       struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
 188 +       u32 reg;
 189 +
 190 +       /* stop TRNG */
 191 +       reg = 0;
 192 +       rk_rng_write_ctl(rk_rng, reg, 0xffff);
 193 +
 194 +       /* stop clocks */
 195 +       clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
 196 +}
 197 +
 198 +static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
 199 +{
 200 +       struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
 201 +       u32 reg;
 202 +       int ret = 0;
 203 +       int i;
 204 +
 205 +       pm_runtime_get_sync((struct device *) rk_rng->rng.priv);
 206 +
 207 +       /* Start collecting random data */
 208 +       reg = TRNG_RNG_CTL_START;
 209 +       rk_rng_write_ctl(rk_rng, reg, reg);
 210 +
 211 +       ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
 212 +                                !(reg & TRNG_RNG_CTL_START),
 213 +                                RK_RNG_POLL_PERIOD_US,
 214 +                                RK_RNG_POLL_TIMEOUT_US);
 215 +       if (ret < 0)
 216 +               goto out;
 217 +
 218 +       /* Read random data stored in big endian in the registers */
 219 +       ret = min_t(size_t, max, RK_RNG_MAX_BYTE);
 220 +       for (i = 0; i < ret; i += 4) {
 221 +               reg = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i);
 222 +               *(u32 *)(buf + i) = be32_to_cpu(reg);
 223 +       }
 224 +
 225 +out:
 226 +       pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
 227 +       pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
 228 +
 229 +       return ret;
 230 +}
 231 +
 232 +static int rk_rng_probe(struct platform_device *pdev)
 233 +{
 234 +       struct device *dev = &pdev->dev;
 235 +       struct rk_rng *rk_rng;
 236 +       int ret;
 237 +
 238 +       rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL);
 239 +       if (!rk_rng)
 240 +               return -ENOMEM;
 241 +
 242 +       rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
 243 +       if (IS_ERR(rk_rng->base))
 244 +               return PTR_ERR(rk_rng->base);
 245 +
 246 +       rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
 247 +       if (rk_rng->clk_num < 0)
 248 +               return dev_err_probe(dev, rk_rng->clk_num,
 249 +                                    "Failed to get clks property\n");
 250 +
 251 +       rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false);
 252 +       if (IS_ERR(rk_rng->rst))
 253 +               return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
 254 +                                    "Failed to get reset property\n");
 255 +
 256 +       reset_control_assert(rk_rng->rst);
 257 +       udelay(2);
 258 +       reset_control_deassert(rk_rng->rst);
 259 +
 260 +       platform_set_drvdata(pdev, rk_rng);
 261 +
 262 +       rk_rng->rng.name = dev_driver_string(dev);
 263 +#ifndef CONFIG_PM
 264 +       rk_rng->rng.init = rk_rng_init;
 265 +       rk_rng->rng.cleanup = rk_rng_cleanup;
 266 +#endif
 267 +       rk_rng->rng.read = rk_rng_read;
 268 +       rk_rng->rng.priv = (unsigned long) dev;
 269 +       rk_rng->rng.quality = 900;
 270 +
 271 +       pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
 272 +       pm_runtime_use_autosuspend(dev);
 273 +       pm_runtime_enable(dev);
 274 +
 275 +       ret = devm_hwrng_register(dev, &rk_rng->rng);
 276 +       if (ret)
 277 +               return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
 278 +
 279 +       dev_info(&pdev->dev, "Registered Rockchip hwrng\n");
 280 +
 281 +       return 0;
 282 +}
 283 +
 284 +static int rk_rng_remove(struct platform_device *pdev)
 285 +{
 286 +       pm_runtime_disable(&pdev->dev);
 287 +
 288 +       return 0;
 289 +}
 290 +
 291 +#ifdef CONFIG_PM
 292 +static int rk_rng_runtime_suspend(struct device *dev)
 293 +{
 294 +       struct rk_rng *rk_rng = dev_get_drvdata(dev);
 295 +
 296 +       rk_rng_cleanup(&rk_rng->rng);
 297 +
 298 +       return 0;
 299 +}
 300 +
 301 +static int rk_rng_runtime_resume(struct device *dev)
 302 +{
 303 +       struct rk_rng *rk_rng = dev_get_drvdata(dev);
 304 +
 305 +       return rk_rng_init(&rk_rng->rng);
 306 +}
 307 +#endif
 308 +
 309 +static const struct dev_pm_ops rk_rng_pm_ops = {
 310 +       SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
 311 +                               rk_rng_runtime_resume, NULL)
 312 +       SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 313 +                               pm_runtime_force_resume)
 314 +};
 315 +
 316 +static const struct of_device_id rk_rng_dt_match[] = {
 317 +       {
 318 +               .compatible = "rockchip,rk3568-rng",
 319 +       },
 320 +       {},
 321 +};
 322 +
 323 +MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
 324 +
 325 +static struct platform_driver rk_rng_driver = {
 326 +       .driver = {
 327 +               .name   = "rockchip-rng",
 328 +               .pm     = &rk_rng_pm_ops,
 329 +               .of_match_table = rk_rng_dt_match,
 330 +       },
 331 +       .probe  = rk_rng_probe,
 332 +       .remove = rk_rng_remove,
 333 +};
 334 +
 335 +module_platform_driver(rk_rng_driver);
 336 +
 337 +MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
 338 +MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>, Aurelien Jarno <aurelien@aurel32.net>");
 339 +MODULE_LICENSE("GPL v2");