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realtek: improve EEE support for RTL8380/8390/9300
[openwrt/staging/zorun.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_write_cam(int idx, u32 *r)
30 {
31 u32 cmd = BIT(16) /* Execute cmd */
32 | BIT(15) /* Read */
33 | BIT(13) /* Table type 0b01 */
34 | (idx & 0x3f);
35
36 sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
37 sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
38 sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
39
40 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
41 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
42 }
43
44 static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
45 {
46 switch (priv->family_id) {
47 case RTL8380_FAMILY_ID:
48 return rtl838x_hash(priv, mac << 12 | vid);
49 case RTL8390_FAMILY_ID:
50 return rtl839x_hash(priv, mac << 12 | vid);
51 case RTL9300_FAMILY_ID:
52 return rtl930x_hash(priv, ((u64)vid) << 48 | mac);
53 default:
54 pr_err("Hash not implemented\n");
55 }
56 return 0;
57 }
58
59 static void rtl83xx_write_hash(int idx, u32 *r)
60 {
61 u32 cmd = BIT(16) /* Execute cmd */
62 | 0 << 15 /* Write */
63 | 0 << 13 /* Table type 0b00 */
64 | (idx & 0x1fff);
65
66 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
67 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
68 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
69 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
70 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
71 }
72
73 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
74 {
75 int i;
76 u64 v = 0;
77
78 msleep(1000);
79 /* Enable all ports with a PHY, including the SFP-ports */
80 for (i = 0; i < priv->cpu_port; i++) {
81 if (priv->ports[i].phy)
82 v |= BIT(i);
83 }
84
85 pr_debug("%s: %16llx\n", __func__, v);
86 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
87
88 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
89 if (priv->family_id == RTL8390_FAMILY_ID)
90 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
91 else if(priv->family_id == RTL9300_FAMILY_ID)
92 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
93 }
94
95 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
96 MIB_DESC(2, 0xf8, "ifInOctets"),
97 MIB_DESC(2, 0xf0, "ifOutOctets"),
98 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
99 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
100 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
101 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
102 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
103 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
104 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
105 MIB_DESC(1, 0xd0, "ifOutDiscards"),
106 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
107 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
108 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
109 MIB_DESC(1, 0xc0, ".3LateCollisions"),
110 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
111 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
112 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
113 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
114 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
115 MIB_DESC(1, 0xa8, "DropEvents"),
116 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
117 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
118 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
119 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
120 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
121 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
122 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
123 MIB_DESC(1, 0x88, "rx_OversizePkts"),
124 MIB_DESC(1, 0x84, "Fragments"),
125 MIB_DESC(1, 0x80, "Jabbers"),
126 MIB_DESC(1, 0x7c, "Collisions"),
127 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
128 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
129 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
130 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
131 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
132 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
133 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
134 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
135 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
136 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
137 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
138 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
139 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
140 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
141 MIB_DESC(1, 0x40, "rxMacDiscards")
142 };
143
144
145 /* DSA callbacks */
146
147
148 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
149 {
150 /* The switch does not tag the frames, instead internally the header
151 * structure for each packet is tagged accordingly.
152 */
153 return DSA_TAG_PROTO_TRAILER;
154 }
155
156 static int rtl83xx_setup(struct dsa_switch *ds)
157 {
158 int i;
159 struct rtl838x_switch_priv *priv = ds->priv;
160 u64 port_bitmap = BIT_ULL(priv->cpu_port);
161
162 pr_debug("%s called\n", __func__);
163
164 /* Disable MAC polling the PHY so that we can start configuration */
165 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
166
167 for (i = 0; i < ds->num_ports; i++)
168 priv->ports[i].enable = false;
169 priv->ports[priv->cpu_port].enable = true;
170
171 /* Isolate ports from each other: traffic only CPU <-> port */
172 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
173 * traffic from source port i to destination port j
174 */
175 for (i = 0; i < priv->cpu_port; i++) {
176 if (priv->ports[i].phy) {
177 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i),
178 priv->r->port_iso_ctrl(i));
179 port_bitmap |= BIT_ULL(i);
180 }
181 }
182 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
183
184 if (priv->family_id == RTL8380_FAMILY_ID)
185 rtl838x_print_matrix();
186 else
187 rtl839x_print_matrix();
188
189 rtl83xx_init_stats(priv);
190
191 ds->configure_vlan_while_not_filtering = true;
192
193 /* Enable MAC Polling PHY again */
194 rtl83xx_enable_phy_polling(priv);
195 pr_debug("Please wait until PHY is settled\n");
196 msleep(1000);
197 return 0;
198 }
199
200 static int rtl930x_setup(struct dsa_switch *ds)
201 {
202 int i;
203 struct rtl838x_switch_priv *priv = ds->priv;
204 u32 port_bitmap = BIT(priv->cpu_port);
205
206 pr_info("%s called\n", __func__);
207
208 // Enable CSTI STP mode
209 // sw_w32(1, RTL930X_ST_CTRL);
210
211 /* Disable MAC polling the PHY so that we can start configuration */
212 sw_w32(0, RTL930X_SMI_POLL_CTRL);
213
214 // Disable all ports except CPU port
215 for (i = 0; i < ds->num_ports; i++)
216 priv->ports[i].enable = false;
217 priv->ports[priv->cpu_port].enable = true;
218
219 for (i = 0; i < priv->cpu_port; i++) {
220 if (priv->ports[i].phy) {
221 priv->r->traffic_set(i, BIT(priv->cpu_port) | BIT(i));
222 port_bitmap |= 1ULL << i;
223 }
224 }
225 priv->r->traffic_set(priv->cpu_port, port_bitmap);
226
227 rtl930x_print_matrix();
228
229 // TODO: Initialize statistics
230
231 ds->configure_vlan_while_not_filtering = true;
232
233 rtl83xx_enable_phy_polling(priv);
234
235 return 0;
236 }
237
238 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
239 unsigned long *supported,
240 struct phylink_link_state *state)
241 {
242 struct rtl838x_switch_priv *priv = ds->priv;
243 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
244
245 pr_debug("In %s port %d", __func__, port);
246
247 if (!phy_interface_mode_is_rgmii(state->interface) &&
248 state->interface != PHY_INTERFACE_MODE_NA &&
249 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
250 state->interface != PHY_INTERFACE_MODE_MII &&
251 state->interface != PHY_INTERFACE_MODE_REVMII &&
252 state->interface != PHY_INTERFACE_MODE_GMII &&
253 state->interface != PHY_INTERFACE_MODE_QSGMII &&
254 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
255 state->interface != PHY_INTERFACE_MODE_SGMII) {
256 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
257 dev_err(ds->dev,
258 "Unsupported interface: %d for port %d\n",
259 state->interface, port);
260 return;
261 }
262
263 /* Allow all the expected bits */
264 phylink_set(mask, Autoneg);
265 phylink_set_port_modes(mask);
266 phylink_set(mask, Pause);
267 phylink_set(mask, Asym_Pause);
268
269 /* With the exclusion of MII and Reverse MII, we support Gigabit,
270 * including Half duplex
271 */
272 if (state->interface != PHY_INTERFACE_MODE_MII &&
273 state->interface != PHY_INTERFACE_MODE_REVMII) {
274 phylink_set(mask, 1000baseT_Full);
275 phylink_set(mask, 1000baseT_Half);
276 }
277
278 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
279 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
280 phylink_set(mask, 1000baseX_Full);
281
282 phylink_set(mask, 10baseT_Half);
283 phylink_set(mask, 10baseT_Full);
284 phylink_set(mask, 100baseT_Half);
285 phylink_set(mask, 100baseT_Full);
286
287 bitmap_and(supported, supported, mask,
288 __ETHTOOL_LINK_MODE_MASK_NBITS);
289 bitmap_and(state->advertising, state->advertising, mask,
290 __ETHTOOL_LINK_MODE_MASK_NBITS);
291 }
292
293 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
294 struct phylink_link_state *state)
295 {
296 struct rtl838x_switch_priv *priv = ds->priv;
297 u64 speed;
298 u64 link;
299
300 if (port < 0 || port > priv->cpu_port)
301 return -EINVAL;
302
303 /*
304 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
305 * state needs to be read twice in order to read a correct result.
306 * This would not be necessary for ports connected e.g. to RTL8218D
307 * PHYs.
308 */
309 state->link = 0;
310 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
311 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
312 if (link & BIT_ULL(port))
313 state->link = 1;
314 pr_debug("%s: link state: %llx\n", __func__, link & BIT_ULL(port));
315
316 state->duplex = 0;
317 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
318 state->duplex = 1;
319
320 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
321 speed >>= (port % 16) << 1;
322 switch (speed & 0x3) {
323 case 0:
324 state->speed = SPEED_10;
325 break;
326 case 1:
327 state->speed = SPEED_100;
328 break;
329 case 2:
330 state->speed = SPEED_1000;
331 break;
332 case 3:
333 if (port == 24 || port == 26) /* Internal serdes */
334 state->speed = SPEED_2500;
335 else
336 state->speed = SPEED_100; /* Is in fact 500Mbit */
337 }
338
339 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
340 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
341 state->pause |= MLO_PAUSE_RX;
342 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
343 state->pause |= MLO_PAUSE_TX;
344 return 1;
345 }
346
347
348 static void rtl83xx_config_interface(int port, phy_interface_t interface)
349 {
350 u32 old, int_shift, sds_shift;
351
352 switch (port) {
353 case 24:
354 int_shift = 0;
355 sds_shift = 5;
356 break;
357 case 26:
358 int_shift = 3;
359 sds_shift = 0;
360 break;
361 default:
362 return;
363 }
364
365 old = sw_r32(RTL838X_SDS_MODE_SEL);
366 switch (interface) {
367 case PHY_INTERFACE_MODE_1000BASEX:
368 if ((old >> sds_shift & 0x1f) == 4)
369 return;
370 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
371 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
372 break;
373 case PHY_INTERFACE_MODE_SGMII:
374 if ((old >> sds_shift & 0x1f) == 2)
375 return;
376 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
377 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
378 break;
379 default:
380 return;
381 }
382 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
383 }
384
385 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
386 unsigned int mode,
387 const struct phylink_link_state *state)
388 {
389 struct rtl838x_switch_priv *priv = ds->priv;
390 u32 reg;
391 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
392
393 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
394
395 // BUG: Make this work on RTL93XX
396 if (priv->family_id >= RTL9300_FAMILY_ID)
397 return;
398
399 if (port == priv->cpu_port) {
400 /* Set Speed, duplex, flow control
401 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
402 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
403 * | MEDIA_SEL
404 */
405 if (priv->family_id == RTL8380_FAMILY_ID) {
406 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
407 /* allow CRC errors on CPU-port */
408 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
409 } else {
410 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
411 }
412 return;
413 }
414
415 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
416 /* Auto-Negotiation does not work for MAC in RTL8390 */
417 if (priv->family_id == RTL8380_FAMILY_ID) {
418 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
419 pr_debug("PHY autonegotiates\n");
420 reg |= BIT(2);
421 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
422 rtl83xx_config_interface(port, state->interface);
423 return;
424 }
425 }
426
427 if (mode != MLO_AN_FIXED)
428 pr_debug("Fixed state.\n");
429
430 if (priv->family_id == RTL8380_FAMILY_ID) {
431 /* Clear id_mode_dis bit, and the existing port mode, let
432 * RGMII_MODE_EN bet set by mac_link_{up,down}
433 */
434 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
435
436 if (state->pause & MLO_PAUSE_TXRX_MASK) {
437 if (state->pause & MLO_PAUSE_TX)
438 reg |= TX_PAUSE_EN;
439 reg |= RX_PAUSE_EN;
440 }
441 }
442
443 reg &= ~(3 << speed_bit);
444 switch (state->speed) {
445 case SPEED_1000:
446 reg |= 2 << speed_bit;
447 break;
448 case SPEED_100:
449 reg |= 1 << speed_bit;
450 break;
451 }
452
453 if (priv->family_id == RTL8380_FAMILY_ID) {
454 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
455 if (state->link)
456 reg |= FORCE_LINK_EN;
457 if (state->duplex == DUPLEX_FULL)
458 reg |= DUPLX_MODE;
459 }
460
461 // Disable AN
462 if (priv->family_id == RTL8380_FAMILY_ID)
463 reg &= ~BIT(2);
464 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
465 }
466
467 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
468 unsigned int mode,
469 phy_interface_t interface)
470 {
471 struct rtl838x_switch_priv *priv = ds->priv;
472 /* Stop TX/RX to port */
473 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
474 }
475
476 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
477 unsigned int mode,
478 phy_interface_t interface,
479 struct phy_device *phydev)
480 {
481 struct rtl838x_switch_priv *priv = ds->priv;
482 /* Restart TX/RX to port */
483 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
484 }
485
486 static void rtl83xx_get_strings(struct dsa_switch *ds,
487 int port, u32 stringset, u8 *data)
488 {
489 int i;
490
491 if (stringset != ETH_SS_STATS)
492 return;
493
494 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
495 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
496 ETH_GSTRING_LEN);
497 }
498
499 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
500 uint64_t *data)
501 {
502 struct rtl838x_switch_priv *priv = ds->priv;
503 const struct rtl83xx_mib_desc *mib;
504 int i;
505 u64 h;
506
507 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
508 mib = &rtl83xx_mib[i];
509
510 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
511 if (mib->size == 2) {
512 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
513 data[i] |= h << 32;
514 }
515 }
516 }
517
518 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
519 {
520 if (sset != ETH_SS_STATS)
521 return 0;
522
523 return ARRAY_SIZE(rtl83xx_mib);
524 }
525
526 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
527 struct phy_device *phydev)
528 {
529 struct rtl838x_switch_priv *priv = ds->priv;
530 u64 v;
531
532 pr_debug("%s: %x %d", __func__, (u32) priv, port);
533 priv->ports[port].enable = true;
534
535 /* enable inner tagging on egress, do not keep any tags */
536 if (priv->family_id == RTL9310_FAMILY_ID)
537 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
538 else
539 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
540
541 if (dsa_is_cpu_port(ds, port))
542 return 0;
543
544 /* add port to switch mask of CPU_PORT */
545 priv->r->traffic_enable(priv->cpu_port, port);
546
547 /* add all other ports in the same bridge to switch mask of port */
548 v = priv->r->traffic_get(port);
549 v |= priv->ports[port].pm;
550 priv->r->traffic_set(port, v);
551
552 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
553 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
554
555 return 0;
556 }
557
558 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
559 {
560 struct rtl838x_switch_priv *priv = ds->priv;
561 u64 v;
562
563 pr_debug("%s %x: %d", __func__, (u32)priv, port);
564 /* you can only disable user ports */
565 if (!dsa_is_user_port(ds, port))
566 return;
567
568 // BUG: This does not work on RTL931X
569 /* remove port from switch mask of CPU_PORT */
570 priv->r->traffic_disable(priv->cpu_port, port);
571
572 /* remove all other ports in the same bridge from switch mask of port */
573 v = priv->r->traffic_get(port);
574 v &= ~priv->ports[port].pm;
575 priv->r->traffic_set(port, v);
576
577 priv->ports[port].enable = false;
578 }
579
580 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
581 struct ethtool_eee *e)
582 {
583 struct rtl838x_switch_priv *priv = ds->priv;
584
585 if (e->eee_enabled && !priv->eee_enabled) {
586 pr_info("Globally enabling EEE\n");
587 priv->r->init_eee(priv, true);
588 }
589
590 priv->r->port_eee_set(priv, port, e->eee_enabled);
591
592 if (e->eee_enabled)
593 pr_info("Enabled EEE for port %d\n", port);
594 else
595 pr_info("Disabled EEE for port %d\n", port);
596 return 0;
597 }
598
599 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
600 struct ethtool_eee *e)
601 {
602 struct rtl838x_switch_priv *priv = ds->priv;
603
604 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
605
606 priv->r->eee_port_ability(priv, e, port);
607
608 e->eee_enabled = priv->ports[port].eee_enabled;
609
610 e->eee_active = !!(e->advertised & e->lp_advertised);
611
612 return 0;
613 }
614
615 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
616 struct ethtool_eee *e)
617 {
618 struct rtl838x_switch_priv *priv = ds->priv;
619
620 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
621 | SUPPORTED_2500baseX_Full;
622
623 priv->r->eee_port_ability(priv, e, port);
624
625 e->eee_enabled = priv->ports[port].eee_enabled;
626
627 e->eee_active = !!(e->advertised & e->lp_advertised);
628
629 return 0;
630 }
631
632 /*
633 * Set Switch L2 Aging time, t is time in milliseconds
634 * t = 0: aging is disabled
635 */
636 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
637 {
638 struct rtl838x_switch_priv *priv = ds->priv;
639 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
640
641 /* Convert time in mseconds to internal value */
642 if (t > 0x10000000) { /* Set to maximum */
643 t = t_max;
644 } else {
645 if (priv->family_id == RTL8380_FAMILY_ID)
646 t = ((t * 625) / 1000 + 127) / 128;
647 else
648 t = (t * 5 + 2) / 3;
649 }
650 sw_w32(t, priv->r->l2_ctrl_1);
651 return 0;
652 }
653
654 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
655 struct net_device *bridge)
656 {
657 struct rtl838x_switch_priv *priv = ds->priv;
658 u64 port_bitmap = 1ULL << priv->cpu_port, v;
659 int i;
660
661 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
662 mutex_lock(&priv->reg_mutex);
663 for (i = 0; i < ds->num_ports; i++) {
664 /* Add this port to the port matrix of the other ports in the
665 * same bridge. If the port is disabled, port matrix is kept
666 * and not being setup until the port becomes enabled.
667 */
668 if (dsa_is_user_port(ds, i) && i != port) {
669 if (dsa_to_port(ds, i)->bridge_dev != bridge)
670 continue;
671 if (priv->ports[i].enable)
672 priv->r->traffic_enable(i, port);
673
674 priv->ports[i].pm |= 1ULL << port;
675 port_bitmap |= 1ULL << i;
676 }
677 }
678
679 /* Add all other ports to this port matrix. */
680 if (priv->ports[port].enable) {
681 priv->r->traffic_enable(priv->cpu_port, port);
682 v = priv->r->traffic_get(port);
683 v |= port_bitmap;
684 priv->r->traffic_set(port, v);
685 }
686 priv->ports[port].pm |= port_bitmap;
687 mutex_unlock(&priv->reg_mutex);
688
689 return 0;
690 }
691
692 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
693 struct net_device *bridge)
694 {
695 struct rtl838x_switch_priv *priv = ds->priv;
696 u64 port_bitmap = 1ULL << priv->cpu_port, v;
697 int i;
698
699 pr_debug("%s %x: %d", __func__, (u32)priv, port);
700 mutex_lock(&priv->reg_mutex);
701 for (i = 0; i < ds->num_ports; i++) {
702 /* Remove this port from the port matrix of the other ports
703 * in the same bridge. If the port is disabled, port matrix
704 * is kept and not being setup until the port becomes enabled.
705 * And the other port's port matrix cannot be broken when the
706 * other port is still a VLAN-aware port.
707 */
708 if (dsa_is_user_port(ds, i) && i != port) {
709 if (dsa_to_port(ds, i)->bridge_dev != bridge)
710 continue;
711 if (priv->ports[i].enable)
712 priv->r->traffic_disable(i, port);
713
714 priv->ports[i].pm |= 1ULL << port;
715 port_bitmap &= ~BIT_ULL(i);
716 }
717 }
718
719 /* Add all other ports to this port matrix. */
720 if (priv->ports[port].enable) {
721 v = priv->r->traffic_get(port);
722 v |= port_bitmap;
723 priv->r->traffic_set(port, v);
724 }
725 priv->ports[port].pm &= ~port_bitmap;
726
727 mutex_unlock(&priv->reg_mutex);
728 }
729
730 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
731 {
732 u32 msti = 0;
733 u32 port_state[4];
734 int index, bit;
735 int pos = port;
736 struct rtl838x_switch_priv *priv = ds->priv;
737 int n = priv->port_width << 1;
738
739 /* Ports above or equal CPU port can never be configured */
740 if (port >= priv->cpu_port)
741 return;
742
743 mutex_lock(&priv->reg_mutex);
744
745 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
746 * have 64 bit fields, 839x and 931x have 128 bit fields
747 */
748 if (priv->family_id == RTL8390_FAMILY_ID)
749 pos += 12;
750 if (priv->family_id == RTL9300_FAMILY_ID)
751 pos += 3;
752 if (priv->family_id == RTL9310_FAMILY_ID)
753 pos += 8;
754
755 index = n - (pos >> 4) - 1;
756 bit = (pos << 1) % 32;
757
758 priv->r->stp_get(priv, msti, port_state);
759
760 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
761 port_state[index] &= ~(3 << bit);
762
763 switch (state) {
764 case BR_STATE_DISABLED: /* 0 */
765 port_state[index] |= (0 << bit);
766 break;
767 case BR_STATE_BLOCKING: /* 4 */
768 case BR_STATE_LISTENING: /* 1 */
769 port_state[index] |= (1 << bit);
770 break;
771 case BR_STATE_LEARNING: /* 2 */
772 port_state[index] |= (2 << bit);
773 break;
774 case BR_STATE_FORWARDING: /* 3*/
775 port_state[index] |= (3 << bit);
776 default:
777 break;
778 }
779
780 priv->r->stp_set(priv, msti, port_state);
781
782 mutex_unlock(&priv->reg_mutex);
783 }
784
785 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
786 {
787 struct rtl838x_switch_priv *priv = ds->priv;
788 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
789
790 pr_debug("FAST AGE port %d\n", port);
791 mutex_lock(&priv->reg_mutex);
792 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
793 * port fields:
794 * 0-4: Replacing port
795 * 5-9: Flushed/replaced port
796 * 10-21: FVID
797 * 22: Entry types: 1: dynamic, 0: also static
798 * 23: Match flush port
799 * 24: Match FVID
800 * 25: Flush (0) or replace (1) L2 entries
801 * 26: Status of action (1: Start, 0: Done)
802 */
803 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
804
805 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
806
807 mutex_unlock(&priv->reg_mutex);
808 }
809
810 void rtl930x_fast_age(struct dsa_switch *ds, int port)
811 {
812 struct rtl838x_switch_priv *priv = ds->priv;
813
814 pr_debug("FAST AGE port %d\n", port);
815 mutex_lock(&priv->reg_mutex);
816 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
817
818 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
819
820 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
821
822 mutex_unlock(&priv->reg_mutex);
823 }
824
825 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
826 bool vlan_filtering)
827 {
828 struct rtl838x_switch_priv *priv = ds->priv;
829
830 pr_debug("%s: port %d\n", __func__, port);
831 mutex_lock(&priv->reg_mutex);
832
833 if (vlan_filtering) {
834 /* Enable ingress and egress filtering
835 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
836 * the filter action:
837 * 0: Always Forward
838 * 1: Drop packet
839 * 2: Trap packet to CPU port
840 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
841 */
842 if (port != priv->cpu_port)
843 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
844 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
845 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
846 } else {
847 /* Disable ingress and egress filtering */
848 if (port != priv->cpu_port)
849 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
850 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
851 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
852 }
853
854 /* Do we need to do something to the CPU-Port, too? */
855 mutex_unlock(&priv->reg_mutex);
856
857 return 0;
858 }
859
860 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
861 const struct switchdev_obj_port_vlan *vlan)
862 {
863 struct rtl838x_vlan_info info;
864 struct rtl838x_switch_priv *priv = ds->priv;
865
866 pr_info("%s: port %d\n", __func__, port);
867
868 mutex_lock(&priv->reg_mutex);
869
870 priv->r->vlan_profile_dump(1);
871 priv->r->vlan_tables_read(1, &info);
872
873 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
874 info.tagged_ports, info.untagged_ports, info.profile_id,
875 info.hash_mc_fid, info.hash_uc_fid, info.fid);
876
877 priv->r->vlan_set_untagged(1, info.untagged_ports);
878 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
879
880 priv->r->vlan_set_tagged(1, &info);
881 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
882
883 mutex_unlock(&priv->reg_mutex);
884 return 0;
885 }
886
887 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
888 const struct switchdev_obj_port_vlan *vlan)
889 {
890 struct rtl838x_vlan_info info;
891 struct rtl838x_switch_priv *priv = ds->priv;
892 int v;
893
894 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
895 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
896
897 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
898 dev_err(priv->dev, "VLAN out of range: %d - %d",
899 vlan->vid_begin, vlan->vid_end);
900 return;
901 }
902
903 mutex_lock(&priv->reg_mutex);
904
905 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
906 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
907 if (!v)
908 continue;
909 /* Set both inner and outer PVID of the port */
910 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
911 priv->ports[port].pvid = vlan->vid_end;
912 }
913 }
914
915 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
916 if (!v)
917 continue;
918
919 /* Get port memberships of this vlan */
920 priv->r->vlan_tables_read(v, &info);
921
922 /* new VLAN? */
923 if (!info.tagged_ports) {
924 info.fid = 0;
925 info.hash_mc_fid = false;
926 info.hash_uc_fid = false;
927 info.profile_id = 0;
928 }
929
930 /* sanitize untagged_ports - must be a subset */
931 if (info.untagged_ports & ~info.tagged_ports)
932 info.untagged_ports = 0;
933
934 info.tagged_ports |= BIT_ULL(port);
935 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
936 info.untagged_ports |= BIT_ULL(port);
937
938 priv->r->vlan_set_untagged(v, info.untagged_ports);
939 pr_info("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
940
941 priv->r->vlan_set_tagged(v, &info);
942 pr_info("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
943 }
944
945 mutex_unlock(&priv->reg_mutex);
946 }
947
948 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
949 const struct switchdev_obj_port_vlan *vlan)
950 {
951 struct rtl838x_vlan_info info;
952 struct rtl838x_switch_priv *priv = ds->priv;
953 int v;
954 u16 pvid;
955
956 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
957 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
958
959 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
960 dev_err(priv->dev, "VLAN out of range: %d - %d",
961 vlan->vid_begin, vlan->vid_end);
962 return -ENOTSUPP;
963 }
964
965 mutex_lock(&priv->reg_mutex);
966 pvid = priv->ports[port].pvid;
967
968 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
969 /* Reset to default if removing the current PVID */
970 if (v == pvid)
971 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
972
973 /* Get port memberships of this vlan */
974 priv->r->vlan_tables_read(v, &info);
975
976 /* remove port from both tables */
977 info.untagged_ports &= (~BIT_ULL(port));
978 /* always leave vid 1 */
979 if (v != 1)
980 info.tagged_ports &= (~BIT_ULL(port));
981
982 priv->r->vlan_set_untagged(v, info.untagged_ports);
983 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
984
985 priv->r->vlan_set_tagged(v, &info);
986 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
987 }
988 mutex_unlock(&priv->reg_mutex);
989
990 return 0;
991 }
992
993 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
994 const unsigned char *addr, u16 vid)
995 {
996 struct rtl838x_switch_priv *priv = ds->priv;
997 u64 mac = ether_addr_to_u64(addr);
998 u32 key = rtl83xx_hash_key(priv, mac, vid);
999 struct rtl838x_l2_entry e;
1000 u32 r[3];
1001 u64 entry;
1002 int idx = -1, err = 0, i;
1003
1004 mutex_lock(&priv->reg_mutex);
1005 for (i = 0; i < 4; i++) {
1006 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
1007 if (!e.valid) {
1008 idx = (key << 2) | i;
1009 break;
1010 }
1011 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1012 idx = (key << 2) | i;
1013 break;
1014 }
1015 }
1016 if (idx >= 0) {
1017 r[0] = 3 << 17 | port << 12; // Aging and port
1018 r[0] |= vid;
1019 r[1] = mac >> 16;
1020 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1021 rtl83xx_write_hash(idx, r);
1022 goto out;
1023 }
1024
1025 /* Hash buckets full, try CAM */
1026 for (i = 0; i < 64; i++) {
1027 entry = priv->r->read_cam(i, &e);
1028 if (!e.valid) {
1029 if (idx < 0) /* First empty entry? */
1030 idx = i;
1031 break;
1032 } else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1033 pr_debug("Found entry in CAM\n");
1034 idx = i;
1035 break;
1036 }
1037 }
1038 if (idx >= 0) {
1039 r[0] = 3 << 17 | port << 12; // Aging
1040 r[0] |= vid;
1041 r[1] = mac >> 16;
1042 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1043 rtl83xx_write_cam(idx, r);
1044 goto out;
1045 }
1046 err = -ENOTSUPP;
1047 out:
1048 mutex_unlock(&priv->reg_mutex);
1049 return err;
1050 }
1051
1052 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1053 const unsigned char *addr, u16 vid)
1054 {
1055 struct rtl838x_switch_priv *priv = ds->priv;
1056 u64 mac = ether_addr_to_u64(addr);
1057 u32 key = rtl83xx_hash_key(priv, mac, vid);
1058 struct rtl838x_l2_entry e;
1059 u32 r[3];
1060 u64 entry;
1061 int idx = -1, err = 0, i;
1062
1063 pr_debug("In %s, mac %llx, vid: %d, key: %x08x\n", __func__, mac, vid, key);
1064 mutex_lock(&priv->reg_mutex);
1065 for (i = 0; i < 4; i++) {
1066 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
1067 if (!e.valid)
1068 continue;
1069 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1070 idx = (key << 2) | i;
1071 break;
1072 }
1073 }
1074
1075 if (idx >= 0) {
1076 r[0] = r[1] = r[2] = 0;
1077 rtl83xx_write_hash(idx, r);
1078 goto out;
1079 }
1080
1081 /* Check CAM for spillover from hash buckets */
1082 for (i = 0; i < 64; i++) {
1083 entry = priv->r->read_cam(i, &e);
1084 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1085 idx = i;
1086 break;
1087 }
1088 }
1089 if (idx >= 0) {
1090 r[0] = r[1] = r[2] = 0;
1091 rtl83xx_write_cam(idx, r);
1092 goto out;
1093 }
1094 err = -ENOENT;
1095 out:
1096 mutex_unlock(&priv->reg_mutex);
1097 return err;
1098 }
1099
1100 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1101 dsa_fdb_dump_cb_t *cb, void *data)
1102 {
1103 struct rtl838x_l2_entry e;
1104 struct rtl838x_switch_priv *priv = ds->priv;
1105 int i;
1106 u32 fid;
1107 u32 pkey;
1108 u64 mac;
1109
1110 mutex_lock(&priv->reg_mutex);
1111
1112 for (i = 0; i < priv->fib_entries; i++) {
1113 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1114
1115 if (!e.valid)
1116 continue;
1117
1118 if (e.port == port) {
1119 fid = (i & 0x3ff) | (e.rvid & ~0x3ff);
1120 mac = ether_addr_to_u64(&e.mac[0]);
1121 pkey = rtl838x_hash(priv, mac << 12 | fid);
1122 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1123 pr_debug("-> mac %016llx, fid: %d\n", mac, fid);
1124 cb(e.mac, e.vid, e.is_static, data);
1125 }
1126 }
1127
1128 for (i = 0; i < 64; i++) {
1129 priv->r->read_cam(i, &e);
1130
1131 if (!e.valid)
1132 continue;
1133
1134 if (e.port == port)
1135 cb(e.mac, e.vid, e.is_static, data);
1136 }
1137
1138 mutex_unlock(&priv->reg_mutex);
1139 return 0;
1140 }
1141
1142 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1143 struct dsa_mall_mirror_tc_entry *mirror,
1144 bool ingress)
1145 {
1146 /* We support 4 mirror groups, one destination port per group */
1147 int group;
1148 struct rtl838x_switch_priv *priv = ds->priv;
1149 int ctrl_reg, dpm_reg, spm_reg;
1150
1151 pr_debug("In %s\n", __func__);
1152
1153 for (group = 0; group < 4; group++) {
1154 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1155 break;
1156 }
1157 if (group >= 4) {
1158 for (group = 0; group < 4; group++) {
1159 if (priv->mirror_group_ports[group] < 0)
1160 break;
1161 }
1162 }
1163
1164 if (group >= 4)
1165 return -ENOSPC;
1166
1167 ctrl_reg = priv->r->mir_ctrl + group * 4;
1168 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1169 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1170
1171 pr_debug("Using group %d\n", group);
1172 mutex_lock(&priv->reg_mutex);
1173
1174 if (priv->family_id == RTL8380_FAMILY_ID) {
1175 /* Enable mirroring to port across VLANs (bit 11) */
1176 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1177 } else {
1178 /* Enable mirroring to destination port */
1179 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1180 }
1181
1182 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1183 mutex_unlock(&priv->reg_mutex);
1184 return -EEXIST;
1185 }
1186 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1187 mutex_unlock(&priv->reg_mutex);
1188 return -EEXIST;
1189 }
1190
1191 if (ingress)
1192 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1193 else
1194 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1195
1196 priv->mirror_group_ports[group] = mirror->to_local_port;
1197 mutex_unlock(&priv->reg_mutex);
1198 return 0;
1199 }
1200
1201 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1202 struct dsa_mall_mirror_tc_entry *mirror)
1203 {
1204 int group = 0;
1205 struct rtl838x_switch_priv *priv = ds->priv;
1206 int ctrl_reg, dpm_reg, spm_reg;
1207
1208 pr_debug("In %s\n", __func__);
1209 for (group = 0; group < 4; group++) {
1210 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1211 break;
1212 }
1213 if (group >= 4)
1214 return;
1215
1216 ctrl_reg = priv->r->mir_ctrl + group * 4;
1217 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1218 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1219
1220 mutex_lock(&priv->reg_mutex);
1221 if (mirror->ingress) {
1222 /* Ingress, clear source port matrix */
1223 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1224 } else {
1225 /* Egress, clear destination port matrix */
1226 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1227 }
1228
1229 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1230 priv->mirror_group_ports[group] = -1;
1231 sw_w32(0, ctrl_reg);
1232 }
1233
1234 mutex_unlock(&priv->reg_mutex);
1235 }
1236
1237 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1238 {
1239 u32 val;
1240 u32 offset = 0;
1241 struct rtl838x_switch_priv *priv = ds->priv;
1242
1243 if (phy_addr >= 24 && phy_addr <= 27
1244 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1245 if (phy_addr == 26)
1246 offset = 0x100;
1247 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1248 return val;
1249 }
1250
1251 read_phy(phy_addr, 0, phy_reg, &val);
1252 return val;
1253 }
1254
1255 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1256 {
1257 u32 offset = 0;
1258 struct rtl838x_switch_priv *priv = ds->priv;
1259
1260 if (phy_addr >= 24 && phy_addr <= 27
1261 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1262 if (phy_addr == 26)
1263 offset = 0x100;
1264 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1265 return 0;
1266 }
1267 return write_phy(phy_addr, 0, phy_reg, val);
1268 }
1269
1270 const struct dsa_switch_ops rtl83xx_switch_ops = {
1271 .get_tag_protocol = rtl83xx_get_tag_protocol,
1272 .setup = rtl83xx_setup,
1273
1274 .phy_read = dsa_phy_read,
1275 .phy_write = dsa_phy_write,
1276
1277 .phylink_validate = rtl83xx_phylink_validate,
1278 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1279 .phylink_mac_config = rtl83xx_phylink_mac_config,
1280 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1281 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1282
1283 .get_strings = rtl83xx_get_strings,
1284 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1285 .get_sset_count = rtl83xx_get_sset_count,
1286
1287 .port_enable = rtl83xx_port_enable,
1288 .port_disable = rtl83xx_port_disable,
1289
1290 .get_mac_eee = rtl83xx_get_mac_eee,
1291 .set_mac_eee = rtl83xx_set_mac_eee,
1292
1293 .set_ageing_time = rtl83xx_set_l2aging,
1294 .port_bridge_join = rtl83xx_port_bridge_join,
1295 .port_bridge_leave = rtl83xx_port_bridge_leave,
1296 .port_stp_state_set = rtl83xx_port_stp_state_set,
1297 .port_fast_age = rtl83xx_fast_age,
1298
1299 .port_vlan_filtering = rtl83xx_vlan_filtering,
1300 .port_vlan_prepare = rtl83xx_vlan_prepare,
1301 .port_vlan_add = rtl83xx_vlan_add,
1302 .port_vlan_del = rtl83xx_vlan_del,
1303
1304 .port_fdb_add = rtl83xx_port_fdb_add,
1305 .port_fdb_del = rtl83xx_port_fdb_del,
1306 .port_fdb_dump = rtl83xx_port_fdb_dump,
1307
1308 .port_mirror_add = rtl83xx_port_mirror_add,
1309 .port_mirror_del = rtl83xx_port_mirror_del,
1310 };
1311
1312 const struct dsa_switch_ops rtl930x_switch_ops = {
1313 .get_tag_protocol = rtl83xx_get_tag_protocol,
1314 .setup = rtl930x_setup,
1315
1316 .phy_read = dsa_phy_read,
1317 .phy_write = dsa_phy_write,
1318
1319 .phylink_validate = rtl83xx_phylink_validate,
1320 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1321 .phylink_mac_config = rtl83xx_phylink_mac_config,
1322 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1323 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1324
1325 .get_strings = rtl83xx_get_strings,
1326 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1327 .get_sset_count = rtl83xx_get_sset_count,
1328
1329 .port_enable = rtl83xx_port_enable,
1330 .port_disable = rtl83xx_port_disable,
1331
1332 .get_mac_eee = rtl93xx_get_mac_eee,
1333 .set_mac_eee = rtl83xx_set_mac_eee,
1334
1335 .set_ageing_time = rtl83xx_set_l2aging,
1336 .port_bridge_join = rtl83xx_port_bridge_join,
1337 .port_bridge_leave = rtl83xx_port_bridge_leave,
1338 .port_stp_state_set = rtl83xx_port_stp_state_set,
1339 .port_fast_age = rtl930x_fast_age,
1340
1341 .port_vlan_filtering = rtl83xx_vlan_filtering,
1342 .port_vlan_prepare = rtl83xx_vlan_prepare,
1343 .port_vlan_add = rtl83xx_vlan_add,
1344 .port_vlan_del = rtl83xx_vlan_del,
1345
1346 .port_fdb_add = rtl83xx_port_fdb_add,
1347 .port_fdb_del = rtl83xx_port_fdb_del,
1348 .port_fdb_dump = rtl83xx_port_fdb_dump,
1349 };
Staging tree of Baptiste Jonglez