target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2023 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include "clk-mtk.h"
  14 #include "clk-gate.h"
  15 #include "clk-mux.h"
  16 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
  17
  18 #define MT7988_PLL_FMAX (2500UL * MHZ)
  19 #define MT7988_PCW_CHG_SHIFT 2
  20
  21 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
  22                  _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
  23                  _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg,           \
  24                  _div_table)                                                  \
  25         {                                                                     \
  26                 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,   \
  27                 .en_mask = _en_mask, .flags = _flags,                         \
  28                 .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX,  \
  29                 .pcwbits = _pcwbits, .pd_reg = _pd_reg,                       \
  30                 .pd_shift = _pd_shift, .tuner_reg = _tuner_reg,               \
  31                 .tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
  32                 .pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift,                 \
  33                 .pcw_chg_reg = _pcw_chg_reg,                                  \
  34                 .pcw_chg_shift = MT7988_PCW_CHG_SHIFT,                        \
  35                 .div_table = _div_table, .parent_name = "clkxtal",            \
  36         }
  37
  38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,      \
  39             _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,          \
  40             _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg)                \
  41         PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
  42                  _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
  43                  _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
  44
  45 static const struct mtk_pll_data plls[] = {
  46         PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
  47             0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
  48         PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
  49             23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
  50         PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
  51             HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
  52         PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
  53             0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
  54         PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
  55             HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
  56         PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
  57             (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
  58             0x0154),
  59         PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
  60             0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
  61         PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
  62             0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
  63         PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
  64             (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
  65             0x0204),
  66         PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
  67             HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
  68         PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
  69             HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
  70         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
  71             32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
  72 };
  73
  74 static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
  75         {
  76                 .compatible = "mediatek,mt7988-apmixedsys",
  77         },
  78         {}
  79 };
  80
  81 static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
  82 {
  83         struct clk_onecell_data *clk_data;
  84         struct device_node *node = pdev->dev.of_node;
  85         int r;
  86
  87         clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
  88         if (!clk_data)
  89                 return -ENOMEM;
  90
  91         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  92
  93         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  94         if (r) {
  95                 pr_err("%s(): could not register clock provider: %d\n",
  96                        __func__, r);
  97                 goto free_apmixed_data;
  98         }
  99         return r;
 100
 101 free_apmixed_data:
 102         mtk_free_clk_data(clk_data);
 103         return r;
 104 }
 105
 106 static struct platform_driver clk_mt7988_apmixed_drv = {
 107         .probe = clk_mt7988_apmixed_probe,
 108         .driver = {
 109                 .name = "clk-mt7988-apmixed",
 110                 .of_match_table = of_match_clk_mt7988_apmixed,
 111         },
 112 };
 113 builtin_platform_driver(clk_mt7988_apmixed_drv);