target/linux/mediatek/files-4.19/drivers/net/phy/mtk/mt753x/mt7531.c

   1 /*
   2  * Driver for MediaTek MT7531 gigabit switch
   3  *
   4  * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
   5  *
   6  * Author: Zhanguo Ju <zhanguo.ju@mediatek.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/hrtimer.h>
  14
  15 #include "mt753x.h"
  16 #include "mt753x_regs.h"
  17
  18 /* MT7531 registers */
  19 #define SGMII_REG_BASE                  0x5000
  20 #define SGMII_REG_PORT_BASE             0x1000
  21 #define SGMII_REG(p, r)                 (SGMII_REG_BASE + \
  22                                         (p) * SGMII_REG_PORT_BASE + (r))
  23 #define PCS_CONTROL_1(p)                SGMII_REG(p, 0x00)
  24 #define SGMII_MODE(p)                   SGMII_REG(p, 0x20)
  25 #define QPHY_PWR_STATE_CTRL(p)          SGMII_REG(p, 0xe8)
  26 #define PHYA_CTRL_SIGNAL3(p)            SGMII_REG(p, 0x128)
  27
  28 /* Fields of PCS_CONTROL_1 */
  29 #define SGMII_LINK_STATUS               BIT(18)
  30 #define SGMII_AN_ENABLE                 BIT(12)
  31 #define SGMII_AN_RESTART                BIT(9)
  32
  33 /* Fields of SGMII_MODE */
  34 #define SGMII_REMOTE_FAULT_DIS          BIT(8)
  35 #define SGMII_IF_MODE_FORCE_DUPLEX      BIT(4)
  36 #define SGMII_IF_MODE_FORCE_SPEED_S     0x2
  37 #define SGMII_IF_MODE_FORCE_SPEED_M     0x0c
  38 #define SGMII_IF_MODE_ADVERT_AN         BIT(1)
  39
  40 /* Values of SGMII_IF_MODE_FORCE_SPEED */
  41 #define SGMII_IF_MODE_FORCE_SPEED_10    0
  42 #define SGMII_IF_MODE_FORCE_SPEED_100   1
  43 #define SGMII_IF_MODE_FORCE_SPEED_1000  2
  44
  45 /* Fields of QPHY_PWR_STATE_CTRL */
  46 #define PHYA_PWD                        BIT(4)
  47
  48 /* Fields of PHYA_CTRL_SIGNAL3 */
  49 #define RG_TPHY_SPEED_S                 2
  50 #define RG_TPHY_SPEED_M                 0x0c
  51
  52 /* Values of RG_TPHY_SPEED */
  53 #define RG_TPHY_SPEED_1000              0
  54 #define RG_TPHY_SPEED_2500              1
  55
  56 /* Unique fields of (M)HWSTRAP for MT7531 */
  57 #define XTAL_FSEL_S                     7
  58 #define XTAL_FSEL_M                     BIT(7)
  59 #define PHY_EN                          BIT(6)
  60 #define CHG_STRAP                       BIT(8)
  61
  62 /* Efuse Register Define */
  63 #define GBE_EFUSE                       0x7bc8
  64 #define GBE_SEL_EFUSE_EN                BIT(0)
  65
  66 /* PHY ENABLE Register bitmap define */
  67 #define PHY_DEV1F                       0x1f
  68 #define PHY_DEV1F_REG_44                0x44
  69 #define PHY_DEV1F_REG_268               0x268
  70 #define PHY_DEV1F_REG_269               0x269
  71 #define PHY_DEV1F_REG_403               0x403
  72
  73 /* Fields of PHY_DEV1F_REG_403 */
  74 #define GBE_EFUSE_SETTING               BIT(3)
  75 #define PHY_EN_BYPASS_MODE              BIT(4)
  76 #define POWER_ON_OFF                    BIT(5)
  77
  78 /* PHY EEE Register bitmap of define */
  79 #define PHY_DEV07                       0x07
  80 #define PHY_DEV07_REG_03C               0x3c
  81
  82 /* PHY Extend Register 0x14 bitmap of define */
  83 #define PHY_EXT_REG_14                  0x14
  84
  85 /* Fields of PHY_EXT_REG_14 */
  86 #define PHY_EN_DOWN_SHFIT               BIT(4)
  87
  88 /* PHY Extend Register 0x17 bitmap of define */
  89 #define PHY_EXT_REG_17                  0x17
  90
  91 /* Fields of PHY_EXT_REG_17 */
  92 #define PHY_LINKDOWN_POWER_SAVING_EN    BIT(4)
  93
  94 /* PHY Token Ring Register 0x10 bitmap of define */
  95 #define PHY_TR_REG_10                   0x10
  96
  97 /* PHY Token Ring Register 0x12 bitmap of define */
  98 #define PHY_TR_REG_12                   0x12
  99
 100 /* PHY DEV 0x1e Register bitmap of define */
 101 #define PHY_DEV1E                       0x1e
 102 #define PHY_DEV1E_REG_13                0x13
 103 #define PHY_DEV1E_REG_14                0x14
 104 #define PHY_DEV1E_REG_41                0x41
 105 #define PHY_DEV1E_REG_A6                0xa6
 106 #define PHY_DEV1E_REG_0C6               0x0c6
 107 #define PHY_DEV1E_REG_0FE               0x0fe
 108 #define PHY_DEV1E_REG_123               0x123
 109 #define PHY_DEV1E_REG_189               0x189
 110
 111 /* Fields of PHY_DEV1E_REG_0C6 */
 112 #define PHY_POWER_SAVING_S              8
 113 #define PHY_POWER_SAVING_M              0x300
 114 #define PHY_POWER_SAVING_TX             0x0
 115
 116 /* Fields of PHY_DEV1E_REG_189 */
 117 #define DESCRAMBLER_CLEAR_EN            0x1
 118
 119 /* Values of XTAL_FSEL_S */
 120 #define XTAL_40MHZ                      0
 121 #define XTAL_25MHZ                      1
 122
 123 #define PLLGP_EN                        0x7820
 124 #define EN_COREPLL                      BIT(2)
 125 #define SW_CLKSW                        BIT(1)
 126 #define SW_PLLGP                        BIT(0)
 127
 128 #define PLLGP_CR0                       0x78a8
 129 #define RG_COREPLL_EN                   BIT(22)
 130 #define RG_COREPLL_POSDIV_S             23
 131 #define RG_COREPLL_POSDIV_M             0x3800000
 132 #define RG_COREPLL_SDM_PCW_S            1
 133 #define RG_COREPLL_SDM_PCW_M            0x3ffffe
 134 #define RG_COREPLL_SDM_PCW_CHG          BIT(0)
 135
 136 /* TOP Signals Status Register */
 137 #define TOP_SIG_SR                      0x780c
 138 #define PAD_DUAL_SGMII_EN               BIT(1)
 139
 140 /* RGMII and SGMII PLL clock */
 141 #define ANA_PLLGP_CR2                   0x78b0
 142 #define ANA_PLLGP_CR5                   0x78bc
 143
 144 /* GPIO mode define */
 145 #define GPIO_MODE_REGS(x)               (0x7c0c + ((x / 8) * 4))
 146 #define GPIO_MODE_S                     4
 147
 148 /* GPIO GROUP IOLB SMT0 Control */
 149 #define SMT0_IOLB                       0x7f04
 150 #define SMT_IOLB_5_SMI_MDC_EN           BIT(5)
 151
 152 /* Unique fields of PMCR for MT7531 */
 153 #define FORCE_MODE_EEE1G                BIT(25)
 154 #define FORCE_MODE_EEE100               BIT(26)
 155 #define FORCE_MODE_TX_FC                BIT(27)
 156 #define FORCE_MODE_RX_FC                BIT(28)
 157 #define FORCE_MODE_DPX                  BIT(29)
 158 #define FORCE_MODE_SPD                  BIT(30)
 159 #define FORCE_MODE_LNK                  BIT(31)
 160 #define FORCE_MODE                      BIT(15)
 161
 162 #define CHIP_REV                        0x781C
 163 #define CHIP_NAME_S                     16
 164 #define CHIP_NAME_M                     0xffff0000
 165 #define CHIP_REV_S                      0
 166 #define CHIP_REV_M                      0x0f
 167 #define CHIP_REV_E1                     0x0
 168
 169 #define CLKGEN_CTRL                     0x7500
 170 #define CLK_SKEW_OUT_S                  8
 171 #define CLK_SKEW_OUT_M                  0x300
 172 #define CLK_SKEW_IN_S                   6
 173 #define CLK_SKEW_IN_M                   0xc0
 174 #define RXCLK_NO_DELAY                  BIT(5)
 175 #define TXCLK_NO_REVERSE                BIT(4)
 176 #define GP_MODE_S                       1
 177 #define GP_MODE_M                       0x06
 178 #define GP_CLK_EN                       BIT(0)
 179
 180 /* Values of GP_MODE */
 181 #define GP_MODE_RGMII                   0
 182 #define GP_MODE_MII                     1
 183 #define GP_MODE_REV_MII                 2
 184
 185 /* Values of CLK_SKEW_IN */
 186 #define CLK_SKEW_IN_NO_CHANGE           0
 187 #define CLK_SKEW_IN_DELAY_100PPS        1
 188 #define CLK_SKEW_IN_DELAY_200PPS        2
 189 #define CLK_SKEW_IN_REVERSE             3
 190
 191 /* Values of CLK_SKEW_OUT */
 192 #define CLK_SKEW_OUT_NO_CHANGE          0
 193 #define CLK_SKEW_OUT_DELAY_100PPS       1
 194 #define CLK_SKEW_OUT_DELAY_200PPS       2
 195 #define CLK_SKEW_OUT_REVERSE            3
 196
 197 /* Proprietory Control Register of Internal Phy device 0x1e */
 198 #define RXADC_CONTROL_3                 0xc2
 199 #define RXADC_LDO_CONTROL_2             0xd3
 200
 201 /* Proprietory Control Register of Internal Phy device 0x1f */
 202 #define TXVLD_DA_271                    0x271
 203 #define TXVLD_DA_272                    0x272
 204 #define TXVLD_DA_273                    0x273
 205
 206 /* DSP Channel and NOD_ADDR*/
 207 #define DSP_CH                          0x2
 208 #define DSP_NOD_ADDR                    0xD
 209
 210 /* gpio pinmux pins and functions define */
 211 static int gpio_int_pins[] = {0};
 212 static int gpio_int_funcs[] = {1};
 213 static int gpio_mdc_pins[] = {11, 20};
 214 static int gpio_mdc_funcs[] = {2, 2};
 215 static int gpio_mdio_pins[] = {12, 21};
 216 static int gpio_mdio_funcs[] = {2, 2};
 217
 218 static int mt7531_set_port_sgmii_force_mode(struct gsw_mt753x *gsw, u32 port,
 219                                             struct mt753x_port_cfg *port_cfg)
 220 {
 221         u32 speed, port_base, val;
 222         ktime_t timeout;
 223         u32 timeout_us;
 224
 225         if (port < 5 || port >= MT753X_NUM_PORTS) {
 226                 dev_info(gsw->dev, "port %d is not a SGMII port\n", port);
 227                 return -EINVAL;
 228         }
 229
 230         port_base = port - 5;
 231
 232         switch (port_cfg->speed) {
 233         case MAC_SPD_1000:
 234                 speed = RG_TPHY_SPEED_1000;
 235                 break;
 236         case MAC_SPD_2500:
 237                 speed = RG_TPHY_SPEED_2500;
 238                 break;
 239         default:
 240                 dev_info(gsw->dev, "invalid SGMII speed idx %d for port %d\n",
 241                          port_cfg->speed, port);
 242
 243                 speed = RG_TPHY_SPEED_1000;
 244         }
 245
 246         /* Step 1: Speed select register setting */
 247         val = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base));
 248         val &= ~RG_TPHY_SPEED_M;
 249         val |= speed << RG_TPHY_SPEED_S;
 250         mt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val);
 251
 252         /* Step 2 : Disable AN */
 253         val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base));
 254         val &= ~SGMII_AN_ENABLE;
 255         mt753x_reg_write(gsw, PCS_CONTROL_1(port_base), val);
 256
 257         /* Step 3: SGMII force mode setting */
 258         val = mt753x_reg_read(gsw, SGMII_MODE(port_base));
 259         val &= ~SGMII_IF_MODE_ADVERT_AN;
 260         val &= ~SGMII_IF_MODE_FORCE_SPEED_M;
 261         val |= SGMII_IF_MODE_FORCE_SPEED_1000 << SGMII_IF_MODE_FORCE_SPEED_S;
 262         val |= SGMII_IF_MODE_FORCE_DUPLEX;
 263         /* For sgmii force mode, 0 is full duplex and 1 is half duplex */
 264         if (port_cfg->duplex)
 265                 val &= ~SGMII_IF_MODE_FORCE_DUPLEX;
 266
 267         mt753x_reg_write(gsw, SGMII_MODE(port_base), val);
 268
 269         /* Step 4: XXX: Disable Link partner's AN and set force mode */
 270
 271         /* Step 5: XXX: Special setting for PHYA ==> reserved for flexible */
 272
 273         /* Step 6 : Release PHYA power down state */
 274         val = mt753x_reg_read(gsw, QPHY_PWR_STATE_CTRL(port_base));
 275         val &= ~PHYA_PWD;
 276         mt753x_reg_write(gsw, QPHY_PWR_STATE_CTRL(port_base), val);
 277
 278         /* Step 7 : Polling SGMII_LINK_STATUS */
 279         timeout_us = 2000000;
 280         timeout = ktime_add_us(ktime_get(), timeout_us);
 281         while (1) {
 282                 val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base));
 283                 val &= SGMII_LINK_STATUS;
 284
 285                 if (val)
 286                         break;
 287
 288                 if (ktime_compare(ktime_get(), timeout) > 0)
 289                         return -ETIMEDOUT;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static int mt7531_set_port_sgmii_an_mode(struct gsw_mt753x *gsw, u32 port,
 296                                          struct mt753x_port_cfg *port_cfg)
 297 {
 298         u32 speed, port_base, val;
 299         ktime_t timeout;
 300         u32 timeout_us;
 301
 302         if (port < 5 || port >= MT753X_NUM_PORTS) {
 303                 dev_info(gsw->dev, "port %d is not a SGMII port\n", port);
 304                 return -EINVAL;
 305         }
 306
 307         port_base = port - 5;
 308
 309         switch (port_cfg->speed) {
 310         case MAC_SPD_1000:
 311                 speed = RG_TPHY_SPEED_1000;
 312                 break;
 313         case MAC_SPD_2500:
 314                 speed = RG_TPHY_SPEED_2500;
 315                 break;
 316         default:
 317                 dev_info(gsw->dev, "invalid SGMII speed idx %d for port %d\n",
 318                          port_cfg->speed, port);
 319
 320                 speed = RG_TPHY_SPEED_1000;
 321         }
 322
 323         /* Step 1: Speed select register setting */
 324         val = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base));
 325         val &= ~RG_TPHY_SPEED_M;
 326         val |= speed << RG_TPHY_SPEED_S;
 327         mt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val);
 328
 329         /* Step 2: Remote fault disable */
 330         val = mt753x_reg_read(gsw, SGMII_MODE(port));
 331         val |= SGMII_REMOTE_FAULT_DIS;
 332         mt753x_reg_write(gsw, SGMII_MODE(port), val);
 333
 334         /* Step 3: Setting Link partner's AN enable = 1 */
 335
 336         /* Step 4: Setting Link partner's device ability for speed/duplex */
 337
 338         /* Step 5: AN re-start */
 339         val = mt753x_reg_read(gsw, PCS_CONTROL_1(port));
 340         val |= SGMII_AN_RESTART;
 341         mt753x_reg_write(gsw, PCS_CONTROL_1(port), val);
 342
 343         /* Step 6: Special setting for PHYA ==> reserved for flexible */
 344
 345         /* Step 7 : Polling SGMII_LINK_STATUS */
 346         timeout_us = 2000000;
 347         timeout = ktime_add_us(ktime_get(), timeout_us);
 348         while (1) {
 349                 val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base));
 350                 val &= SGMII_LINK_STATUS;
 351
 352                 if (val)
 353                         break;
 354
 355                 if (ktime_compare(ktime_get(), timeout) > 0)
 356                         return -ETIMEDOUT;
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int mt7531_set_port_rgmii(struct gsw_mt753x *gsw, u32 port)
 363 {
 364         u32 val;
 365
 366         if (port != 5) {
 367                 dev_info(gsw->dev, "RGMII mode is not available for port %d\n",
 368                          port);
 369                 return -EINVAL;
 370         }
 371
 372         val = mt753x_reg_read(gsw, CLKGEN_CTRL);
 373         val |= GP_CLK_EN;
 374         val &= ~GP_MODE_M;
 375         val |= GP_MODE_RGMII << GP_MODE_S;
 376         val |= TXCLK_NO_REVERSE;
 377         val |= RXCLK_NO_DELAY;
 378         val &= ~CLK_SKEW_IN_M;
 379         val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S;
 380         val &= ~CLK_SKEW_OUT_M;
 381         val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S;
 382         mt753x_reg_write(gsw, CLKGEN_CTRL, val);
 383
 384         return 0;
 385 }
 386
 387 static int mt7531_mac_port_setup(struct gsw_mt753x *gsw, u32 port,
 388                                  struct mt753x_port_cfg *port_cfg)
 389 {
 390         u32 pmcr;
 391         u32 speed;
 392
 393         if (port < 5 || port >= MT753X_NUM_PORTS) {
 394                 dev_info(gsw->dev, "port %d is not a MAC port\n", port);
 395                 return -EINVAL;
 396         }
 397
 398         if (port_cfg->enabled) {
 399                 pmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
 400                        MAC_MODE | MAC_TX_EN | MAC_RX_EN |
 401                        BKOFF_EN | BACKPR_EN;
 402
 403                 if (port_cfg->force_link) {
 404                         /* PMCR's speed field 0x11 is reserved,
 405                          * sw should set 0x10
 406                          */
 407                         speed = port_cfg->speed;
 408                         if (port_cfg->speed == MAC_SPD_2500)
 409                                 speed = MAC_SPD_1000;
 410
 411                         pmcr |= FORCE_MODE_LNK | FORCE_LINK |
 412                                 FORCE_MODE_SPD | FORCE_MODE_DPX |
 413                                 FORCE_MODE_RX_FC | FORCE_MODE_TX_FC |
 414                                 FORCE_RX_FC | FORCE_TX_FC |
 415                                 (speed << FORCE_SPD_S);
 416
 417                         if (port_cfg->duplex)
 418                                 pmcr |= FORCE_DPX;
 419                 }
 420         } else {
 421                 pmcr = FORCE_MODE_LNK;
 422         }
 423
 424         switch (port_cfg->phy_mode) {
 425         case PHY_INTERFACE_MODE_RGMII:
 426                 mt7531_set_port_rgmii(gsw, port);
 427                 break;
 428         case PHY_INTERFACE_MODE_SGMII:
 429                 if (port_cfg->force_link)
 430                         mt7531_set_port_sgmii_force_mode(gsw, port, port_cfg);
 431                 else
 432                         mt7531_set_port_sgmii_an_mode(gsw, port, port_cfg);
 433                 break;
 434         default:
 435                 if (port_cfg->enabled)
 436                         dev_info(gsw->dev, "%s is not supported by port %d\n",
 437                                  phy_modes(port_cfg->phy_mode), port);
 438
 439                 pmcr = FORCE_MODE_LNK;
 440         }
 441
 442         mt753x_reg_write(gsw, PMCR(port), pmcr);
 443
 444         return 0;
 445 }
 446
 447 static void mt7531_core_pll_setup(struct gsw_mt753x *gsw)
 448 {
 449         u32 hwstrap;
 450         u32 val;
 451
 452         val = mt753x_reg_read(gsw, TOP_SIG_SR);
 453         if (val & PAD_DUAL_SGMII_EN)
 454                 return;
 455
 456         hwstrap = mt753x_reg_read(gsw, HWSTRAP);
 457
 458         switch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) {
 459         case XTAL_25MHZ:
 460                 /* Step 1 : Disable MT7531 COREPLL */
 461                 val = mt753x_reg_read(gsw, PLLGP_EN);
 462                 val &= ~EN_COREPLL;
 463                 mt753x_reg_write(gsw, PLLGP_EN, val);
 464
 465                 /* Step 2: switch to XTAL output */
 466                 val = mt753x_reg_read(gsw, PLLGP_EN);
 467                 val |= SW_CLKSW;
 468                 mt753x_reg_write(gsw, PLLGP_EN, val);
 469
 470                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 471                 val &= ~RG_COREPLL_EN;
 472                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 473
 474                 /* Step 3: disable PLLGP and enable program PLLGP */
 475                 val = mt753x_reg_read(gsw, PLLGP_EN);
 476                 val |= SW_PLLGP;
 477                 mt753x_reg_write(gsw, PLLGP_EN, val);
 478
 479                 /* Step 4: program COREPLL output frequency to 500MHz */
 480                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 481                 val &= ~RG_COREPLL_POSDIV_M;
 482                 val |= 2 << RG_COREPLL_POSDIV_S;
 483                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 484                 usleep_range(25, 35);
 485
 486                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 487                 val &= ~RG_COREPLL_SDM_PCW_M;
 488                 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
 489                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 490
 491                 /* Set feedback divide ratio update signal to high */
 492                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 493                 val |= RG_COREPLL_SDM_PCW_CHG;
 494                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 495                 /* Wait for at least 16 XTAL clocks */
 496                 usleep_range(10, 20);
 497
 498                 /* Step 5: set feedback divide ratio update signal to low */
 499                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 500                 val &= ~RG_COREPLL_SDM_PCW_CHG;
 501                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 502
 503                 /* Enable 325M clock for SGMII */
 504                 mt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000);
 505
 506                 /* Enable 250SSC clock for RGMII */
 507                 mt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000);
 508
 509                 /* Step 6: Enable MT7531 PLL */
 510                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 511                 val |= RG_COREPLL_EN;
 512                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 513
 514                 val = mt753x_reg_read(gsw, PLLGP_EN);
 515                 val |= EN_COREPLL;
 516                 mt753x_reg_write(gsw, PLLGP_EN, val);
 517                 usleep_range(25, 35);
 518
 519                 break;
 520         case XTAL_40MHZ:
 521                 /* Step 1 : Disable MT7531 COREPLL */
 522                 val = mt753x_reg_read(gsw, PLLGP_EN);
 523                 val &= ~EN_COREPLL;
 524                 mt753x_reg_write(gsw, PLLGP_EN, val);
 525
 526                 /* Step 2: switch to XTAL output */
 527                 val = mt753x_reg_read(gsw, PLLGP_EN);
 528                 val |= SW_CLKSW;
 529                 mt753x_reg_write(gsw, PLLGP_EN, val);
 530
 531                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 532                 val &= ~RG_COREPLL_EN;
 533                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 534
 535                 /* Step 3: disable PLLGP and enable program PLLGP */
 536                 val = mt753x_reg_read(gsw, PLLGP_EN);
 537                 val |= SW_PLLGP;
 538                 mt753x_reg_write(gsw, PLLGP_EN, val);
 539
 540                 /* Step 4: program COREPLL output frequency to 500MHz */
 541                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 542                 val &= ~RG_COREPLL_POSDIV_M;
 543                 val |= 2 << RG_COREPLL_POSDIV_S;
 544                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 545                 usleep_range(25, 35);
 546
 547                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 548                 val &= ~RG_COREPLL_SDM_PCW_M;
 549                 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
 550                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 551
 552                 /* Set feedback divide ratio update signal to high */
 553                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 554                 val |= RG_COREPLL_SDM_PCW_CHG;
 555                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 556                 /* Wait for at least 16 XTAL clocks */
 557                 usleep_range(10, 20);
 558
 559                 /* Step 5: set feedback divide ratio update signal to low */
 560                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 561                 val &= ~RG_COREPLL_SDM_PCW_CHG;
 562                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 563
 564                 /* Enable 325M clock for SGMII */
 565                 mt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000);
 566
 567                 /* Enable 250SSC clock for RGMII */
 568                 mt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000);
 569
 570                 /* Step 6: Enable MT7531 PLL */
 571                 val = mt753x_reg_read(gsw, PLLGP_CR0);
 572                 val |= RG_COREPLL_EN;
 573                 mt753x_reg_write(gsw, PLLGP_CR0, val);
 574
 575                 val = mt753x_reg_read(gsw, PLLGP_EN);
 576                 val |= EN_COREPLL;
 577                 mt753x_reg_write(gsw, PLLGP_EN, val);
 578                 usleep_range(25, 35);
 579                 break;
 580         }
 581 }
 582
 583 static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw)
 584 {
 585         return 0;
 586 }
 587
 588 static int mt7531_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev)
 589 {
 590         u32 rev, topsig;
 591
 592         rev = mt753x_reg_read(gsw, CHIP_REV);
 593
 594         if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7531) {
 595                 if (crev) {
 596                         topsig = mt753x_reg_read(gsw, TOP_SIG_SR);
 597
 598                         crev->rev = rev & CHIP_REV_M;
 599                         crev->name = topsig & PAD_DUAL_SGMII_EN ?
 600                                      "MT7531AE" : "MT7531BE";
 601                 }
 602
 603                 return 0;
 604         }
 605
 606         return -ENODEV;
 607 }
 608
 609 static void pinmux_set_mux_7531(struct gsw_mt753x *gsw, u32 pin, u32 mode)
 610 {
 611         u32 val;
 612
 613         val = mt753x_reg_read(gsw, GPIO_MODE_REGS(pin));
 614         val &= ~(0xf << (pin & 7) * GPIO_MODE_S);
 615         val |= mode << (pin & 7) * GPIO_MODE_S;
 616         mt753x_reg_write(gsw, GPIO_MODE_REGS(pin), val);
 617 }
 618
 619 static int mt7531_set_gpio_pinmux(struct gsw_mt753x *gsw)
 620 {
 621         u32 group = 0;
 622         struct device_node *np = gsw->dev->of_node;
 623
 624         /* Set GPIO 0 interrupt mode */
 625         pinmux_set_mux_7531(gsw, gpio_int_pins[0], gpio_int_funcs[0]);
 626
 627         of_property_read_u32(np, "mediatek,mdio_master_pinmux", &group);
 628
 629         /* group = 0: do nothing, 1: 1st group (AE), 2: 2nd group (BE) */
 630         if (group > 0 && group <= 2) {
 631                 group--;
 632                 pinmux_set_mux_7531(gsw, gpio_mdc_pins[group],
 633                                     gpio_mdc_funcs[group]);
 634                 pinmux_set_mux_7531(gsw, gpio_mdio_pins[group],
 635                                     gpio_mdio_funcs[group]);
 636         }
 637
 638         return 0;
 639 }
 640
 641 static void mt7531_phy_setting(struct gsw_mt753x *gsw)
 642 {
 643         int i;
 644         u32 val;
 645
 646         /* Adjust DAC TX Delay */
 647         gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_44, 0xc0);
 648
 649         for (i = 0; i < MT753X_NUM_PHYS; i++) {
 650                 /* Disable EEE */
 651                 gsw->mmd_write(gsw, i, PHY_DEV07, PHY_DEV07_REG_03C, 0);
 652
 653                 /* Enable HW auto downshift */
 654                 gsw->mii_write(gsw, i, 0x1f, 0x1);
 655                 val = gsw->mii_read(gsw, i, PHY_EXT_REG_14);
 656                 val |= PHY_EN_DOWN_SHFIT;
 657                 gsw->mii_write(gsw, i, PHY_EXT_REG_14, val);
 658
 659                 /* Increase SlvDPSready time */
 660                 gsw->mii_write(gsw, i, 0x1f, 0x52b5);
 661                 gsw->mii_write(gsw, i, PHY_TR_REG_10, 0xafae);
 662                 gsw->mii_write(gsw, i, PHY_TR_REG_12, 0x2f);
 663                 gsw->mii_write(gsw, i, PHY_TR_REG_10, 0x8fae);
 664                 gsw->mii_write(gsw, i, 0x1f, 0);
 665
 666                 /* Adjust 100_mse_threshold */
 667                 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff);
 668
 669                 /* Disable mcc */
 670                 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300);
 671
 672                 /* PHY link down power saving enable */
 673                 val = gsw->mii_read(gsw, i, PHY_EXT_REG_17);
 674                 val |= PHY_LINKDOWN_POWER_SAVING_EN;
 675                 gsw->mii_write(gsw, i, PHY_EXT_REG_17, val);
 676
 677                 val = gsw->mmd_read(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6);
 678                 val &= ~PHY_POWER_SAVING_M;
 679                 val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
 680                 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6, val);
 681
 682                 /* Set TX Pair delay selection */
 683                 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_13, 0x404);
 684                 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_14, 0x404);
 685         }
 686 }
 687
 688 static void mt7531_adjust_line_driving(struct gsw_mt753x *gsw, u32 port)
 689 {
 690         /* For ADC timing margin window for LDO calibration */
 691         gsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_LDO_CONTROL_2, 0x2222);
 692
 693         /* Adjust AD sample timing */
 694         gsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_CONTROL_3, 0x4444);
 695
 696         /* Adjust Line driver current for different mode */
 697         gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_271, 0x2c63);
 698
 699         /* Adjust Line driver current for different mode */
 700         gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_272, 0xc6b);
 701
 702         /* Adjust Line driver amplitude for 10BT */
 703         gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_273, 0x3000);
 704
 705         /* Adjust RX Echo path filter */
 706         gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2);
 707
 708         /* Adjust RX HVGA bias current */
 709         gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_41, 0x3333);
 710
 711         /* Adjust TX class AB driver 1 */
 712         gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_268, 0x3aa);
 713
 714         /* Adjust TX class AB driver 2 */
 715         gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_269, 0xaaaa);
 716 }
 717
 718 static void mt7531_eee_setting(struct gsw_mt753x *gsw, u32 port)
 719 {
 720         u32 tr_reg_control;
 721         u32 val;
 722
 723         /* Disable generate signal to clear the scramble_lock when lpi mode */
 724         val = gsw->mmd_read(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189);
 725         val &= ~DESCRAMBLER_CLEAR_EN;
 726         gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189, val);
 727
 728         /* roll back CR*/
 729         gsw->mii_write(gsw, port, 0x1f, 0x52b5);
 730         gsw->mmd_write(gsw, port, 0x1e, 0x2d1, 0);
 731         tr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) |
 732                          (DSP_NOD_ADDR << 7) | (0x8 << 1);
 733         gsw->mii_write(gsw, port, 17, 0x1b);
 734         gsw->mii_write(gsw, port, 18, 0);
 735         gsw->mii_write(gsw, port, 16, tr_reg_control);
 736         tr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) |
 737                          (DSP_NOD_ADDR << 7) | (0xf << 1);
 738         gsw->mii_write(gsw, port, 17, 0);
 739         gsw->mii_write(gsw, port, 18, 0);
 740         gsw->mii_write(gsw, port, 16, tr_reg_control);
 741
 742         tr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) |
 743                          (DSP_NOD_ADDR << 7) | (0x10 << 1);
 744         gsw->mii_write(gsw, port, 17, 0x500);
 745         gsw->mii_write(gsw, port, 18, 0);
 746         gsw->mii_write(gsw, port, 16, tr_reg_control);
 747         gsw->mii_write(gsw, port, 0x1f, 0);
 748 }
 749
 750 static int mt7531_sw_init(struct gsw_mt753x *gsw)
 751 {
 752         int i;
 753         u32 val;
 754
 755         gsw->phy_base = (gsw->smi_addr + 1) & MT753X_SMI_ADDR_MASK;
 756
 757         gsw->mii_read = mt753x_mii_read;
 758         gsw->mii_write = mt753x_mii_write;
 759         gsw->mmd_read = mt753x_mmd_read;
 760         gsw->mmd_write = mt753x_mmd_write;
 761
 762         for (i = 0; i < MT753X_NUM_PHYS; i++) {
 763                 val = gsw->mii_read(gsw, i, MII_BMCR);
 764                 val |= BMCR_ISOLATE;
 765                 gsw->mii_write(gsw, i, MII_BMCR, val);
 766         }
 767
 768         /* Force MAC link down before reset */
 769         mt753x_reg_write(gsw, PMCR(5), FORCE_MODE_LNK);
 770         mt753x_reg_write(gsw, PMCR(6), FORCE_MODE_LNK);
 771
 772         /* Switch soft reset */
 773         mt753x_reg_write(gsw, SYS_CTRL, SW_SYS_RST | SW_REG_RST);
 774         usleep_range(10, 20);
 775
 776         /* Enable MDC input Schmitt Trigger */
 777         val = mt753x_reg_read(gsw, SMT0_IOLB);
 778         mt753x_reg_write(gsw, SMT0_IOLB, val | SMT_IOLB_5_SMI_MDC_EN);
 779
 780         /* Set 7531 gpio pinmux */
 781         mt7531_set_gpio_pinmux(gsw);
 782
 783         /* Global mac control settings */
 784         mt753x_reg_write(gsw, GMACCR,
 785                          (15 << MTCC_LMT_S) | (11 << MAX_RX_JUMBO_S) |
 786                          RX_PKT_LEN_MAX_JUMBO);
 787
 788         mt7531_core_pll_setup(gsw);
 789         mt7531_mac_port_setup(gsw, 5, &gsw->port5_cfg);
 790         mt7531_mac_port_setup(gsw, 6, &gsw->port6_cfg);
 791
 792         return 0;
 793 }
 794
 795 static int mt7531_sw_post_init(struct gsw_mt753x *gsw)
 796 {
 797         int i;
 798         u32 val;
 799
 800         /* Internal PHYs are disabled by default. SW should enable them.
 801          * Note that this may already be enabled in bootloader stage.
 802          */
 803         val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);
 804         val |= PHY_EN_BYPASS_MODE;
 805         val &= ~POWER_ON_OFF;
 806         gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);
 807
 808         mt7531_phy_setting(gsw);
 809
 810         for (i = 0; i < MT753X_NUM_PHYS; i++) {
 811                 val = gsw->mii_read(gsw, i, MII_BMCR);
 812                 val &= ~BMCR_ISOLATE;
 813                 gsw->mii_write(gsw, i, MII_BMCR, val);
 814         }
 815
 816         for (i = 0; i < MT753X_NUM_PHYS; i++)
 817                 mt7531_adjust_line_driving(gsw, i);
 818
 819         for (i = 0; i < MT753X_NUM_PHYS; i++)
 820                 mt7531_eee_setting(gsw, i);
 821
 822         val = mt753x_reg_read(gsw, CHIP_REV);
 823         val &= CHIP_REV_M;
 824         if (val == CHIP_REV_E1) {
 825                 mt7531_internal_phy_calibration(gsw);
 826         } else {
 827                 val = mt753x_reg_read(gsw, GBE_EFUSE);
 828                 if (val & GBE_SEL_EFUSE_EN) {
 829                         val = gsw->mmd_read(gsw, 0, PHY_DEV1F,
 830                                             PHY_DEV1F_REG_403);
 831                         val &= ~GBE_EFUSE_SETTING;
 832                         gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403,
 833                                        val);
 834                 } else {
 835                         mt7531_internal_phy_calibration(gsw);
 836                 }
 837         }
 838
 839         return 0;
 840 }
 841
 842 struct mt753x_sw_id mt7531_id = {
 843         .model = MT7531,
 844         .detect = mt7531_sw_detect,
 845         .init = mt7531_sw_init,
 846         .post_init = mt7531_sw_post_init
 847 };
 848
 849 MODULE_LICENSE("GPL");
 850 MODULE_AUTHOR("Zhanguo Ju <zhanguo.ju@mediatek.com>");
 851 MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch");