target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include "qcom-ipq8065-smb208.dtsi"
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         model = "Arris TR4400 v2";
   8         compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
   9
  10         memory@0 {
  11                 reg = <0x42000000 0x1e000000>;
  12                 device_type = "memory";
  13         };
  14
  15         aliases {
  16                 led-boot = &led_status_blue;
  17                 led-failsafe = &led_status_red;
  18                 led-running = &led_status_blue;
  19                 led-upgrade = &led_status_red;
  20         };
  21
  22         chosen {
  23                 bootargs = "rootfstype=squashfs noinitrd";
  24         };
  25
  26         keys {
  27                 compatible = "gpio-keys";
  28                 pinctrl-0 = <&button_pins>;
  29                 pinctrl-names = "default";
  30
  31                 reset {
  32                         label = "reset";
  33                         gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_RESTART>;
  35                         debounce-interval = <60>;
  36                         wakeup-source;
  37                 };
  38
  39                 wps {
  40                         label = "wps";
  41                         gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  42                         linux,code = <KEY_WPS_BUTTON>;
  43                         debounce-interval = <60>;
  44                         wakeup-source;
  45                 };
  46         };
  47
  48         leds {
  49                 compatible = "gpio-leds";
  50                 pinctrl-0 = <&led_pins>;
  51                 pinctrl-names = "default";
  52
  53                 led_status_red: status_red {
  54                         label = "red:status";
  55                         gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  56                 };
  57
  58                 led_status_blue: status_blue {
  59                         label = "blue:status";
  60                         gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  61                 };
  62         };
  63 };
  64
  65 &qcom_pinmux {
  66         button_pins: button_pins {
  67                 mux {
  68                         pins = "gpio6", "gpio54";
  69                         function = "gpio";
  70                         drive-strength = <2>;
  71                         bias-pull-up;
  72                 };
  73         };
  74
  75         led_pins: led_pins {
  76                 mux {
  77                         pins = "gpio7", "gpio8";
  78                         function = "gpio";
  79                         drive-strength = <2>;
  80                         bias-pull-down;
  81                 };
  82         };
  83
  84         rgmii2_pins: rgmii2-pins {
  85                 tx {
  86                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  87                         input-disable;
  88                 };
  89         };
  90
  91         spi_pins: spi_pins {
  92                 cs {
  93                         pins = "gpio20";
  94                         drive-strength = <12>;
  95                 };
  96         };
  97 };
  98
  99 &gsbi5 {
 100         qcom,mode = <GSBI_PROT_SPI>;
 101         status = "okay";
 102
 103         spi@1a280000 {
 104                 status = "okay";
 105
 106                 pinctrl-0 = <&spi_pins>;
 107                 pinctrl-names = "default";
 108
 109                 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 110
 111                 flash@0 {
 112                         compatible = "everspin,mr25h256";
 113                         spi-max-frequency = <40000000>;
 114                         reg = <0>;
 115                 };
 116         };
 117 };
 118
 119 &nand {
 120         status = "okay";
 121
 122         nand@0 {
 123                 reg = <0>;
 124                 compatible = "qcom,nandcs";
 125
 126                 nand-ecc-strength = <4>;
 127                 nand-bus-width = <8>;
 128                 nand-ecc-step-size = <512>;
 129
 130                 qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
 131
 132                 partitions {
 133                         compatible = "fixed-partitions";
 134                         #address-cells = <1>;
 135                         #size-cells = <1>;
 136
 137                         partition@0 {
 138                                 label = "0:SBL1";
 139                                 reg = <0x0000000 0x0040000>;
 140                                 read-only;
 141                         };
 142                         partition@40000 {
 143                                 label = "0:MIBIB";
 144                                 reg = <0x0040000 0x0140000>;
 145                                 read-only;
 146                         };
 147                         partition@180000 {
 148                                 label = "0:SBL2";
 149                                 reg = <0x0180000 0x0140000>;
 150                                 read-only;
 151                         };
 152                         partition@2c0000 {
 153                                 label = "0:SBL3";
 154                                 reg = <0x02c0000 0x0280000>;
 155                                 read-only;
 156                         };
 157                         partition@540000 {
 158                                 label = "0:DDRCONFIG";
 159                                 reg = <0x0540000 0x0120000>;
 160                                 read-only;
 161                         };
 162                         partition@660000 {
 163                                 label = "0:SSD";
 164                                 reg = <0x0660000 0x0120000>;
 165                                 read-only;
 166                         };
 167                         partition@780000 {
 168                                 label = "0:TZ";
 169                                 reg = <0x0780000 0x0280000>;
 170                                 read-only;
 171                         };
 172                         partition@a00000 {
 173                                 label = "0:RPM";
 174                                 reg = <0x0a00000 0x0280000>;
 175                                 read-only;
 176                         };
 177                         partition@c80000 {
 178                                 label = "0:APPSBL";
 179                                 reg = <0x0c80000 0x0500000>;
 180                                 read-only;
 181                         };
 182                         partition@1180000 {
 183                                 label = "0:APPSBLENV";
 184                                 reg = <0x1180000 0x0080000>;
 185                         };
 186                         partition@1200000 {
 187                                 label = "0:ART";
 188                                 reg = <0x1200000 0x0140000>;
 189                                 read-only;
 190
 191                                 compatible = "nvmem-cells";
 192                                 #address-cells = <1>;
 193                                 #size-cells = <1>;
 194
 195                                 precal_ART_1000: precal@1000 {
 196                                         reg = <0x1000 0x2f20>;
 197                                 };
 198                                 precal_ART_5000: precal@5000 {
 199                                         reg = <0x5000 0x2f20>;
 200                                 };
 201                         };
 202                         stock_partition@1340000 {
 203                                 label = "stock_rootfs";
 204                                 reg = <0x1340000 0x4000000>;
 205                         };
 206                         partition@5340000 {
 207                                 label = "0:BOOTCONFIG";
 208                                 reg = <0x5340000 0x0060000>;
 209                                 read-only;
 210                         };
 211                         partition@53a0000 {
 212                                 label = "0:SBL2_1";
 213                                 reg = <0x53a0000 0x0140000>;
 214                                 read-only;
 215                         };
 216                         partition@54e0000 {
 217                                 label = "0:SBL3_1";
 218                                 reg = <0x54e0000 0x0280000>;
 219                                 read-only;
 220                         };
 221                         partition@5760000 {
 222                                 label = "0:DDRCONFIG_1";
 223                                 reg = <0x5760000 0x0120000>;
 224                                 read-only;
 225                         };
 226                         partition@5880000 {
 227                                 label = "0:SSD_1";
 228                                 reg = <0x5880000 0x0120000>;
 229                                 read-only;
 230                         };
 231                         partition@59a0000 {
 232                                 label = "0:TZ_1";
 233                                 reg = <0x59a0000 0x0280000>;
 234                                 read-only;
 235                         };
 236                         partition@5c20000 {
 237                                 label = "0:RPM_1";
 238                                 reg = <0x5c20000 0x0280000>;
 239                                 read-only;
 240                         };
 241                         partition@5ea0000 {
 242                                 label = "0:BOOTCONFIG1";
 243                                 reg = <0x5ea0000 0x0060000>;
 244                                 read-only;
 245                         };
 246                         partition@5f00000 {
 247                                 label = "0:APPSBL_1";
 248                                 reg = <0x5f00000 0x0500000>;
 249                                 read-only;
 250                         };
 251                         stock_partition@6400000 {
 252                                 label = "stock_rootfs_1";
 253                                 reg = <0x6400000 0x4000000>;
 254                         };
 255                         stock_partition@a400000 {
 256                                 label = "stock_fw_env";
 257                                 reg = <0xa400000 0x0100000>;
 258                         };
 259                         stock_partition@a500000 {
 260                                 label = "stock_config";
 261                                 reg = <0xa500000 0x0800000>;
 262                         };
 263                         stock_partition@ad00000 {
 264                                 label = "stock_PKI";
 265                                 reg = <0xad00000 0x0200000>;
 266                         };
 267                         stock_partition@af00000 {
 268                                 label = "stock_scfgmgr";
 269                                 reg = <0xaf00000 0x0100000>;
 270                         };
 271
 272                         partition@6400000 {
 273                                 label = "fw_env";
 274                                 reg = <0x6400000 0x0100000>;
 275
 276                                 compatible = "nvmem-cells";
 277                                 #address-cells = <1>;
 278                                 #size-cells = <1>;
 279
 280                                 macaddr_fw_env_0: macaddr@0 {
 281                                         reg = <0x00 0x6>;
 282                                 };
 283                                 macaddr_fw_env_6: macaddr@6 {
 284                                         reg = <0x06 0x6>;
 285                                 };
 286                                 macaddr_fw_env_c: macaddr@c {
 287                                         reg = <0x0c 0x6>;
 288                                 };
 289                                 macaddr_fw_env_12: macaddr@12 {
 290                                         reg = <0x12 0x6>;
 291                                 };
 292                                 macaddr_fw_env_18: macaddr@18 {
 293                                         reg = <0x18 0x6>;
 294                                 };
 295                         };
 296                         partition@6500000 {
 297                                 label = "ubi";
 298                                 reg = <0x6500000 0x9b00000>;
 299                         };
 300                         partition@1340000 {
 301                                 label = "extra";
 302                                 reg = <0x1340000 0x4000000>;
 303                         };
 304                 };
 305         };
 306 };
 307
 308 &mdio0 {
 309         status = "okay";
 310
 311         pinctrl-0 = <&mdio0_pins>;
 312         pinctrl-names = "default";
 313
 314         switch@10 {
 315                 compatible = "qca,qca8337";
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 reg = <0x10>;
 319
 320                 ports {
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323
 324                         port@0 {
 325                                 reg = <0>;
 326                                 label = "cpu";
 327                                 ethernet = <&gmac0>;
 328                                 phy-mode = "rgmii";
 329                                 tx-internal-delay-ps = <1000>;
 330                                 rx-internal-delay-ps = <1000>;
 331
 332                                 fixed-link {
 333                                         speed = <1000>;
 334                                         full-duplex;
 335                                 };
 336                         };
 337
 338                         port@1 {
 339                                 reg = <1>;
 340                                 label = "lan1";
 341                                 phy-mode = "internal";
 342                                 phy-handle = <&phy_port1>;
 343                         };
 344
 345                         port@2 {
 346                                 reg = <2>;
 347                                 label = "lan2";
 348                                 phy-mode = "internal";
 349                                 phy-handle = <&phy_port2>;
 350                         };
 351
 352                         port@3 {
 353                                 reg = <3>;
 354                                 label = "lan3";
 355                                 phy-mode = "internal";
 356                                 phy-handle = <&phy_port3>;
 357                         };
 358
 359                         port@4 {
 360                                 reg = <4>;
 361                                 label = "lan4";
 362                                 phy-mode = "internal";
 363                                 phy-handle = <&phy_port4>;
 364                         };
 365
 366                         /*
 367                         port@6 {
 368                                 reg = <0>;
 369                                 label = "cpu";
 370                                 ethernet = <&gmac1>;
 371                                 phy-mode = "rgmii";
 372
 373                                 fixed-link {
 374                                         speed = <1000>;
 375                                         full-duplex;
 376                                         pause;
 377                                         asym-pause;
 378                                 };
 379                         };
 380                         */
 381                 };
 382
 383                 mdio {
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386
 387                         phy_port1: phy@0 {
 388                                 reg = <0>;
 389                         };
 390
 391                         phy_port2: phy@1 {
 392                                 reg = <1>;
 393                         };
 394
 395                         phy_port3: phy@2 {
 396                                 reg = <2>;
 397                         };
 398
 399                         phy_port4: phy@3 {
 400                                 reg = <3>;
 401                         };
 402                 };
 403         };
 404
 405         phy7: ethernet-phy@7 {
 406                 reg = <7>;
 407         };
 408 };
 409
 410 &gmac0 {
 411         status = "okay";
 412         phy-mode = "rgmii";
 413         qcom,id = <0>;
 414
 415         nvmem-cells = <&macaddr_fw_env_18>;
 416         nvmem-cell-names = "mac-address";
 417
 418         pinctrl-0 = <&rgmii2_pins>;
 419         pinctrl-names = "default";
 420
 421         fixed-link {
 422                 speed = <1000>;
 423                 full-duplex;
 424         };
 425 };
 426
 427 &gmac1 {
 428         status = "okay";
 429         phy-mode = "sgmii";
 430         qcom,id = <1>;
 431
 432         nvmem-cells = <&macaddr_fw_env_0>;
 433         nvmem-cell-names = "mac-address";
 434
 435         fixed-link {
 436                 speed = <1000>;
 437                 full-duplex;
 438         };
 439 };
 440
 441 &gmac3 {
 442         status = "okay";
 443         phy-mode = "sgmii";
 444         qcom,id = <3>;
 445         phy-handle = <&phy7>;
 446
 447         nvmem-cells = <&macaddr_fw_env_6>;
 448         nvmem-cell-names = "mac-address";
 449 };
 450
 451 &adm_dma {
 452         status = "okay";
 453 };
 454
 455 &hs_phy_1 {
 456         status = "okay";
 457 };
 458
 459 &ss_phy_1 {
 460         status = "okay";
 461 };
 462
 463 &usb3_1 {
 464         status = "okay";
 465 };
 466
 467 &pcie0 {
 468         status = "okay";
 469         reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 470         pinctrl-0 = <&pcie0_pins>;
 471         pinctrl-names = "default";
 472
 473         bridge@0,0 {
 474                 reg = <0x00000000 0 0 0 0>;
 475                 #address-cells = <3>;
 476                 #size-cells = <2>;
 477                 ranges;
 478
 479                 wifi0: wifi@1,0 {
 480                         compatible = "pci168c,0046";
 481                         reg = <0x00010000 0 0 0 0>;
 482
 483                         nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
 484                         nvmem-cell-names = "pre-calibration", "mac-address";
 485                 };
 486         };
 487 };
 488
 489 &pcie1 {
 490         status = "okay";
 491         reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
 492         pinctrl-0 = <&pcie1_pins>;
 493         pinctrl-names = "default";
 494         max-link-speed = <1>;
 495
 496         bridge@0,0 {
 497                 reg = <0x00000000 0 0 0 0>;
 498                 #address-cells = <3>;
 499                 #size-cells = <2>;
 500                 ranges;
 501
 502                 wifi1: wifi@1,0 {
 503                         compatible = "pci168c,0040";
 504                         reg = <0x00010000 0 0 0 0>;
 505
 506                         nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
 507                         nvmem-cell-names = "pre-calibration", "mac-address";
 508                 };
 509         };
 510 };