target/linux/bcm27xx/patches-6.1/950-1055-arm-dt-add-dtparams-for-PCIe-reset-timing-override.patch

   1 From db90a5e5fc2fbd843b29eb8110ed5e03604a2887 Mon Sep 17 00:00:00 2001
   2 From: Jonathan Bell <jonathan@raspberrypi.com>
   3 Date: Wed, 20 Sep 2023 13:04:54 +0100
   4 Subject: [PATCH] arm: dt: add dtparams for PCIe reset timing override
   5
   6 The Pi 5 variant gets two parameters so that the CM4-compatible
   7 name will also work on Pi 5.
   8
   9 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  10 ---
  11  arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 2 ++
  12  arch/arm/boot/dts/bcm2712-rpi-5-b.dts | 2 ++
  13  arch/arm/boot/dts/overlays/README     | 7 +++++++
  14  3 files changed, 11 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts
  17 +++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts
  18 @@ -446,5 +446,7 @@ i2c_csi_dsi0: &i2c0 {
  19                 cam1_reg = <&cam1_reg>,"status";
  20                 cam1_reg_gpio = <&cam1_reg>,"gpio:4",
  21                                   <&cam1_reg>,"gpio:0=", <&gpio>;
  22 +
  23 +               pcie_tperst_clk_ms = <&pcie0>,"brcm,tperst-clk-ms:0";
  24         };
  25  };
  26 --- a/arch/arm/boot/dts/bcm2712-rpi-5-b.dts
  27 +++ b/arch/arm/boot/dts/bcm2712-rpi-5-b.dts
  28 @@ -814,6 +814,8 @@ spi10_cs_pins: &spi10_cs_gpio1 {};
  29                 pciex1 = <&pciex1>, "status";
  30                 pciex1_gen = <&pciex1> , "max-link-speed:0";
  31                 pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?";
  32 +               pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0";
  33 +               pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0";
  34                 random = <&random>, "status";
  35                 rtc_bbat_vchg = <&rpi_rtc>, "trickle-charge-microvolt:0";
  36                 spi = <&spi0>, "status";
  37 --- a/arch/arm/boot/dts/overlays/README
  38 +++ b/arch/arm/boot/dts/overlays/README
  39 @@ -280,6 +280,10 @@ Params:
  40                                  (2711 only, but not applicable on CM4S)
  41                                  N.B. USB-A ports on 4B are subsequently disabled
  42
  43 +        pcie_tperst_clk_ms      Add N milliseconds between PCIe reference clock
  44 +                                activation and PERST# deassertion
  45 +                                (CM4 and 2712, default "0")
  46 +
  47          pciex1                  Set to "on" to enable the external PCIe link
  48                                  (2712 only, default "off")
  49
  50 @@ -290,6 +294,9 @@ Params:
  51                                  PCIe link for devices that have broken
  52                                  implementations (2712 only, default "off")
  53
  54 +        pciex1_tperst_clk_ms    Alias for pcie_tperst_clk_ms
  55 +                                (2712 only, default "0")
  56 +
  57          spi                     Set to "on" to enable the spi interfaces
  58                                  (default "off")
  59