plat/bcm/include/pmc_addr_4908.h

   1 /*
   2 <:copyright-BRCM:2019:DUAL/GPL:standard
   3
   4    Copyright (c) 2019 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef PMC_ADDR_4908_H__
  25 #define PMC_ADDR_4908_H__
  26
  27 #define PMB_BUS_MAX                     2
  28 #define PMB_BUS_ID_SHIFT                8
  29
  30 #define PMB_BUS_PERIPH                  0
  31 #define PMB_ADDR_PERIPH                 (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
  32 #define PMB_ZONES_PERIPH                4
  33
  34 #define PMB_BUS_CRYPTO                  0
  35 #define PMB_ADDR_CRYPTO                 (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
  36 #define PMB_ZONES_CRYPTO                1
  37
  38 #define PMB_BUS_PCIE2                   0
  39 #define PMB_ADDR_PCIE2                  (2 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
  40 #define PMB_ZONES_PCIE2                 1
  41
  42 #define PMB_BUS_RDP                     0
  43 #define PMB_ADDR_RDP                    (3 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
  44 #define PMB_ZONES_RDP                   2
  45
  46 #define PMB_BUS_FPM                     0
  47 #define PMB_ADDR_FPM                    (4 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
  48 #define PMB_ZONES_FPM                   1
  49
  50 #define PMB_BUS_DQM                     0
  51 #define PMB_ADDR_DQM                    (5 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
  52 #define PMB_ZONES_DQM                   1
  53
  54 #define PMB_BUS_URB                     0
  55 #define PMB_ADDR_URB                    (6 | PMB_BUS_URB << PMB_BUS_ID_SHIFT)
  56 #define PMB_ZONES_URB                   1
  57
  58 #define PMB_BUS_MEMC                    0
  59 #define PMB_ADDR_MEMC                   (7 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
  60 #define PMB_ZONES_MEMC                  1
  61
  62 #define PMB_BUS_RDPPLL                  0
  63 #define PMB_ADDR_RDPPLL                 (8 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
  64 #define PMB_ZONES_RDPPLL                0
  65
  66 #define PMB_BUS_B53PLL                  0
  67 #define PMB_ADDR_B53PLL                 (9 | PMB_BUS_B53PLL << PMB_BUS_ID_SHIFT)
  68 #define PMB_ZONES_B53PLL                0
  69
  70 #define PMB_BUS_SWITCH                  1
  71 #define PMB_ADDR_SWITCH                 (10 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
  72 #define PMB_ZONES_SWITCH                3
  73
  74 #define PMB_BUS_PCM                     1
  75 #define PMB_ADDR_PCM                    (11 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
  76 #define PMB_ZONES_PCM                   2
  77 enum {
  78         PCM_Zone_Main,
  79         PCM_Zone_PCM,
  80 };
  81 //--------- SOFT Reset bits for PCM ------------------------
  82 #define   BPCM_PCM_SRESET_HARDRST_N   0x00000004
  83 #define   BPCM_PCM_SRESET_PCM_N       0x00000002
  84 #define   BPCM_PCM_SRESET_200_N       0x00000001
  85
  86 #define PMB_BUS_SGMII                   1
  87 #define PMB_ADDR_SGMII                  (12 | PMB_BUS_SGMII << PMB_BUS_ID_SHIFT)
  88 #define PMB_ZONES_SGMII                 0
  89
  90 #define PMB_BUS_CHIP_CLKRST             1
  91 #define PMB_ADDR_CHIP_CLKRST            (13 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
  92 #define PMB_ZONES_CHIP_CLKRST           0
  93
  94 #define PMB_BUS_PCIE0                   1
  95 #define PMB_ADDR_PCIE0                  (14 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
  96 #define PMB_ZONES_PCIE0                 1
  97
  98 #define PMB_BUS_PCIE1                   1
  99 #define PMB_ADDR_PCIE1                  (15 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
 100 #define PMB_ZONES_PCIE1                 1
 101
 102 #define PMB_BUS_SATA                    1
 103 #define PMB_ADDR_SATA                   (16 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
 104 #define PMB_ZONES_SATA                  1
 105
 106 #define PMB_BUS_USB                             1
 107 #define PMB_ADDR_USB30_2X               (17 | PMB_BUS_USB << PMB_BUS_ID_SHIFT)
 108 #define PMB_ZONES_USB                   4
 109
 110 #define PMB_BUS_SYSPLL                  1
 111 #define PMB_ADDR_SYSPLL                 (18 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
 112 #define PMB_ZONES_SYSPLL                0
 113
 114 #define PMB_BUS_SWTPLL                  1
 115 #define PMB_ADDR_SWTPLL                 (19 | PMB_BUS_SWTPLL << PMB_BUS_ID_SHIFT)
 116 #define PMB_ZONES_SWTPLL                0
 117
 118 #define PMB_BUS_I2SPLL                  1
 119 #define PMB_ADDR_I2SPLL                 (20 | PMB_BUS_I2SPLL << PMB_BUS_ID_SHIFT)
 120 #define PMB_ZONES_I2SPLL                0
 121
 122 #define PMB_BUS_GMAC                    1
 123 #define PMB_ADDR_GMAC                   (21 | PMB_BUS_GMAC << PMB_BUS_ID_SHIFT)
 124 #define PMB_ZONES_GMAC                  1
 125
 126 #endif