1 From cde57aebfd86b3b062ce0bcf71395d735d05b2f6 Mon Sep 17 00:00:00 2001
2 From: Emil Renner Berthing <kernel@esmil.dk>
3 Date: Wed, 6 Apr 2022 00:38:05 +0200
4 Subject: [PATCH 1018/1024] soc: sifive: ccache: Add StarFive JH71x0 support
6 This adds support for the StarFive JH7100 and JH7110 SoCs which also
7 feature this SiFive cache controller.
9 Unfortunately the interrupt for uncorrected data is broken on the JH7100
10 and fires continuously, so add a quirk to not register a handler for it.
12 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
14 arch/riscv/Kconfig.socs | 1 +
15 drivers/soc/sifive/Kconfig | 2 +-
16 drivers/soc/sifive/sifive_ccache.c | 12 +++++++++++-
17 3 files changed, 13 insertions(+), 2 deletions(-)
19 --- a/arch/riscv/Kconfig.socs
20 +++ b/arch/riscv/Kconfig.socs
21 @@ -28,6 +28,7 @@ config SOC_STARFIVE
24 select RESET_CONTROLLER
25 + select SIFIVE_CCACHE
29 --- a/drivers/soc/sifive/Kconfig
30 +++ b/drivers/soc/sifive/Kconfig
32 # SPDX-License-Identifier: GPL-2.0
35 +if SOC_SIFIVE || SOC_STARFIVE
38 bool "Sifive Composable Cache controller"
39 --- a/drivers/soc/sifive/sifive_ccache.c
40 +++ b/drivers/soc/sifive/sifive_ccache.c
41 @@ -106,6 +106,8 @@ static void ccache_config_read(void)
42 static const struct of_device_id sifive_ccache_ids[] = {
43 { .compatible = "sifive,fu540-c000-ccache" },
44 { .compatible = "sifive,fu740-c000-ccache" },
45 + { .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) },
46 + { .compatible = "starfive,jh7110-ccache" },
47 { .compatible = "sifive,ccache0" },
48 { /* end of table */ }
50 @@ -210,11 +212,15 @@ static int __init sifive_ccache_init(voi
51 struct device_node *np;
54 + const struct of_device_id *match;
55 + unsigned long broken_irqs;
57 - np = of_find_matching_node(NULL, sifive_ccache_ids);
58 + np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
62 + broken_irqs = (uintptr_t)match->data;
64 if (of_address_to_resource(np, 0, &res)) {
67 @@ -240,6 +246,10 @@ static int __init sifive_ccache_init(voi
69 for (i = 0; i < intr_num; i++) {
70 g_irq[i] = irq_of_parse_and_map(np, i);
72 + if (broken_irqs & BIT(i))
75 rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",