target/linux/starfive/patches-6.1/0112-dmaengine-dw-axi-dmac-Add-support-for-StarFive-JH711.patch

   1 From 69ed990fda6795039a2b5b37d8ad5df785f4d97b Mon Sep 17 00:00:00 2001
   2 From: Walker Chen <walker.chen@starfivetech.com>
   3 Date: Wed, 22 Mar 2023 17:48:18 +0800
   4 Subject: [PATCH 112/122] dmaengine: dw-axi-dmac: Add support for StarFive
   5  JH7110 DMA
   6
   7 Add DMA reset operation in device probe and use different configuration
   8 on CH_CFG registers according to match data. Update all uses of
   9 of_device_is_compatible with of_device_get_match_data.
  10
  11 Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
  12 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
  13 ---
  14  .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 38 ++++++++++++++++---
  15  drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  1 +
  16  2 files changed, 34 insertions(+), 5 deletions(-)
  17
  18 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
  19 +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
  20 @@ -21,10 +21,12 @@
  21  #include <linux/kernel.h>
  22  #include <linux/module.h>
  23  #include <linux/of.h>
  24 +#include <linux/of_device.h>
  25  #include <linux/of_dma.h>
  26  #include <linux/platform_device.h>
  27  #include <linux/pm_runtime.h>
  28  #include <linux/property.h>
  29 +#include <linux/reset.h>
  30  #include <linux/slab.h>
  31  #include <linux/types.h>
  32
  33 @@ -46,6 +48,10 @@
  34         DMA_SLAVE_BUSWIDTH_32_BYTES     | \
  35         DMA_SLAVE_BUSWIDTH_64_BYTES)
  36
  37 +#define AXI_DMA_FLAG_HAS_APB_REGS      BIT(0)
  38 +#define AXI_DMA_FLAG_HAS_RESETS                BIT(1)
  39 +#define AXI_DMA_FLAG_USE_CFG2          BIT(2)
  40 +
  41  static inline void
  42  axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
  43  {
  44 @@ -86,7 +92,8 @@ static inline void axi_chan_config_write
  45
  46         cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
  47                   config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
  48 -       if (chan->chip->dw->hdata->reg_map_8_channels) {
  49 +       if (chan->chip->dw->hdata->reg_map_8_channels &&
  50 +           !chan->chip->dw->hdata->use_cfg2) {
  51                 cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
  52                          config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
  53                          config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
  54 @@ -1367,11 +1374,12 @@ static int parse_device_properties(struc
  55
  56  static int dw_probe(struct platform_device *pdev)
  57  {
  58 -       struct device_node *node = pdev->dev.of_node;
  59         struct axi_dma_chip *chip;
  60         struct resource *mem;
  61         struct dw_axi_dma *dw;
  62         struct dw_axi_dma_hcfg *hdata;
  63 +       struct reset_control *resets;
  64 +       unsigned int flags;
  65         u32 i;
  66         int ret;
  67
  68 @@ -1400,12 +1408,25 @@ static int dw_probe(struct platform_devi
  69         if (IS_ERR(chip->regs))
  70                 return PTR_ERR(chip->regs);
  71
  72 -       if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
  73 +       flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
  74 +       if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
  75                 chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
  76                 if (IS_ERR(chip->apb_regs))
  77                         return PTR_ERR(chip->apb_regs);
  78         }
  79
  80 +       if (flags & AXI_DMA_FLAG_HAS_RESETS) {
  81 +               resets = devm_reset_control_array_get_exclusive(&pdev->dev);
  82 +               if (IS_ERR(resets))
  83 +                       return PTR_ERR(resets);
  84 +
  85 +               ret = reset_control_deassert(resets);
  86 +               if (ret)
  87 +                       return ret;
  88 +       }
  89 +
  90 +       chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
  91 +
  92         chip->core_clk = devm_clk_get(chip->dev, "core-clk");
  93         if (IS_ERR(chip->core_clk))
  94                 return PTR_ERR(chip->core_clk);
  95 @@ -1556,8 +1577,15 @@ static const struct dev_pm_ops dw_axi_dm
  96  };
  97
  98  static const struct of_device_id dw_dma_of_id_table[] = {
  99 -       { .compatible = "snps,axi-dma-1.01a" },
 100 -       { .compatible = "intel,kmb-axi-dma" },
 101 +       {
 102 +               .compatible = "snps,axi-dma-1.01a"
 103 +       }, {
 104 +               .compatible = "intel,kmb-axi-dma",
 105 +               .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
 106 +       }, {
 107 +               .compatible = "starfive,jh7110-axi-dma",
 108 +               .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
 109 +       },
 110         {}
 111  };
 112  MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
 113 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
 114 +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
 115 @@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
 116         /* Register map for DMAX_NUM_CHANNELS <= 8 */
 117         bool    reg_map_8_channels;
 118         bool    restrict_axi_burst_len;
 119 +       bool    use_cfg2;
 120  };
 121
 122  struct axi_dma_chan {