starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0091-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch
1 From 6a2392c96041d0599d33799a9aedbcdbfb4030b6 Mon Sep 17 00:00:00 2001
2 From: Minda Chen <minda.chen@starfivetech.com>
3 Date: Thu, 18 May 2023 19:27:48 +0800
4 Subject: [PATCH 091/122] dt-bindings: usb: Add StarFive JH7110 USB controller
5
6 StarFive JH7110 platforms USB have a wrapper module around
7 the Cadence USBSS-DRD controller. Add binding information doc
8 for that.
9
10 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
11 Reviewed-by: Peter Chen <peter.chen@kernel.org>
12 Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
13 ---
14 .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++
15 1 file changed, 115 insertions(+)
16 create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
17
18 --- /dev/null
19 +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
20 @@ -0,0 +1,115 @@
21 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
22 +%YAML 1.2
23 +---
24 +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
25 +$schema: http://devicetree.org/meta-schemas/core.yaml#
26 +
27 +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
28 +
29 +maintainers:
30 + - Minda Chen <minda.chen@starfivetech.com>
31 +
32 +properties:
33 + compatible:
34 + const: starfive,jh7110-usb
35 +
36 + ranges: true
37 +
38 + starfive,stg-syscon:
39 + $ref: /schemas/types.yaml#/definitions/phandle-array
40 + items:
41 + - items:
42 + - description: phandle to System Register Controller stg_syscon node.
43 + - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB.
44 + description:
45 + The phandle to System Register Controller syscon node and the offset
46 + of STG_SYSCONSAIF__SYSCFG register for USB.
47 +
48 + dr_mode:
49 + enum: [host, otg, peripheral]
50 +
51 + "#address-cells":
52 + enum: [1, 2]
53 +
54 + "#size-cells":
55 + enum: [1, 2]
56 +
57 + clocks:
58 + items:
59 + - description: link power management clock
60 + - description: standby clock
61 + - description: APB clock
62 + - description: AXI clock
63 + - description: UTMI APB clock
64 +
65 + clock-names:
66 + items:
67 + - const: lpm
68 + - const: stb
69 + - const: apb
70 + - const: axi
71 + - const: utmi_apb
72 +
73 + resets:
74 + items:
75 + - description: Power up reset
76 + - description: APB clock reset
77 + - description: AXI clock reset
78 + - description: UTMI APB clock reset
79 +
80 + reset-names:
81 + items:
82 + - const: pwrup
83 + - const: apb
84 + - const: axi
85 + - const: utmi_apb
86 +
87 +patternProperties:
88 + "^usb@[0-9a-f]+$":
89 + $ref: cdns,usb3.yaml#
90 + description: Required child node
91 +
92 +required:
93 + - compatible
94 + - ranges
95 + - starfive,stg-syscon
96 + - '#address-cells'
97 + - '#size-cells'
98 + - dr_mode
99 + - clocks
100 + - resets
101 +
102 +additionalProperties: false
103 +
104 +examples:
105 + - |
106 + usb@10100000 {
107 + compatible = "starfive,jh7110-usb";
108 + ranges = <0x0 0x10100000 0x100000>;
109 + #address-cells = <1>;
110 + #size-cells = <1>;
111 + starfive,stg-syscon = <&stg_syscon 0x4>;
112 + clocks = <&syscrg 4>,
113 + <&stgcrg 5>,
114 + <&stgcrg 1>,
115 + <&stgcrg 3>,
116 + <&stgcrg 2>;
117 + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
118 + resets = <&stgcrg 10>,
119 + <&stgcrg 8>,
120 + <&stgcrg 7>,
121 + <&stgcrg 9>;
122 + reset-names = "pwrup", "apb", "axi", "utmi_apb";
123 + dr_mode = "host";
124 +
125 + usb@0 {
126 + compatible = "cdns,usb3";
127 + reg = <0x0 0x10000>,
128 + <0x10000 0x10000>,
129 + <0x20000 0x10000>;
130 + reg-names = "otg", "xhci", "dev";
131 + interrupts = <100>, <108>, <110>;
132 + interrupt-names = "host", "peripheral", "otg";
133 + maximum-speed = "super-speed";
134 + };
135 + };