1 From 6a2392c96041d0599d33799a9aedbcdbfb4030b6 Mon Sep 17 00:00:00 2001
2 From: Minda Chen <minda.chen@starfivetech.com>
3 Date: Thu, 18 May 2023 19:27:48 +0800
4 Subject: [PATCH 091/122] dt-bindings: usb: Add StarFive JH7110 USB controller
6 StarFive JH7110 platforms USB have a wrapper module around
7 the Cadence USBSS-DRD controller. Add binding information doc
10 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
11 Reviewed-by: Peter Chen <peter.chen@kernel.org>
12 Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
14 .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++
15 1 file changed, 115 insertions(+)
16 create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
19 +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
21 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
24 +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
25 +$schema: http://devicetree.org/meta-schemas/core.yaml#
27 +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
30 + - Minda Chen <minda.chen@starfivetech.com>
34 + const: starfive,jh7110-usb
38 + starfive,stg-syscon:
39 + $ref: /schemas/types.yaml#/definitions/phandle-array
42 + - description: phandle to System Register Controller stg_syscon node.
43 + - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB.
45 + The phandle to System Register Controller syscon node and the offset
46 + of STG_SYSCONSAIF__SYSCFG register for USB.
49 + enum: [host, otg, peripheral]
59 + - description: link power management clock
60 + - description: standby clock
61 + - description: APB clock
62 + - description: AXI clock
63 + - description: UTMI APB clock
75 + - description: Power up reset
76 + - description: APB clock reset
77 + - description: AXI clock reset
78 + - description: UTMI APB clock reset
89 + $ref: cdns,usb3.yaml#
90 + description: Required child node
95 + - starfive,stg-syscon
102 +additionalProperties: false
107 + compatible = "starfive,jh7110-usb";
108 + ranges = <0x0 0x10100000 0x100000>;
109 + #address-cells = <1>;
111 + starfive,stg-syscon = <&stg_syscon 0x4>;
112 + clocks = <&syscrg 4>,
117 + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
118 + resets = <&stgcrg 10>,
122 + reset-names = "pwrup", "apb", "axi", "utmi_apb";
126 + compatible = "cdns,usb3";
127 + reg = <0x0 0x10000>,
130 + reg-names = "otg", "xhci", "dev";
131 + interrupts = <100>, <108>, <110>;
132 + interrupt-names = "host", "peripheral", "otg";
133 + maximum-speed = "super-speed";