3b3b7ad2f84f04a344e53e05f062be24a4923db5
[openwrt/staging/hauke.git] / target / linux / realtek / dts-5.15 / rtl8382_tplink_t1600g-28ts-v3.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "rtl838x.dtsi"
4
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8
9 / {
10 compatible = "tplink,t1600g-28ts-v3", "realtek,rtl838x-soc";
11 model = "TP-Link T1600G-28TS v3";
12
13 aliases {
14 led-boot = &led_sys;
15 led-failsafe = &led_sys;
16 led-running = &led_sys;
17 led-upgrade = &led_sys;
18 label-mac-device = &ethernet0;
19 };
20
21 chosen {
22 stdout-path = "serial0:38400n8";
23 };
24
25 leds {
26 pinctrl-names = "default";
27 compatible = "gpio-leds";
28
29 led_sys: led-0 {
30 label = "green:sys";
31 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
32 color = <LED_COLOR_ID_GREEN>;
33 function = LED_FUNCTION_STATUS;
34 };
35 };
36
37 memory@0 {
38 device_type = "memory";
39 reg = <0x0 0x10000000>;
40 };
41 };
42
43 &spi0 {
44 status = "okay";
45
46 flash@0 {
47 compatible = "jedec,spi-nor";
48 reg = <0>;
49 spi-max-frequency = <10000000>;
50
51 partitions {
52 compatible = "fixed-partitions";
53 #address-cells = <1>;
54 #size-cells = <1>;
55
56 partition@0 {
57 label = "u-boot";
58 reg = <0x0 0xe0000>;
59 read-only;
60 };
61 partition@e0000 {
62 label = "u-boot-env";
63 reg = <0xe0000 0x20000>;
64 };
65 partition@100000 {
66 compatible = "denx,uimage";
67 label = "firmware";
68 reg = <0x100000 0x1a00000>;
69 };
70 partition@1b00000 {
71 label = "usrappfs";
72 reg = <0x1b00000 0x400000>;
73 };
74 partition@1f00000 {
75 compatible = "nvmem-cells";
76 label = "para";
77 reg = <0x1f00000 0x100000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 read-only;
81
82 factory_macaddr: macaddr@fdff4 {
83 reg = <0xfdff4 0x6>;
84 };
85 };
86 };
87 };
88 };
89
90 &ethernet0 {
91 nvmem-cells = <&factory_macaddr>;
92 nvmem-cell-names = "mac-address";
93
94 mdio-bus {
95 compatible = "realtek,rtl838x-mdio";
96 regmap = <&ethernet0>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 EXTERNAL_PHY(0)
101 EXTERNAL_PHY(1)
102 EXTERNAL_PHY(2)
103 EXTERNAL_PHY(3)
104 EXTERNAL_PHY(4)
105 EXTERNAL_PHY(5)
106 EXTERNAL_PHY(6)
107 EXTERNAL_PHY(7)
108
109 INTERNAL_PHY(8)
110 INTERNAL_PHY(9)
111 INTERNAL_PHY(10)
112 INTERNAL_PHY(11)
113 INTERNAL_PHY(12)
114 INTERNAL_PHY(13)
115 INTERNAL_PHY(14)
116 INTERNAL_PHY(15)
117
118 EXTERNAL_PHY(16)
119 EXTERNAL_PHY(17)
120 EXTERNAL_PHY(18)
121 EXTERNAL_PHY(19)
122 EXTERNAL_PHY(20)
123 EXTERNAL_PHY(21)
124 EXTERNAL_PHY(22)
125 EXTERNAL_PHY(23)
126 };
127 };
128
129 &switch0 {
130 ports {
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 SWITCH_PORT(0, 1, qsgmii)
135 SWITCH_PORT(1, 2, qsgmii)
136 SWITCH_PORT(2, 3, qsgmii)
137 SWITCH_PORT(3, 4, qsgmii)
138 SWITCH_PORT(4, 5, qsgmii)
139 SWITCH_PORT(5, 6, qsgmii)
140 SWITCH_PORT(6, 7, qsgmii)
141 SWITCH_PORT(7, 8, qsgmii)
142
143 SWITCH_PORT(8, 9, internal)
144 SWITCH_PORT(9, 10, internal)
145 SWITCH_PORT(10, 11, internal)
146 SWITCH_PORT(11, 12, internal)
147 SWITCH_PORT(12, 13, internal)
148 SWITCH_PORT(13, 14, internal)
149 SWITCH_PORT(14, 15, internal)
150 SWITCH_PORT(15, 16, internal)
151
152 SWITCH_PORT(16, 17, qsgmii)
153 SWITCH_PORT(17, 18, qsgmii)
154 SWITCH_PORT(18, 19, qsgmii)
155 SWITCH_PORT(19, 20, qsgmii)
156 SWITCH_PORT(20, 21, qsgmii)
157 SWITCH_PORT(21, 22, qsgmii)
158 SWITCH_PORT(22, 23, qsgmii)
159 SWITCH_PORT(23, 24, qsgmii)
160
161 port@28 {
162 ethernet = <&ethernet0>;
163 reg = <28>;
164 phy-mode = "internal";
165
166 fixed-link {
167 speed = <1000>;
168 full-duplex;
169 };
170 };
171 };
172 };