d1: add new target
[openwrt/staging/mans0n.git] / target / linux / d1 / patches-6.1 / 0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch
1 From 03dbb926f6d65f75af902e421c44aeaaf84be66a Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Thu, 11 Aug 2022 22:46:28 -0500
4 Subject: [PATCH 089/117] riscv: dts: allwinner: lichee-rv-86-panel-480p: Add
5 panel
6
7 Signed-off-by: Samuel Holland <samuel@sholland.org>
8 ---
9 .../sun20i-d1-lichee-rv-86-panel-480p.dts | 51 +++++++++++++++++++
10 1 file changed, 51 insertions(+)
11
12 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
13 +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
14 @@ -7,6 +7,40 @@
15 model = "Sipeed Lichee RV 86 Panel (480p)";
16 compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
17 "allwinner,sun20i-d1";
18 +
19 + backlight: backlight {
20 + compatible = "pwm-backlight";
21 + power-supply = <&reg_vcc>;
22 + pwms = <&pwm 7 50000 0>;
23 + };
24 +
25 + spi {
26 + compatible = "spi-gpio";
27 + cs-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
28 + mosi-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
29 + sck-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
30 + num-chipselects = <1>;
31 + #address-cells = <1>;
32 + #size-cells = <0>;
33 +
34 + panel@0 {
35 + compatible = "sitronix,st7701s";
36 + reg = <0>;
37 + backlight = <&backlight>;
38 + reset-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
39 + spi-3wire;
40 +
41 + port {
42 + panel_in_tcon_lcd0: endpoint {
43 + remote-endpoint = <&tcon_lcd0_out_panel>;
44 + };
45 + };
46 + };
47 + };
48 +};
49 +
50 +&de {
51 + status = "okay";
52 };
53
54 &i2c2 {
55 @@ -27,3 +61,20 @@
56 wakeup-source;
57 };
58 };
59 +
60 +&pwm {
61 + pinctrl-0 = <&pwm7_pd22_pin>;
62 + pinctrl-names = "default";
63 + status = "okay";
64 +};
65 +
66 +&tcon_lcd0 {
67 + pinctrl-0 = <&lcd_rgb666_pins>;
68 + pinctrl-names = "default";
69 +};
70 +
71 +&tcon_lcd0_out {
72 + tcon_lcd0_out_panel: endpoint {
73 + remote-endpoint = <&panel_in_tcon_lcd0>;
74 + };
75 +};