AArch32: Disable Secure Cycle Counter
authorAlexei Fedorov <Alexei.Fedorov@arm.com>
Tue, 20 Aug 2019 14:22:44 +0000 (15:22 +0100)
committerPaul Beesley <paul.beesley@arm.com>
Thu, 26 Sep 2019 15:36:02 +0000 (15:36 +0000)
commitc3e8b0be9bde36d220beea5d0452ecd04dcd94c6
tree2f5efa0f2fc2f922e19abd9e1eadebc0c8eb8f85
parent69ef7b7ffe66b64bdffee0a387774e7088022503
AArch32: Disable Secure Cycle Counter

This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.

Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
bl32/sp_min/aarch32/entrypoint.S
include/arch/aarch32/arch.h
include/arch/aarch32/el3_common_macros.S
include/arch/aarch32/smccc_macros.S
lib/el3_runtime/aarch32/context_mgmt.c