From b4864bf1135359f7b8012dedb5d5c37fadb22fdc Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sun, 27 Aug 2023 01:05:32 +0200 Subject: [PATCH] uboot-sunxi: t113: refresh patches to fix clock issues Signed-off-by: Zoltan HERPAI --- ...3t-bananapi-m3-describe-SATA-disk-re.patch | 52 - ...=> 4000-sunxi-remove-CONFIG_SATAPWR.patch} | 4 +- ...xi_emac-Switch-to-new-U-Boot-PHY-API.patch | 46 + ...chase-DT-nodes-to-find-PHY-regulator.patch | 102 ++ ...mac-Add-a-structure-for-variant-data.patch | 152 ++ ...n8i-emac-Add-a-flag-for-RMII-support.patch | 77 + ...nctrl-sunxi-add-GPIO-in-out-wrappers.patch | 120 -- ...dd-a-flag-for-the-internal-PHY-switc.patch | 47 + ...emac-Use-common-syscon-setup-for-R40.patch | 133 ++ ...sun8i-emac-Remove-the-SoC-variant-ID.patch | 70 + ... => 4008-sunxi-remove-CONFIG_MACPWR.patch} | 78 +- ...nctrl-sunxi-add-GPIO-in-out-wrappers.patch | 169 ++ ...ctrl-sunxi-remove-struct-sunxi_gpio.patch} | 118 +- ...e-pinctrl-code-and-remove-GPIO_EXTR.patch} | 16 +- ...nxi-move-PIO_BASE-into-sunxi_gpio.h.patch} | 8 +- ...rl-sunxi-add-new-D1-pinctrl-support.patch} | 10 +- ...xi-introduce-NCAT2-generation-model.patch} | 118 +- ...dd-Allwinner-D1-pinctrl-description.patch} | 6 +- ...lk-sunxi-Add-support-for-the-D1-CCU.patch} | 78 +- ...28-Enable-PLL-LDO-during-PLL1-setup.patch} | 6 +- ...xi-clock-support-D1-R528-PLL6-clock.patch} | 6 +- ...-clock-h6-prepare-for-PRCM-less-SoCs.patch | 75 + ...prepare-for-using-drivers-ram-sunxi.patch} | 21 +- ...13-s3-D1-s-DRAM-initialisation-code.patch} | 362 ++-- ...add-Allwinner-R528-T113-SoC-support.patch} | 48 +- ...rial-base-addresses-to-avoid-asm-ar.patch} | 40 +- ...inner-Add-the-D1-D1s-SoC-devicetree.patch} | 38 +- ...unxi-add-Allwinner-T113-s-SoC-.dtsi.patch} | 36 +- ...unxi-add-MangoPi-MQ-R-board-support.patch} | 26 +- ..._pins-on-Port-E-PE2-PE3-on-D1s-T133.patch} | 6 +- ...ort-for-MangoPI-MQDual-T113-variant.patch} | 4 +- ...t-for-UART5-in-Port-E-group-on-T133.patch} | 6 +- ...030-sunxi-add-MYIR-MYD-YT113X-board.patch} | 41 +- ...xi-add-support-for-UART3-on-PE-pins.patch} | 12 +- ...d-support-for-Rongpin-RP-T113-board.patch} | 4 +- ...h => 4033-net-add-ICPlus-PHY-driver.patch} | 4 +- ...unxi-enable-emac-on-Rongpin-RP-T113.patch} | 4 +- ...r-for-Motorcomm-yt8531-gigabit-ethe.patch} | 4 +- ...-on-MYIR-MYD-YT113X-with-the-YT8531.patch} | 21 +- ...and-update-driver-for-Motorcomm-yt8.patch} | 4 +- ...-rp-t113-add-missing-gpio.h-include.patch} | 4 +- ...d-SPI-boot-support-for-the-Allwinner.patch | 206 +++ ...pport-for-R329-D1-R528-T113-SPI-cont.patch | 122 ++ ...llwinner-d1-Add-SPI-controllers-node.patch | 77 + ...sunxi-add-MYIR-MYD-YT113X-SPI-board.patch} | 49 +- ...unxi-add-support-for-emac-on-PG-pins.patch | 34 + ...ernet-support-on-MYIR-MYD-YT113X-SPI.patch | 62 + ...i-nand-backport-from-upstream-kernel.patch | 1569 +++++++++++++++++ ...tition-table-for-MYIR-MYD-YT113X-SPI.patch | 60 + ...-UBI-support-for-MYIR-MYD-YT113X-SPI.patch | 22 + ...1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch | 31 + .../uboot-sunxi/patches/4100-SQUASH-ME.patch | 44 - ...-psci-clean-away-preprocessor-macros.patch | 148 -- ...tor-register-access-to-separate-func.patch | 145 -- ...03-sunxi-psci-implement-PSCI-on-R528.patch | 154 -- .../boot/uboot-sunxi/patches/4200-spi.patch | 751 -------- 56 files changed, 3692 insertions(+), 1958 deletions(-) delete mode 100644 package/boot/uboot-sunxi/patches/4000-ARM-dts-sun8i-a83t-bananapi-m3-describe-SATA-disk-re.patch rename package/boot/uboot-sunxi/patches/{4001-sunxi-remove-CONFIG_SATAPWR.patch => 4000-sunxi-remove-CONFIG_SATAPWR.patch} (99%) create mode 100644 package/boot/uboot-sunxi/patches/4001-net-sunxi_emac-Switch-to-new-U-Boot-PHY-API.patch create mode 100644 package/boot/uboot-sunxi/patches/4002-net-sunxi_emac-chase-DT-nodes-to-find-PHY-regulator.patch create mode 100644 package/boot/uboot-sunxi/patches/4003-net-sun8i-emac-Add-a-structure-for-variant-data.patch create mode 100644 package/boot/uboot-sunxi/patches/4004-net-sun8i-emac-Add-a-flag-for-RMII-support.patch delete mode 100644 package/boot/uboot-sunxi/patches/4004-pinctrl-sunxi-add-GPIO-in-out-wrappers.patch create mode 100644 package/boot/uboot-sunxi/patches/4005-net-sun8i-emac-Add-a-flag-for-the-internal-PHY-switc.patch create mode 100644 package/boot/uboot-sunxi/patches/4006-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch create mode 100644 package/boot/uboot-sunxi/patches/4007-net-sun8i-emac-Remove-the-SoC-variant-ID.patch rename package/boot/uboot-sunxi/patches/{4002-sunxi-remove-CONFIG_MACPWR.patch => 4008-sunxi-remove-CONFIG_MACPWR.patch} (86%) create mode 100644 package/boot/uboot-sunxi/patches/4009-pinctrl-sunxi-add-GPIO-in-out-wrappers.patch rename package/boot/uboot-sunxi/patches/{4003-pinctrl-sunxi-remove-struct-sunxi_gpio.patch => 4010-pinctrl-sunxi-remove-struct-sunxi_gpio.patch} (84%) rename package/boot/uboot-sunxi/patches/{4005-pinctrl-sunxi-move-pinctrl-code-and-remove-GPIO_EXTR.patch => 4011-pinctrl-sunxi-move-pinctrl-code-and-remove-GPIO_EXTR.patch} (96%) rename package/boot/uboot-sunxi/patches/{4006-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch => 4012-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch} (95%) rename package/boot/uboot-sunxi/patches/{4007-pinctrl-sunxi-add-new-D1-pinctrl-support.patch => 4013-pinctrl-sunxi-add-new-D1-pinctrl-support.patch} (90%) rename package/boot/uboot-sunxi/patches/{4008-sunxi-introduce-NCAT2-generation-model.patch => 4014-sunxi-introduce-NCAT2-generation-model.patch} (81%) rename package/boot/uboot-sunxi/patches/{4009-pinctrl-sunxi-add-Allwinner-D1-pinctrl-description.patch => 4015-pinctrl-sunxi-add-Allwinner-D1-pinctrl-description.patch} (93%) rename package/boot/uboot-sunxi/patches/{4010-clk-sunxi-Add-support-for-the-D1-CCU.patch => 4016-clk-sunxi-Add-support-for-the-D1-CCU.patch} (86%) rename package/boot/uboot-sunxi/patches/{4011-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch => 4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch} (91%) rename package/boot/uboot-sunxi/patches/{4012-sunxi-clock-support-D1-R528-PLL6-clock.patch => 4018-sunxi-clock-support-D1-R528-PLL6-clock.patch} (93%) create mode 100644 package/boot/uboot-sunxi/patches/4019-sunxi-clock-h6-prepare-for-PRCM-less-SoCs.patch rename package/boot/uboot-sunxi/patches/{4013-Kconfig-sunxi-prepare-for-using-drivers-ram-sunxi.patch => 4020-Kconfig-sunxi-prepare-for-using-drivers-ram-sunxi.patch} (74%) rename package/boot/uboot-sunxi/patches/{4014-sunxi-add-R528-T113-s3-D1-s-DRAM-initialisation-code.patch => 4021-sunxi-add-R528-T113-s3-D1-s-DRAM-initialisation-code.patch} (82%) rename package/boot/uboot-sunxi/patches/{4015-sunxi-add-early-Allwinner-R528-T113-SoC-support.patch => 4022-sunxi-add-Allwinner-R528-T113-SoC-support.patch} (83%) rename package/boot/uboot-sunxi/patches/{4016-sunxi-refactor-serial-base-addresses-to-avoid-asm-ar.patch => 4023-sunxi-refactor-serial-base-addresses-to-avoid-asm-ar.patch} (89%) rename package/boot/uboot-sunxi/patches/{4017-riscv-dts-allwinner-Add-the-D1-D1s-SoC-devicetree.patch => 4024-riscv-dts-allwinner-Add-the-D1-D1s-SoC-devicetree.patch} (97%) rename package/boot/uboot-sunxi/patches/{4018-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch => 4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch} (68%) rename package/boot/uboot-sunxi/patches/{4019-sunxi-add-preliminary-MangoPi-MQ-R-board-support.patch => 4026-sunxi-add-MangoPi-MQ-R-board-support.patch} (92%) rename package/boot/uboot-sunxi/patches/{4020-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch => 4027-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch} (79%) rename package/boot/uboot-sunxi/patches/{4021-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch => 4028-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch} (95%) rename package/boot/uboot-sunxi/patches/{4022-sunxi-add-support-for-UART5-in-Port-E-group-on-T133.patch => 4029-sunxi-add-support-for-UART5-in-Port-E-group-on-T133.patch} (94%) rename package/boot/uboot-sunxi/patches/{4023-sunxi-add-MYIR-MYD-YT113X-board.patch => 4030-sunxi-add-MYIR-MYD-YT113X-board.patch} (76%) rename package/boot/uboot-sunxi/patches/{4024-sunxi-add-support-for-UART3-on-PE-pins.patch => 4031-sunxi-add-support-for-UART3-on-PE-pins.patch} (92%) rename package/boot/uboot-sunxi/patches/{4025-sunxi-add-support-for-Rongpin-RP-T113-board.patch => 4032-sunxi-add-support-for-Rongpin-RP-T113-board.patch} (96%) rename package/boot/uboot-sunxi/patches/{4026-net-add-ICPlus-PHY-driver.patch => 4033-net-add-ICPlus-PHY-driver.patch} (97%) rename package/boot/uboot-sunxi/patches/{4027-sunxi-enable-emac-on-Rongpin-RP-T113.patch => 4034-sunxi-enable-emac-on-Rongpin-RP-T113.patch} (95%) rename package/boot/uboot-sunxi/patches/{4028-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch => 4035-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch} (99%) rename package/boot/uboot-sunxi/patches/{4029-sunxi-enable-gmac-on-MYIR-MYD-YT113X-with-the-YT8531.patch => 4036-sunxi-enable-gmac-on-MYIR-MYD-YT113X-with-the-YT8531.patch} (55%) rename package/boot/uboot-sunxi/patches/{4030-net-phy-backport-and-update-driver-for-Motorcomm-yt8.patch => 4037-net-phy-backport-and-update-driver-for-Motorcomm-yt8.patch} (93%) rename package/boot/uboot-sunxi/patches/{4031-sunxi-rongpin-rp-t113-add-missing-gpio.h-include.patch => 4038-sunxi-rongpin-rp-t113-add-missing-gpio.h-include.patch} (83%) create mode 100644 package/boot/uboot-sunxi/patches/4039-sunxi-SPL-SPI-Add-SPI-boot-support-for-the-Allwinner.patch create mode 100644 package/boot/uboot-sunxi/patches/4040-spi-sunxi-Add-support-for-R329-D1-R528-T113-SPI-cont.patch create mode 100644 package/boot/uboot-sunxi/patches/4041-riscv-dts-allwinner-d1-Add-SPI-controllers-node.patch rename package/boot/uboot-sunxi/patches/{4201-myir-spi.patch => 4042-sunxi-add-MYIR-MYD-YT113X-SPI-board.patch} (61%) create mode 100644 package/boot/uboot-sunxi/patches/4043-sunxi-add-support-for-emac-on-PG-pins.patch create mode 100644 package/boot/uboot-sunxi/patches/4044-sunxi-add-ethernet-support-on-MYIR-MYD-YT113X-SPI.patch create mode 100644 package/boot/uboot-sunxi/patches/4045-mtd-spi-nand-backport-from-upstream-kernel.patch create mode 100644 package/boot/uboot-sunxi/patches/4046-arm-dts-add-partition-table-for-MYIR-MYD-YT113X-SPI.patch create mode 100644 package/boot/uboot-sunxi/patches/4047-configs-enable-UBI-support-for-MYIR-MYD-YT113X-SPI.patch create mode 100644 package/boot/uboot-sunxi/patches/4048-sunxi-r528-d1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch delete mode 100644 package/boot/uboot-sunxi/patches/4100-SQUASH-ME.patch delete mode 100644 package/boot/uboot-sunxi/patches/4101-sunxi-psci-clean-away-preprocessor-macros.patch delete mode 100644 package/boot/uboot-sunxi/patches/4102-sunxi-psci-refactor-register-access-to-separate-func.patch delete mode 100644 package/boot/uboot-sunxi/patches/4103-sunxi-psci-implement-PSCI-on-R528.patch delete mode 100644 package/boot/uboot-sunxi/patches/4200-spi.patch diff --git a/package/boot/uboot-sunxi/patches/4000-ARM-dts-sun8i-a83t-bananapi-m3-describe-SATA-disk-re.patch b/package/boot/uboot-sunxi/patches/4000-ARM-dts-sun8i-a83t-bananapi-m3-describe-SATA-disk-re.patch deleted file mode 100644 index 0abc2e682c..0000000000 --- a/package/boot/uboot-sunxi/patches/4000-ARM-dts-sun8i-a83t-bananapi-m3-describe-SATA-disk-re.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 99a186dbbbc9869d705fb3c189bcafc87c3bfe75 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Thu, 19 Jan 2023 23:40:20 +0000 -Subject: [PATCH 4000/4031] ARM: dts: sun8i: a83t: bananapi-m3: describe SATA - disk regulator - -The Bananapi-M3 has a SATA connector, driven by a USB-to-SATA bridge -soldered on the board. The power for the SATA device is provided by a -GPIO controlled regulator. Since the SATA device is behind USB, it has -no DT node, so we never described this regulator. Instead U-Boot was -turning this on in a rather hackish way, which we now want to get rid of. -On top of that it seems fragile to leave this GPIO undescribed, as -userland could claim it and turn the disk off. - -Add a fixed regulator, controlled by the PD25 GPIO, and mark it as -always-on. This would mimic the current situation, but in a safer way, -and would allow U-Boot to drop the CONFIG_SATAPWR enable hack. - -Signed-off-by: Andre Przywara ---- - arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts -index b60016a442..197cf6959b 100644 ---- a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts -+++ b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts -@@ -105,6 +105,21 @@ - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -+ -+ /* -+ * Power supply for the SATA disk, behind a USB-SATA bridge. -+ * Since it is a USB device, there is no consumer in the DT, so we -+ * have to keep this always on. -+ */ -+ regulator-sata-disk-pwr { -+ compatible = "regulator-fixed"; -+ regulator-name = "sata-disk-pwr"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ enable-active-high; -+ gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ -+ }; - }; - - &cpu0 { --- -2.20.1 - diff --git a/package/boot/uboot-sunxi/patches/4001-sunxi-remove-CONFIG_SATAPWR.patch b/package/boot/uboot-sunxi/patches/4000-sunxi-remove-CONFIG_SATAPWR.patch similarity index 99% rename from package/boot/uboot-sunxi/patches/4001-sunxi-remove-CONFIG_SATAPWR.patch rename to package/boot/uboot-sunxi/patches/4000-sunxi-remove-CONFIG_SATAPWR.patch index eb4e543af3..8924000f7c 100644 --- a/package/boot/uboot-sunxi/patches/4001-sunxi-remove-CONFIG_SATAPWR.patch +++ b/package/boot/uboot-sunxi/patches/4000-sunxi-remove-CONFIG_SATAPWR.patch @@ -1,7 +1,7 @@ -From f79b84dca3597605c29793ad69ada86d5932d8cb Mon Sep 17 00:00:00 2001 +From cb7c055953c65ce4b532e3548fb6676515c1c1b9 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 15 Jul 2022 16:52:14 +0100 -Subject: [PATCH 4001/4031] sunxi: remove CONFIG_SATAPWR +Subject: [PATCH 4000/4044] sunxi: remove CONFIG_SATAPWR The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that enables the power for a SATA harddisk. diff --git a/package/boot/uboot-sunxi/patches/4001-net-sunxi_emac-Switch-to-new-U-Boot-PHY-API.patch b/package/boot/uboot-sunxi/patches/4001-net-sunxi_emac-Switch-to-new-U-Boot-PHY-API.patch new file mode 100644 index 0000000000..d3d1ae01fa --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4001-net-sunxi_emac-Switch-to-new-U-Boot-PHY-API.patch @@ -0,0 +1,46 @@ +From b68b48654248dedb7127631003a206cbfe7c5a2c Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Wed, 31 May 2023 00:51:24 +0200 +Subject: [PATCH 4001/4044] net: sunxi_emac: Switch to new U-Boot PHY API + +Use new U-Boot phy_connect() API which also supports fixed PHYs. + +Signed-off-by: Marek Vasut +Reviewed-by: Ramon Fried +--- + drivers/net/sunxi_emac.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c +index ad9e1abd16..4c90d4b498 100644 +--- a/drivers/net/sunxi_emac.c ++++ b/drivers/net/sunxi_emac.c +@@ -248,10 +248,10 @@ static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + + static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev) + { +- int ret, mask = 0xffffffff; ++ int ret, mask = -1; + + #ifdef CONFIG_PHY_ADDR +- mask = 1 << CONFIG_PHY_ADDR; ++ mask = CONFIG_PHY_ADDR; + #endif + + priv->bus = mdio_alloc(); +@@ -269,11 +269,10 @@ static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev) + if (ret) + return ret; + +- priv->phydev = phy_find_by_mask(priv->bus, mask); ++ priv->phydev = phy_connect(priv->bus, mask, dev, PHY_INTERFACE_MODE_MII); + if (!priv->phydev) + return -ENODEV; + +- phy_connect_dev(priv->phydev, dev, PHY_INTERFACE_MODE_MII); + phy_config(priv->phydev); + + return 0; +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4002-net-sunxi_emac-chase-DT-nodes-to-find-PHY-regulator.patch b/package/boot/uboot-sunxi/patches/4002-net-sunxi_emac-chase-DT-nodes-to-find-PHY-regulator.patch new file mode 100644 index 0000000000..e3d5ca365a --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4002-net-sunxi_emac-chase-DT-nodes-to-find-PHY-regulator.patch @@ -0,0 +1,102 @@ +From 91d57f14ebe23a425354a039d0a68926f3292d5f Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Fri, 21 Jul 2023 14:45:47 +0100 +Subject: [PATCH 4002/4044] net: sunxi_emac: chase DT nodes to find PHY + regulator + +At the moment the sun4i EMAC driver relies on hardcoded CONFIG_MACPWR +Kconfig symbols to enable potential PHY regulators. As we want to get rid +of those, we need to find the regulator by chasing up the DT. + +The sun4i-emac binding puts the PHY regulator into the MDIO node, which +is the parent of the PHY device. U-Boot does not have (and does not +need) an MDIO driver, so we need to chase down the regulator through the +EMAC node: we follow the "phy-handle" property to find the PHY node, +then go up to its parent, where we find the "phy-supply" link to the +regulator. Let U-Boot find the associated regulator device, and put that +into the private device struct, so we can find and enable the regulator +at probe time, later. + +Signed-off-by: Andre Przywara +Reviewed-by: Sam Edwards +--- + drivers/net/sunxi_emac.c | 39 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c +index 4c90d4b498..f1f0e5bbbb 100644 +--- a/drivers/net/sunxi_emac.c ++++ b/drivers/net/sunxi_emac.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + /* EMAC register */ + struct emac_regs { +@@ -165,6 +166,7 @@ struct emac_eth_dev { + struct phy_device *phydev; + int link_printed; + uchar rx_buf[EMAC_RX_BUFSIZE]; ++ struct udevice *phy_reg; + }; + + struct emac_rxhdr { +@@ -572,6 +574,9 @@ static int sunxi_emac_eth_probe(struct udevice *dev) + if (ret) + return ret; + ++ if (priv->phy_reg) ++ regulator_set_enable(priv->phy_reg, true); ++ + return sunxi_emac_init_phy(priv, dev); + } + +@@ -585,9 +590,43 @@ static const struct eth_ops sunxi_emac_eth_ops = { + static int sunxi_emac_eth_of_to_plat(struct udevice *dev) + { + struct eth_pdata *pdata = dev_get_plat(dev); ++ struct emac_eth_dev *priv = dev_get_priv(dev); ++ struct ofnode_phandle_args args; ++ ofnode mdio_node; ++ int ret; + + pdata->iobase = dev_read_addr(dev); + ++ /* The PHY regulator is in the MDIO node, not the EMAC or PHY node. */ ++ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); ++ if (ret) { ++ dev_err(dev, "failed to get PHY node\n"); ++ return ret; ++ } ++ ++ /* ++ * U-Boot does not have (and does not need) a device driver for the ++ * MDIO device, so just "pass through" that DT node to get to the ++ * regulator phandle. ++ * The PHY regulator is optional, though: ignore if we cannot find ++ * a phy-supply property. ++ */ ++ mdio_node = ofnode_get_parent(args.node); ++ ret= ofnode_parse_phandle_with_args(mdio_node, "phy-supply", NULL, 0, 0, ++ &args); ++ if (ret && ret != -ENOENT) { ++ dev_err(dev, "failed to get PHY supply node\n"); ++ return ret; ++ } ++ if (!ret) { ++ ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR, args.node, ++ &priv->phy_reg); ++ if (ret) { ++ dev_err(dev, "failed to get PHY regulator node\n"); ++ return ret; ++ } ++ } ++ + return 0; + } + +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4003-net-sun8i-emac-Add-a-structure-for-variant-data.patch b/package/boot/uboot-sunxi/patches/4003-net-sun8i-emac-Add-a-structure-for-variant-data.patch new file mode 100644 index 0000000000..edadb243d9 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4003-net-sun8i-emac-Add-a-structure-for-variant-data.patch @@ -0,0 +1,152 @@ +From 418993044499a9466a6be214c9d996e6e3b09798 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 22 Jan 2023 16:51:02 -0600 +Subject: [PATCH 4003/4044] net: sun8i-emac: Add a structure for variant data + +Currently, EMAC variants are distinguished by their identity, but this +gets unwieldy as more overlapping variants are added. Add a structure so +we can describe the individual feature differences between the variants. + +Signed-off-by: Samuel Holland +Reviewed-by: Andre Przywara +Reviewed-by: Ramon Fried +--- + drivers/net/sun8i_emac.c | 65 +++++++++++++++++++++++++++------------- + 1 file changed, 45 insertions(+), 20 deletions(-) + +diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c +index e800a326b8..986e565cd8 100644 +--- a/drivers/net/sun8i_emac.c ++++ b/drivers/net/sun8i_emac.c +@@ -127,7 +127,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + +-enum emac_variant { ++enum emac_variant_id { + A83T_EMAC = 1, + H3_EMAC, + A64_EMAC, +@@ -135,6 +135,10 @@ enum emac_variant { + H6_EMAC, + }; + ++struct emac_variant { ++ enum emac_variant_id variant; ++}; ++ + struct emac_dma_desc { + u32 status; + u32 ctl_size; +@@ -160,7 +164,7 @@ struct emac_eth_dev { + u32 tx_slot; + bool use_internal_phy; + +- enum emac_variant variant; ++ const struct emac_variant *variant; + void *mac_reg; + phys_addr_t sysctl_reg; + struct phy_device *phydev; +@@ -317,7 +321,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + { + u32 reg; + +- if (priv->variant == R40_GMAC) { ++ if (priv->variant->variant == R40_GMAC) { + /* Select RGMII for R40 */ + reg = readl(priv->sysctl_reg + 0x164); + reg |= SC_ETCS_INT_GMII | +@@ -333,9 +337,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + reg = sun8i_emac_set_syscon_ephy(priv, reg); + + reg &= ~(SC_ETCS_MASK | SC_EPIT); +- if (priv->variant == H3_EMAC || +- priv->variant == A64_EMAC || +- priv->variant == H6_EMAC) ++ if (priv->variant->variant == H3_EMAC || ++ priv->variant->variant == A64_EMAC || ++ priv->variant->variant == H6_EMAC) + reg &= ~SC_RMII_EN; + + switch (priv->interface) { +@@ -349,9 +353,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + reg |= SC_EPIT | SC_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: +- if (priv->variant == H3_EMAC || +- priv->variant == A64_EMAC || +- priv->variant == H6_EMAC) { ++ if (priv->variant->variant == H3_EMAC || ++ priv->variant->variant == A64_EMAC || ++ priv->variant->variant == H6_EMAC) { + reg |= SC_RMII_EN | SC_ETCS_EXT_GMII; + break; + } +@@ -806,7 +810,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + return -EINVAL; + } + +- priv->variant = dev_get_driver_data(dev); ++ priv->variant = (const void *)dev_get_driver_data(dev); + + if (!priv->variant) { + printf("%s: Missing variant\n", __func__); +@@ -860,7 +864,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) + return -EINVAL; + +- if (priv->variant == H3_EMAC) { ++ if (priv->variant->variant == H3_EMAC) { + ret = sun8i_handle_internal_phy(dev, priv); + if (ret) + return ret; +@@ -900,16 +904,37 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + return 0; + } + ++static const struct emac_variant emac_variant_a83t = { ++ .variant = A83T_EMAC, ++}; ++ ++static const struct emac_variant emac_variant_h3 = { ++ .variant = H3_EMAC, ++}; ++ ++static const struct emac_variant emac_variant_r40 = { ++ .variant = R40_GMAC, ++}; ++ ++static const struct emac_variant emac_variant_a64 = { ++ .variant = A64_EMAC, ++}; ++ ++static const struct emac_variant emac_variant_h6 = { ++ .variant = H6_EMAC, ++}; ++ + static const struct udevice_id sun8i_emac_eth_ids[] = { +- {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC }, +- {.compatible = "allwinner,sun50i-a64-emac", +- .data = (uintptr_t)A64_EMAC }, +- {.compatible = "allwinner,sun8i-a83t-emac", +- .data = (uintptr_t)A83T_EMAC }, +- {.compatible = "allwinner,sun8i-r40-gmac", +- .data = (uintptr_t)R40_GMAC }, +- {.compatible = "allwinner,sun50i-h6-emac", +- .data = (uintptr_t)H6_EMAC }, ++ { .compatible = "allwinner,sun8i-a83t-emac", ++ .data = (ulong)&emac_variant_a83t }, ++ { .compatible = "allwinner,sun8i-h3-emac", ++ .data = (ulong)&emac_variant_h3 }, ++ { .compatible = "allwinner,sun8i-r40-gmac", ++ .data = (ulong)&emac_variant_r40 }, ++ { .compatible = "allwinner,sun50i-a64-emac", ++ .data = (ulong)&emac_variant_a64 }, ++ { .compatible = "allwinner,sun50i-h6-emac", ++ .data = (ulong)&emac_variant_h6 }, + { } + }; + +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4004-net-sun8i-emac-Add-a-flag-for-RMII-support.patch b/package/boot/uboot-sunxi/patches/4004-net-sun8i-emac-Add-a-flag-for-RMII-support.patch new file mode 100644 index 0000000000..17715b7d03 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4004-net-sun8i-emac-Add-a-flag-for-RMII-support.patch @@ -0,0 +1,77 @@ +From d9fd9f067e9bfcc03a70a0ead0bbe14595976edd Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 22 Jan 2023 16:51:03 -0600 +Subject: [PATCH 4004/4044] net: sun8i-emac: Add a flag for RMII support + +Describe this feature instead of using the SoC ID. + +Signed-off-by: Samuel Holland +Reviewed-by: Andre Przywara +Reviewed-by: Ramon Fried +--- + drivers/net/sun8i_emac.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c +index 986e565cd8..f232b8f087 100644 +--- a/drivers/net/sun8i_emac.c ++++ b/drivers/net/sun8i_emac.c +@@ -137,6 +137,7 @@ enum emac_variant_id { + + struct emac_variant { + enum emac_variant_id variant; ++ bool support_rmii; + }; + + struct emac_dma_desc { +@@ -337,9 +338,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + reg = sun8i_emac_set_syscon_ephy(priv, reg); + + reg &= ~(SC_ETCS_MASK | SC_EPIT); +- if (priv->variant->variant == H3_EMAC || +- priv->variant->variant == A64_EMAC || +- priv->variant->variant == H6_EMAC) ++ if (priv->variant->support_rmii) + reg &= ~SC_RMII_EN; + + switch (priv->interface) { +@@ -353,13 +352,10 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + reg |= SC_EPIT | SC_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: +- if (priv->variant->variant == H3_EMAC || +- priv->variant->variant == A64_EMAC || +- priv->variant->variant == H6_EMAC) { ++ if (priv->variant->support_rmii) { + reg |= SC_RMII_EN | SC_ETCS_EXT_GMII; +- break; ++ break; + } +- /* RMII not supported on A83T */ + default: + debug("%s: Invalid PHY interface\n", __func__); + return -EINVAL; +@@ -910,6 +906,7 @@ static const struct emac_variant emac_variant_a83t = { + + static const struct emac_variant emac_variant_h3 = { + .variant = H3_EMAC, ++ .support_rmii = true, + }; + + static const struct emac_variant emac_variant_r40 = { +@@ -918,10 +915,12 @@ static const struct emac_variant emac_variant_r40 = { + + static const struct emac_variant emac_variant_a64 = { + .variant = A64_EMAC, ++ .support_rmii = true, + }; + + static const struct emac_variant emac_variant_h6 = { + .variant = H6_EMAC, ++ .support_rmii = true, + }; + + static const struct udevice_id sun8i_emac_eth_ids[] = { +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4004-pinctrl-sunxi-add-GPIO-in-out-wrappers.patch b/package/boot/uboot-sunxi/patches/4004-pinctrl-sunxi-add-GPIO-in-out-wrappers.patch deleted file mode 100644 index 872ac623fb..0000000000 --- a/package/boot/uboot-sunxi/patches/4004-pinctrl-sunxi-add-GPIO-in-out-wrappers.patch +++ /dev/null @@ -1,120 +0,0 @@ -From be773ad59da355ca608287db4c4771bf9120241c Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Tue, 6 Sep 2022 10:07:18 +0100 -Subject: [PATCH 4004/4031] pinctrl: sunxi: add GPIO in/out wrappers - -So far we were open-coding the pincontroller's GPIO output/input access -in each function using that. - -Provide two functions that wrap that nicely, so users don't need to know -about the internals, and we can abstract the new D1 pinctrl more easily. - -Signed-off-by: Andre Przywara ---- - arch/arm/include/asm/arch-sunxi/gpio.h | 2 ++ - arch/arm/mach-sunxi/pinmux.c | 10 ++++++++++ - drivers/gpio/sunxi_gpio.c | 26 +++++--------------------- - 3 files changed, 17 insertions(+), 21 deletions(-) - -diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h -index 8333810a69..42ca03d8c1 100644 ---- a/arch/arm/include/asm/arch-sunxi/gpio.h -+++ b/arch/arm/include/asm/arch-sunxi/gpio.h -@@ -211,6 +211,8 @@ void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val); - void sunxi_gpio_set_cfgpin(u32 pin, u32 val); - int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset); - int sunxi_gpio_get_cfgpin(u32 pin); -+void sunxi_gpio_set_output_bank(void *bank_base, u32 clear_mask, u32 set_mask); -+u32 sunxi_gpio_get_output_bank(void *bank_base); - void sunxi_gpio_set_drv(u32 pin, u32 val); - void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val); - void sunxi_gpio_set_pull(u32 pin, u32 val); -diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c -index b650f6b1ae..91acbf9269 100644 ---- a/arch/arm/mach-sunxi/pinmux.c -+++ b/arch/arm/mach-sunxi/pinmux.c -@@ -46,6 +46,16 @@ int sunxi_gpio_get_cfgpin(u32 pin) - return sunxi_gpio_get_cfgbank(bank_base, pin % 32); - } - -+void sunxi_gpio_set_output_bank(void *bank_base, u32 clear_mask, u32 set_mask) -+{ -+ clrsetbits_le32(bank_base + GPIO_DAT_REG_OFFSET, clear_mask, set_mask); -+} -+ -+u32 sunxi_gpio_get_output_bank(void *bank_base) -+{ -+ return readl(bank_base + GPIO_DAT_REG_OFFSET); -+} -+ - void sunxi_gpio_set_drv(u32 pin, u32 val) - { - u32 bank = GPIO_BANK(pin); -diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c -index 1bf691a204..767996c10f 100644 ---- a/drivers/gpio/sunxi_gpio.c -+++ b/drivers/gpio/sunxi_gpio.c -@@ -21,33 +21,22 @@ - #if !CONFIG_IS_ENABLED(DM_GPIO) - static int sunxi_gpio_output(u32 pin, u32 val) - { -- u32 dat; - u32 bank = GPIO_BANK(pin); - u32 num = GPIO_NUM(pin); - void *pio = BANK_TO_GPIO(bank); - -- dat = readl(pio + 0x10); -- if (val) -- dat |= 0x1 << num; -- else -- dat &= ~(0x1 << num); -- -- writel(dat, pio + 0x10); -- -+ sunxi_gpio_set_output_bank(pio, val ? 0 : 1U << num, -+ val ? 1U << num : 0); - return 0; - } - - static int sunxi_gpio_input(u32 pin) - { -- u32 dat; - u32 bank = GPIO_BANK(pin); - u32 num = GPIO_NUM(pin); - void *pio = BANK_TO_GPIO(bank); - -- dat = readl(pio + 0x10); -- dat >>= num; -- -- return dat & 0x1; -+ return (sunxi_gpio_get_output_bank(pio) >> num) & 0x1; - } - - int gpio_request(unsigned gpio, const char *label) -@@ -136,12 +125,8 @@ static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) - { - struct sunxi_gpio_plat *plat = dev_get_plat(dev); - u32 num = GPIO_NUM(offset); -- unsigned dat; -- -- dat = readl(plat->regs + GPIO_DAT_REG_OFFSET); -- dat >>= num; - -- return dat & 0x1; -+ return (sunxi_gpio_get_output_bank(plat->regs) >> num) & 0x1; - } - - static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset) -@@ -181,8 +166,7 @@ static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset, - u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE); - u32 num = GPIO_NUM(offset); - -- clrsetbits_le32(plat->regs + GPIO_DAT_REG_OFFSET, -- 1 << num, value << num); -+ sunxi_gpio_set_output_bank(plat->regs, 1U << num, value << num); - sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); - } else if (flags & GPIOD_IS_IN) { - u32 pull = 0; --- -2.20.1 - diff --git a/package/boot/uboot-sunxi/patches/4005-net-sun8i-emac-Add-a-flag-for-the-internal-PHY-switc.patch b/package/boot/uboot-sunxi/patches/4005-net-sun8i-emac-Add-a-flag-for-the-internal-PHY-switc.patch new file mode 100644 index 0000000000..455eccff39 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4005-net-sun8i-emac-Add-a-flag-for-the-internal-PHY-switc.patch @@ -0,0 +1,47 @@ +From 0b22263387bb55c70fb774ea70dd386bf6228c97 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 22 Jan 2023 16:51:04 -0600 +Subject: [PATCH 4005/4044] net: sun8i-emac: Add a flag for the internal PHY + switch + +Describe this feature instead of using the SoC ID. + +Signed-off-by: Samuel Holland +Reviewed-by: Andre Przywara +Reviewed-by: Ramon Fried +--- + drivers/net/sun8i_emac.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c +index f232b8f087..36cc2498b5 100644 +--- a/drivers/net/sun8i_emac.c ++++ b/drivers/net/sun8i_emac.c +@@ -137,6 +137,7 @@ enum emac_variant_id { + + struct emac_variant { + enum emac_variant_id variant; ++ bool soc_has_internal_phy; + bool support_rmii; + }; + +@@ -860,7 +861,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) + return -EINVAL; + +- if (priv->variant->variant == H3_EMAC) { ++ if (priv->variant->soc_has_internal_phy) { + ret = sun8i_handle_internal_phy(dev, priv); + if (ret) + return ret; +@@ -906,6 +907,7 @@ static const struct emac_variant emac_variant_a83t = { + + static const struct emac_variant emac_variant_h3 = { + .variant = H3_EMAC, ++ .soc_has_internal_phy = true, + .support_rmii = true, + }; + +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4006-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch b/package/boot/uboot-sunxi/patches/4006-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch new file mode 100644 index 0000000000..f98c35c87a --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4006-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch @@ -0,0 +1,133 @@ +From e2305bd1beef8597351e6036c7c1597c6cd5ca0d Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 22 Jan 2023 16:51:05 -0600 +Subject: [PATCH 4006/4044] net: sun8i-emac: Use common syscon setup for R40 + +While R40 puts the EMAC syscon register at a different address from +other variants, the relevant portion of the register's layout is the +same. Factor out the register offset so the same code can be shared +by all variants. This matches what the Linux driver does. + +This change provides two benefits beyond the simplification: + - R40 boards now respect the RX delays from the devicetree + - This resolves a warning on architectures where readl/writel + expect the address to have a pointer type, not phys_addr_t. + +Signed-off-by: Samuel Holland +Reviewed-by: Andre Przywara +Reviewed-by: Ramon Fried +--- + drivers/net/sun8i_emac.c | 32 +++++++++++++++----------------- + 1 file changed, 15 insertions(+), 17 deletions(-) + +diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c +index 36cc2498b5..231aac19e3 100644 +--- a/drivers/net/sun8i_emac.c ++++ b/drivers/net/sun8i_emac.c +@@ -137,6 +137,7 @@ enum emac_variant_id { + + struct emac_variant { + enum emac_variant_id variant; ++ uint syscon_offset; + bool soc_has_internal_phy; + bool support_rmii; + }; +@@ -168,7 +169,7 @@ struct emac_eth_dev { + + const struct emac_variant *variant; + void *mac_reg; +- phys_addr_t sysctl_reg; ++ void *sysctl_reg; + struct phy_device *phydev; + struct mii_dev *bus; + struct clk tx_clk; +@@ -323,18 +324,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + { + u32 reg; + +- if (priv->variant->variant == R40_GMAC) { +- /* Select RGMII for R40 */ +- reg = readl(priv->sysctl_reg + 0x164); +- reg |= SC_ETCS_INT_GMII | +- SC_EPIT | +- (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET); +- +- writel(reg, priv->sysctl_reg + 0x164); +- return 0; +- } +- +- reg = readl(priv->sysctl_reg + 0x30); ++ reg = readl(priv->sysctl_reg); + + reg = sun8i_emac_set_syscon_ephy(priv, reg); + +@@ -370,7 +360,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET) + & SC_ERXDC_MASK; + +- writel(reg, priv->sysctl_reg + 0x30); ++ writel(reg, priv->sysctl_reg); + + return 0; + } +@@ -793,6 +783,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev); + struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; + struct emac_eth_dev *priv = dev_get_priv(dev); ++ phys_addr_t syscon_base; + const fdt32_t *reg; + int node = dev_of_offset(dev); + int offset = 0; +@@ -838,13 +829,15 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + __func__); + return -EINVAL; + } +- priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, +- offset, reg); +- if (priv->sysctl_reg == FDT_ADDR_T_NONE) { ++ ++ syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg); ++ if (syscon_base == FDT_ADDR_T_NONE) { + debug("%s: Cannot find syscon base address\n", __func__); + return -EINVAL; + } + ++ priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset; ++ + pdata->phy_interface = -1; + priv->phyaddr = -1; + priv->use_internal_phy = false; +@@ -903,25 +896,30 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + + static const struct emac_variant emac_variant_a83t = { + .variant = A83T_EMAC, ++ .syscon_offset = 0x30, + }; + + static const struct emac_variant emac_variant_h3 = { + .variant = H3_EMAC, ++ .syscon_offset = 0x30, + .soc_has_internal_phy = true, + .support_rmii = true, + }; + + static const struct emac_variant emac_variant_r40 = { + .variant = R40_GMAC, ++ .syscon_offset = 0x164, + }; + + static const struct emac_variant emac_variant_a64 = { + .variant = A64_EMAC, ++ .syscon_offset = 0x30, + .support_rmii = true, + }; + + static const struct emac_variant emac_variant_h6 = { + .variant = H6_EMAC, ++ .syscon_offset = 0x30, + .support_rmii = true, + }; + +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4007-net-sun8i-emac-Remove-the-SoC-variant-ID.patch b/package/boot/uboot-sunxi/patches/4007-net-sun8i-emac-Remove-the-SoC-variant-ID.patch new file mode 100644 index 0000000000..1b63599853 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4007-net-sun8i-emac-Remove-the-SoC-variant-ID.patch @@ -0,0 +1,70 @@ +From 3cfbf01d126f127aa812102f9c42f9787748cc21 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 22 Jan 2023 16:51:06 -0600 +Subject: [PATCH 4007/4044] net: sun8i-emac: Remove the SoC variant ID + +Now that all differences in functionality are covered by individual +flags, remove the enumeration of SoC variants. + +Signed-off-by: Samuel Holland +Reviewed-by: Andre Przywara +Reviewed-by: Ramon Fried +--- + drivers/net/sun8i_emac.c | 14 -------------- + 1 file changed, 14 deletions(-) + +diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c +index 231aac19e3..04c3274fbe 100644 +--- a/drivers/net/sun8i_emac.c ++++ b/drivers/net/sun8i_emac.c +@@ -127,16 +127,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + +-enum emac_variant_id { +- A83T_EMAC = 1, +- H3_EMAC, +- A64_EMAC, +- R40_GMAC, +- H6_EMAC, +-}; +- + struct emac_variant { +- enum emac_variant_id variant; + uint syscon_offset; + bool soc_has_internal_phy; + bool support_rmii; +@@ -895,30 +886,25 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + } + + static const struct emac_variant emac_variant_a83t = { +- .variant = A83T_EMAC, + .syscon_offset = 0x30, + }; + + static const struct emac_variant emac_variant_h3 = { +- .variant = H3_EMAC, + .syscon_offset = 0x30, + .soc_has_internal_phy = true, + .support_rmii = true, + }; + + static const struct emac_variant emac_variant_r40 = { +- .variant = R40_GMAC, + .syscon_offset = 0x164, + }; + + static const struct emac_variant emac_variant_a64 = { +- .variant = A64_EMAC, + .syscon_offset = 0x30, + .support_rmii = true, + }; + + static const struct emac_variant emac_variant_h6 = { +- .variant = H6_EMAC, + .syscon_offset = 0x30, + .support_rmii = true, + }; +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4002-sunxi-remove-CONFIG_MACPWR.patch b/package/boot/uboot-sunxi/patches/4008-sunxi-remove-CONFIG_MACPWR.patch similarity index 86% rename from package/boot/uboot-sunxi/patches/4002-sunxi-remove-CONFIG_MACPWR.patch rename to package/boot/uboot-sunxi/patches/4008-sunxi-remove-CONFIG_MACPWR.patch index a58f69e48f..a0b4090382 100644 --- a/package/boot/uboot-sunxi/patches/4002-sunxi-remove-CONFIG_MACPWR.patch +++ b/package/boot/uboot-sunxi/patches/4008-sunxi-remove-CONFIG_MACPWR.patch @@ -1,7 +1,7 @@ -From 9c399ed4ff3e2eb5a4e051be211e9da1fe9c27cb Mon Sep 17 00:00:00 2001 +From 0f7241f68bd8dc76665a050b4012e5882e7badaa Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Wed, 8 Jun 2022 14:56:56 +0100 -Subject: [PATCH 4002/4031] sunxi: remove CONFIG_MACPWR +Date: Fri, 21 Jul 2023 14:45:48 +0100 +Subject: [PATCH 4008/4044] sunxi: remove CONFIG_MACPWR The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). @@ -17,6 +17,7 @@ This allows us to remove the MACPWR Kconfig definition and the respective values from the defconfigs. Signed-off-by: Andre Przywara +Reviewed-by: Sam Edwards --- arch/arm/mach-sunxi/Kconfig | 7 ------- board/sunxi/board.c | 12 +----------- @@ -39,12 +40,10 @@ Signed-off-by: Andre Przywara configs/orangepi_pc2_defconfig | 1 - configs/orangepi_plus2e_defconfig | 1 - configs/orangepi_plus_defconfig | 1 - - configs/orangepi_win_defconfig | 1 - configs/pine_h64_defconfig | 1 - configs/zeropi_defconfig | 1 - drivers/net/sun8i_emac.c | 9 +++++++-- - drivers/net/sunxi_emac.c | 8 ++++++++ - 26 files changed, 16 insertions(+), 42 deletions(-) + 24 files changed, 8 insertions(+), 41 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index c78a553493..d716054f72 100644 @@ -329,18 +328,6 @@ index ed585881d4..092ce77a6c 100644 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig -index 3b78ad7e52..bf52d1ea6b 100644 ---- a/configs/orangepi_win_defconfig -+++ b/configs/orangepi_win_defconfig -@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" - CONFIG_SPL=y - CONFIG_MACH_SUN50I=y - CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y --CONFIG_MACPWR="PD14" - CONFIG_SPL_SPI_SUNXI=y - # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set - CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 6dac6098d0..4712b8e469 100644 --- a/configs/pine_h64_defconfig @@ -366,7 +353,7 @@ index 11f3715e6d..7901bffd15 100644 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c -index e800a326b8..0937ec3c86 100644 +index 04c3274fbe..7b60a60ad5 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -29,6 +29,7 @@ @@ -377,7 +364,7 @@ index e800a326b8..0937ec3c86 100644 #define MDIO_CMD_MII_BUSY BIT(0) #define MDIO_CMD_MII_WRITE BIT(1) -@@ -169,9 +170,8 @@ struct emac_eth_dev { +@@ -167,9 +168,8 @@ struct emac_eth_dev { struct clk ephy_clk; struct reset_ctl tx_rst; struct reset_ctl ephy_rst; @@ -388,7 +375,7 @@ index e800a326b8..0937ec3c86 100644 }; -@@ -738,6 +738,9 @@ static int sun8i_emac_eth_probe(struct udevice *dev) +@@ -720,6 +720,9 @@ static int sun8i_emac_eth_probe(struct udevice *dev) sun8i_emac_set_syscon(sun8i_pdata, priv); @@ -398,58 +385,15 @@ index e800a326b8..0937ec3c86 100644 sun8i_mdio_init(dev->name, dev); priv->bus = miiphy_get_dev_by_name(dev->name); -@@ -844,6 +847,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) - return -EINVAL; - } +@@ -829,6 +832,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) + + priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset; + device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg); + pdata->phy_interface = -1; priv->phyaddr = -1; priv->use_internal_phy = false; -diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c -index ad9e1abd16..ee8b8a1667 100644 ---- a/drivers/net/sunxi_emac.c -+++ b/drivers/net/sunxi_emac.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - - /* EMAC register */ - struct emac_regs { -@@ -165,6 +166,7 @@ struct emac_eth_dev { - struct phy_device *phydev; - int link_printed; - uchar rx_buf[EMAC_RX_BUFSIZE]; -+ struct udevice *phy_reg; - }; - - struct emac_rxhdr { -@@ -573,6 +575,9 @@ static int sunxi_emac_eth_probe(struct udevice *dev) - if (ret) - return ret; - -+ if (priv->phy_reg) -+ regulator_set_enable(priv->phy_reg, true); -+ - return sunxi_emac_init_phy(priv, dev); - } - -@@ -586,9 +591,12 @@ static const struct eth_ops sunxi_emac_eth_ops = { - static int sunxi_emac_eth_of_to_plat(struct udevice *dev) - { - struct eth_pdata *pdata = dev_get_plat(dev); -+ struct emac_eth_dev *priv = dev_get_priv(dev); - - pdata->iobase = dev_read_addr(dev); - -+ device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg); -+ - return 0; - } - -- 2.20.1 diff --git a/package/boot/uboot-sunxi/patches/4009-pinctrl-sunxi-add-GPIO-in-out-wrappers.patch b/package/boot/uboot-sunxi/patches/4009-pinctrl-sunxi-add-GPIO-in-out-wrappers.patch new file mode 100644 index 0000000000..98c80df21c --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4009-pinctrl-sunxi-add-GPIO-in-out-wrappers.patch @@ -0,0 +1,169 @@ +From 83871970cde779ab23107aa46cc840afd435314e Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Fri, 21 Jul 2023 14:45:49 +0100 +Subject: [PATCH 4009/4044] pinctrl: sunxi: add GPIO in/out wrappers + +So far we were open-coding the pincontroller's GPIO output/input access +in each function using that. + +Provide functions that wrap that nicely, and follow the existing pattern +(set/get_{bank,}), so users don't need to know about the internals, and +we can abstract the new D1 pinctrl more easily. + +Signed-off-by: Andre Przywara +Reviewed-by: Sam Edwards +Tested-by: Sam Edwards +--- + arch/arm/include/asm/arch-sunxi/gpio.h | 4 +++ + arch/arm/mach-sunxi/pinmux.c | 28 +++++++++++++++ + drivers/gpio/sunxi_gpio.c | 49 +++++--------------------- + 3 files changed, 40 insertions(+), 41 deletions(-) + +diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h +index 437e86479c..2e7c84e410 100644 +--- a/arch/arm/include/asm/arch-sunxi/gpio.h ++++ b/arch/arm/include/asm/arch-sunxi/gpio.h +@@ -222,6 +222,10 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); + void sunxi_gpio_set_cfgpin(u32 pin, u32 val); + int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); + int sunxi_gpio_get_cfgpin(u32 pin); ++void sunxi_gpio_set_output_bank(struct sunxi_gpio *pio, int pin, bool set); ++void sunxi_gpio_set_output(u32 pin, bool set); ++int sunxi_gpio_get_output_bank(struct sunxi_gpio *pio, int pin); ++int sunxi_gpio_get_output(u32 pin); + void sunxi_gpio_set_drv(u32 pin, u32 val); + void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); + void sunxi_gpio_set_pull(u32 pin, u32 val); +diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c +index c95fcee9f6..751cac8e09 100644 +--- a/arch/arm/mach-sunxi/pinmux.c ++++ b/arch/arm/mach-sunxi/pinmux.c +@@ -45,6 +45,34 @@ int sunxi_gpio_get_cfgpin(u32 pin) + return sunxi_gpio_get_cfgbank(pio, pin); + } + ++void sunxi_gpio_set_output_bank(struct sunxi_gpio *pio, int pin, bool set) ++{ ++ u32 mask = 1U << GPIO_NUM(pin); ++ ++ clrsetbits_le32(&pio->dat, set ? 0 : mask, set ? mask : 0); ++} ++ ++void sunxi_gpio_set_output(u32 pin, bool set) ++{ ++ u32 bank = GPIO_BANK(pin); ++ struct sunxi_gpio *pio = BANK_TO_GPIO(bank); ++ ++ sunxi_gpio_set_output_bank(pio, pin, set); ++} ++ ++int sunxi_gpio_get_output_bank(struct sunxi_gpio *pio, int pin) ++{ ++ return !!(readl(&pio->dat) & (1U << GPIO_NUM(pin))); ++} ++ ++int sunxi_gpio_get_output(u32 pin) ++{ ++ u32 bank = GPIO_BANK(pin); ++ struct sunxi_gpio *pio = BANK_TO_GPIO(bank); ++ ++ return sunxi_gpio_get_output_bank(pio, pin); ++} ++ + void sunxi_gpio_set_drv(u32 pin, u32 val) + { + u32 bank = GPIO_BANK(pin); +diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c +index 1e85db179a..6796375d35 100644 +--- a/drivers/gpio/sunxi_gpio.c ++++ b/drivers/gpio/sunxi_gpio.c +@@ -19,37 +19,6 @@ + #include + + #if !CONFIG_IS_ENABLED(DM_GPIO) +-static int sunxi_gpio_output(u32 pin, u32 val) +-{ +- u32 dat; +- u32 bank = GPIO_BANK(pin); +- u32 num = GPIO_NUM(pin); +- struct sunxi_gpio *pio = BANK_TO_GPIO(bank); +- +- dat = readl(&pio->dat); +- if (val) +- dat |= 0x1 << num; +- else +- dat &= ~(0x1 << num); +- +- writel(dat, &pio->dat); +- +- return 0; +-} +- +-static int sunxi_gpio_input(u32 pin) +-{ +- u32 dat; +- u32 bank = GPIO_BANK(pin); +- u32 num = GPIO_NUM(pin); +- struct sunxi_gpio *pio = BANK_TO_GPIO(bank); +- +- dat = readl(&pio->dat); +- dat >>= num; +- +- return dat & 0x1; +-} +- + int gpio_request(unsigned gpio, const char *label) + { + return 0; +@@ -70,18 +39,21 @@ int gpio_direction_input(unsigned gpio) + int gpio_direction_output(unsigned gpio, int value) + { + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT); ++ sunxi_gpio_set_output(gpio, value); + +- return sunxi_gpio_output(gpio, value); ++ return 0; + } + + int gpio_get_value(unsigned gpio) + { +- return sunxi_gpio_input(gpio); ++ return sunxi_gpio_get_output(gpio); + } + + int gpio_set_value(unsigned gpio, int value) + { +- return sunxi_gpio_output(gpio, value); ++ sunxi_gpio_set_output(gpio, value); ++ ++ return 0; + } + + int sunxi_name_to_gpio(const char *name) +@@ -135,13 +107,8 @@ int sunxi_name_to_gpio(const char *name) + static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) + { + struct sunxi_gpio_plat *plat = dev_get_plat(dev); +- u32 num = GPIO_NUM(offset); +- unsigned dat; +- +- dat = readl(&plat->regs->dat); +- dat >>= num; + +- return dat & 0x1; ++ return sunxi_gpio_get_output_bank(plat->regs, offset) & 0x1; + } + + static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset) +@@ -181,7 +148,7 @@ static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset, + u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE); + u32 num = GPIO_NUM(offset); + +- clrsetbits_le32(&plat->regs->dat, 1 << num, value << num); ++ sunxi_gpio_set_output_bank(plat->regs, num, value); + sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); + } else if (flags & GPIOD_IS_IN) { + u32 pull = 0; +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4003-pinctrl-sunxi-remove-struct-sunxi_gpio.patch b/package/boot/uboot-sunxi/patches/4010-pinctrl-sunxi-remove-struct-sunxi_gpio.patch similarity index 84% rename from package/boot/uboot-sunxi/patches/4003-pinctrl-sunxi-remove-struct-sunxi_gpio.patch rename to package/boot/uboot-sunxi/patches/4010-pinctrl-sunxi-remove-struct-sunxi_gpio.patch index e9623c95d4..8348acef7f 100644 --- a/package/boot/uboot-sunxi/patches/4003-pinctrl-sunxi-remove-struct-sunxi_gpio.patch +++ b/package/boot/uboot-sunxi/patches/4010-pinctrl-sunxi-remove-struct-sunxi_gpio.patch @@ -1,7 +1,7 @@ -From 32d2c051ef1568445a5a27b1d2d5ffe6a9483ef3 Mon Sep 17 00:00:00 2001 +From d795f4442b8c044346c0a7d7acf99481f5bbc45f Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Mon, 5 Sep 2022 18:12:39 +0100 -Subject: [PATCH 4003/4031] pinctrl: sunxi: remove struct sunxi_gpio +Date: Fri, 21 Jul 2023 14:45:50 +0100 +Subject: [PATCH 4010/4044] pinctrl: sunxi: remove struct sunxi_gpio So far every Allwinner SoC used the same basic pincontroller/GPIO register frame, and just differed by the number of implemented banks and @@ -23,14 +23,13 @@ this point, it just prepares the stages for the D1 and friends. Signed-off-by: Andre Przywara --- - arch/arm/include/asm/arch-sunxi/gpio.h | 63 +++++++++++--------------- - arch/arm/mach-sunxi/pinmux.c | 51 +++++++++++---------- - drivers/gpio/sunxi_gpio.c | 15 +++--- + arch/arm/include/asm/arch-sunxi/gpio.h | 67 +++++++++++--------------- + arch/arm/mach-sunxi/pinmux.c | 66 +++++++++++++------------ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 14 +++--- - 4 files changed, 68 insertions(+), 75 deletions(-) + 3 files changed, 71 insertions(+), 76 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h -index 437e86479c..8333810a69 100644 +index 2e7c84e410..96a29aa023 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -28,13 +28,6 @@ @@ -115,7 +114,7 @@ index 437e86479c..8333810a69 100644 /* GPIO bank sizes */ #define SUNXI_GPIOS_PER_BANK 32 -@@ -214,18 +203,18 @@ enum sunxi_gpio_number { +@@ -214,22 +203,22 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_AXP0_GPIO_COUNT 6 struct sunxi_gpio_plat { @@ -130,6 +129,12 @@ index 437e86479c..8333810a69 100644 -int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); +int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset); int sunxi_gpio_get_cfgpin(u32 pin); +-void sunxi_gpio_set_output_bank(struct sunxi_gpio *pio, int pin, bool set); ++void sunxi_gpio_set_output_bank(void *bank_base, int pin, bool set); + void sunxi_gpio_set_output(u32 pin, bool set); +-int sunxi_gpio_get_output_bank(struct sunxi_gpio *pio, int pin); ++int sunxi_gpio_get_output_bank(void *bank_base, int pin); + int sunxi_gpio_get_output(u32 pin); void sunxi_gpio_set_drv(u32 pin, u32 val); -void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); +void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val); @@ -140,7 +145,7 @@ index 437e86479c..8333810a69 100644 #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c -index c95fcee9f6..b650f6b1ae 100644 +index 751cac8e09..17d1a7bdb9 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/arch/arm/mach-sunxi/pinmux.c @@ -9,29 +9,30 @@ @@ -184,7 +189,7 @@ index c95fcee9f6..b650f6b1ae 100644 cfg >>= offset; return cfg & 0xf; -@@ -40,39 +41,41 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) +@@ -40,35 +41,38 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) int sunxi_gpio_get_cfgpin(u32 pin) { u32 bank = GPIO_BANK(pin); @@ -195,6 +200,43 @@ index c95fcee9f6..b650f6b1ae 100644 + return sunxi_gpio_get_cfgbank(bank_base, pin % 32); } +-void sunxi_gpio_set_output_bank(struct sunxi_gpio *pio, int pin, bool set) ++void sunxi_gpio_set_output_bank(void *bank_base, int pin, bool set) + { + u32 mask = 1U << GPIO_NUM(pin); + +- clrsetbits_le32(&pio->dat, set ? 0 : mask, set ? mask : 0); ++ clrsetbits_le32(bank_base + GPIO_DAT_REG_OFFSET, ++ set ? 0 : mask, set ? mask : 0); + } + + void sunxi_gpio_set_output(u32 pin, bool set) + { + u32 bank = GPIO_BANK(pin); +- struct sunxi_gpio *pio = BANK_TO_GPIO(bank); ++ void *pio = BANK_TO_GPIO(bank); + + sunxi_gpio_set_output_bank(pio, pin, set); + } + +-int sunxi_gpio_get_output_bank(struct sunxi_gpio *pio, int pin) ++int sunxi_gpio_get_output_bank(void *bank_base, int pin) + { +- return !!(readl(&pio->dat) & (1U << GPIO_NUM(pin))); ++ u32 mask = 1U << GPIO_NUM(pin); ++ ++ return !!(readl(bank_base + GPIO_DAT_REG_OFFSET) & mask); + } + + int sunxi_gpio_get_output(u32 pin) + { + u32 bank = GPIO_BANK(pin); +- struct sunxi_gpio *pio = BANK_TO_GPIO(bank); ++ void *pio = BANK_TO_GPIO(bank); + + return sunxi_gpio_get_output_bank(pio, pin); + } +@@ -76,31 +80,33 @@ int sunxi_gpio_get_output(u32 pin) void sunxi_gpio_set_drv(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); @@ -240,60 +282,6 @@ index c95fcee9f6..b650f6b1ae 100644 + clrsetbits_le32(bank_base + GPIO_PULL_REG_OFFSET + index * 4, + 0x3U << offset, val << offset); } -diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c -index 1e85db179a..1bf691a204 100644 ---- a/drivers/gpio/sunxi_gpio.c -+++ b/drivers/gpio/sunxi_gpio.c -@@ -24,15 +24,15 @@ static int sunxi_gpio_output(u32 pin, u32 val) - u32 dat; - u32 bank = GPIO_BANK(pin); - u32 num = GPIO_NUM(pin); -- struct sunxi_gpio *pio = BANK_TO_GPIO(bank); -+ void *pio = BANK_TO_GPIO(bank); - -- dat = readl(&pio->dat); -+ dat = readl(pio + 0x10); - if (val) - dat |= 0x1 << num; - else - dat &= ~(0x1 << num); - -- writel(dat, &pio->dat); -+ writel(dat, pio + 0x10); - - return 0; - } -@@ -42,9 +42,9 @@ static int sunxi_gpio_input(u32 pin) - u32 dat; - u32 bank = GPIO_BANK(pin); - u32 num = GPIO_NUM(pin); -- struct sunxi_gpio *pio = BANK_TO_GPIO(bank); -+ void *pio = BANK_TO_GPIO(bank); - -- dat = readl(&pio->dat); -+ dat = readl(pio + 0x10); - dat >>= num; - - return dat & 0x1; -@@ -138,7 +138,7 @@ static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) - u32 num = GPIO_NUM(offset); - unsigned dat; - -- dat = readl(&plat->regs->dat); -+ dat = readl(plat->regs + GPIO_DAT_REG_OFFSET); - dat >>= num; - - return dat & 0x1; -@@ -181,7 +181,8 @@ static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset, - u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE); - u32 num = GPIO_NUM(offset); - -- clrsetbits_le32(&plat->regs->dat, 1 << num, value << num); -+ clrsetbits_le32(plat->regs + GPIO_DAT_REG_OFFSET, -+ 1 << num, value << num); - sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); - } else if (flags & GPIOD_IS_IN) { - u32 pull = 0; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index c4fbda7a92..b0144edcf4 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c diff --git a/package/boot/uboot-sunxi/patches/4005-pinctrl-sunxi-move-pinctrl-code-and-remove-GPIO_EXTR.patch b/package/boot/uboot-sunxi/patches/4011-pinctrl-sunxi-move-pinctrl-code-and-remove-GPIO_EXTR.patch similarity index 96% rename from package/boot/uboot-sunxi/patches/4005-pinctrl-sunxi-move-pinctrl-code-and-remove-GPIO_EXTR.patch rename to package/boot/uboot-sunxi/patches/4011-pinctrl-sunxi-move-pinctrl-code-and-remove-GPIO_EXTR.patch index 54b975fa25..02ae69a439 100644 --- a/package/boot/uboot-sunxi/patches/4005-pinctrl-sunxi-move-pinctrl-code-and-remove-GPIO_EXTR.patch +++ b/package/boot/uboot-sunxi/patches/4011-pinctrl-sunxi-move-pinctrl-code-and-remove-GPIO_EXTR.patch @@ -1,7 +1,7 @@ -From 3e291cf021a0fd248c4a4d86e8bb2b65ca1b0f5c Mon Sep 17 00:00:00 2001 +From 0fe6de16aa4a6164cd46ec5f8993bc058567fdd1 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Tue, 6 Sep 2022 10:36:38 +0100 -Subject: [PATCH 4005/4031] pinctrl: sunxi: move pinctrl code and remove +Date: Fri, 21 Jul 2023 14:45:51 +0100 +Subject: [PATCH 4011/4044] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code @@ -43,7 +43,7 @@ Signed-off-by: Andre Przywara drivers/video/sunxi/sunxi_lcd.c | 1 + .../include/asm/arch-sunxi/gpio.h => include/sunxi_gpio.h | 0 20 files changed, 19 insertions(+), 8 deletions(-) - rename arch/arm/mach-sunxi/pinmux.c => board/sunxi/pinctrl.c (93%) + rename arch/arm/mach-sunxi/pinmux.c => board/sunxi/pinctrl.c (94%) rename arch/arm/include/asm/arch-sunxi/gpio.h => include/sunxi_gpio.h (100%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig @@ -148,10 +148,10 @@ index cde04bebe9..eeee6319e7 100644 #include diff --git a/arch/arm/mach-sunxi/pinmux.c b/board/sunxi/pinctrl.c -similarity index 93% +similarity index 94% rename from arch/arm/mach-sunxi/pinmux.c rename to board/sunxi/pinctrl.c -index 91acbf9269..aac37f639b 100644 +index 17d1a7bdb9..494d92c73b 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/board/sunxi/pinctrl.c @@ -3,11 +3,14 @@ @@ -183,7 +183,7 @@ index 35585dc8ac..14a99ce4c9 100644 static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val); diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c -index 767996c10f..49a6be6fd0 100644 +index 6796375d35..921cf43b25 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -17,6 +17,7 @@ @@ -193,7 +193,7 @@ index 767996c10f..49a6be6fd0 100644 +#include #if !CONFIG_IS_ENABLED(DM_GPIO) - static int sunxi_gpio_output(u32 pin, u32 val) + int gpio_request(unsigned gpio, const char *label) diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c index d221323295..b8e07a533c 100644 --- a/drivers/i2c/sun6i_p2wi.c diff --git a/package/boot/uboot-sunxi/patches/4006-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch b/package/boot/uboot-sunxi/patches/4012-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch similarity index 95% rename from package/boot/uboot-sunxi/patches/4006-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch rename to package/boot/uboot-sunxi/patches/4012-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch index ee932a7d02..dac9772c2f 100644 --- a/package/boot/uboot-sunxi/patches/4006-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch +++ b/package/boot/uboot-sunxi/patches/4012-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch @@ -1,7 +1,7 @@ -From 69c0dbc968700d57189fd19e082f0f8a4b1df878 Mon Sep 17 00:00:00 2001 +From 9dfef76a7374b5da636a50d2a439cb1da0c43421 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Tue, 6 Sep 2022 11:50:54 +0100 -Subject: [PATCH 4006/4031] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h +Date: Fri, 21 Jul 2023 14:45:52 +0100 +Subject: [PATCH 4012/4044] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h On the Allwinner platform we were describing a quite comprehensive memory map in a per-SoC header unser arch/arm. @@ -86,7 +86,7 @@ index 9c2d11b590..20025be231 100644 /* Misc. */ diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h -index 42ca03d8c1..5ac476f960 100644 +index 96a29aa023..2e06745a1c 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -9,7 +9,17 @@ diff --git a/package/boot/uboot-sunxi/patches/4007-pinctrl-sunxi-add-new-D1-pinctrl-support.patch b/package/boot/uboot-sunxi/patches/4013-pinctrl-sunxi-add-new-D1-pinctrl-support.patch similarity index 90% rename from package/boot/uboot-sunxi/patches/4007-pinctrl-sunxi-add-new-D1-pinctrl-support.patch rename to package/boot/uboot-sunxi/patches/4013-pinctrl-sunxi-add-new-D1-pinctrl-support.patch index ca984cca49..42ccdbad0a 100644 --- a/package/boot/uboot-sunxi/patches/4007-pinctrl-sunxi-add-new-D1-pinctrl-support.patch +++ b/package/boot/uboot-sunxi/patches/4013-pinctrl-sunxi-add-new-D1-pinctrl-support.patch @@ -1,7 +1,7 @@ -From 20903c89595e5ad0eb5fd91eebf0a02f6843e8a6 Mon Sep 17 00:00:00 2001 +From 1a97a80f9cd80d4ba65101ceef45de7d99d5aed6 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Tue, 6 Sep 2022 12:12:50 +0100 -Subject: [PATCH 4007/4031] pinctrl: sunxi: add new D1 pinctrl support +Date: Fri, 21 Jul 2023 14:45:53 +0100 +Subject: [PATCH 4013/4044] pinctrl: sunxi: add new D1 pinctrl support For the first time since at least the Allwinner A10 SoCs, the D1 (and related cores) use a new pincontroller MMIO register layout, so we @@ -14,6 +14,8 @@ pincontrollers, and just use that to just switch some basic symbols. The rest is already abstracted enough, so works out of the box. Signed-off-by: Andre Przywara +Reviewed-by: Sam Edwards +Tested-by: Sam Edwards --- arch/arm/mach-sunxi/Kconfig | 6 ++++++ include/sunxi_gpio.h | 26 +++++++++++++++++++++----- @@ -37,7 +39,7 @@ index d716054f72..b328ce8960 100644 # not supported by Kconfig config SUNXI_GEN_SUN4I diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h -index 5ac476f960..2f8b220f75 100644 +index 2e06745a1c..61978db6db 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -68,15 +68,32 @@ diff --git a/package/boot/uboot-sunxi/patches/4008-sunxi-introduce-NCAT2-generation-model.patch b/package/boot/uboot-sunxi/patches/4014-sunxi-introduce-NCAT2-generation-model.patch similarity index 81% rename from package/boot/uboot-sunxi/patches/4008-sunxi-introduce-NCAT2-generation-model.patch rename to package/boot/uboot-sunxi/patches/4014-sunxi-introduce-NCAT2-generation-model.patch index 0efdf41a74..0528970c24 100644 --- a/package/boot/uboot-sunxi/patches/4008-sunxi-introduce-NCAT2-generation-model.patch +++ b/package/boot/uboot-sunxi/patches/4014-sunxi-introduce-NCAT2-generation-model.patch @@ -1,7 +1,7 @@ -From fccd059eaa3b1fa5873606ffbc700e300a4aec17 Mon Sep 17 00:00:00 2001 +From abdc00eee12eed6db2a5e6fb7d72aae6be1d4193 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Wed, 5 Oct 2022 17:54:19 +0100 -Subject: [PATCH 4008/4031] sunxi: introduce NCAT2 generation model +Date: Fri, 21 Jul 2023 14:45:54 +0100 +Subject: [PATCH 4014/4044] sunxi: introduce NCAT2 generation model Allwinner seems to typically stick to a common MMIO memory map for several SoCs, but from time to time does some breaking changes, which @@ -23,20 +23,23 @@ renovated clock controller). This paves the way to introduce a first user of this generation. Signed-off-by: Andre Przywara +Reviewed-by: Sam Edwards +Tested-by: Sam Edwards --- arch/arm/include/asm/arch-sunxi/clock.h | 2 +- arch/arm/include/asm/arch-sunxi/cpu.h | 2 + - .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 54 +++++++++++++++++++ + .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 43 +++++++++++++++++++ arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- arch/arm/include/asm/arch-sunxi/timer.h | 2 +- - arch/arm/mach-sunxi/Kconfig | 14 ++++- + arch/arm/mach-sunxi/Kconfig | 12 +++++- arch/arm/mach-sunxi/Makefile | 1 + - arch/arm/mach-sunxi/board.c | 4 +- + arch/arm/mach-sunxi/board.c | 22 ++++++---- common/spl/Kconfig | 2 +- - drivers/mmc/sunxi_mmc.c | 10 ++-- + drivers/i2c/mvtwsi.c | 3 +- + drivers/mmc/sunxi_mmc.c | 10 +++-- include/sunxi_gpio.h | 3 ++ - 12 files changed, 86 insertions(+), 12 deletions(-) + 13 files changed, 87 insertions(+), 19 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h @@ -67,10 +70,10 @@ index b08f202374..768c6572d6 100644 #endif diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h new file mode 100644 -index 0000000000..13093085a5 +index 0000000000..b13be2c4e8 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h -@@ -0,0 +1,54 @@ +@@ -0,0 +1,43 @@ +/* + * (C) Copyright 2022 Arm Limited + * @@ -80,26 +83,9 @@ index 0000000000..13093085a5 +#ifndef _SUNXI_CPU_SUNXI_NCAT2_H +#define _SUNXI_CPU_SUNXI_NCAT2_H + -+#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS -+#define SUNXI_SRAM_C_BASE 0x00028000 -+#define SUNXI_SRAM_A2_BASE 0x00100000 -+ -+#define SUNXI_SRAMC_BASE 0x02800000 +#define SUNXI_CCM_BASE 0x02001000 -+/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ -+#define SUNXI_SIDC_BASE 0x03006000 -+#define SUNXI_SID_BASE 0x03006200 +#define SUNXI_TIMER_BASE 0x02050000 + -+#ifdef CONFIG_MACH_SUN50I_H6 -+#define SUNXI_DRAM_COM_BASE 0x04002000 -+#define SUNXI_DRAM_CTL0_BASE 0x04003000 -+#define SUNXI_DRAM_PHY0_BASE 0x04005000 -+#endif -+#define SUNXI_MMC0_BASE 0x04020000 -+#define SUNXI_MMC1_BASE 0x04021000 -+#define SUNXI_MMC2_BASE 0x04022000 -+ +#define SUNXI_UART0_BASE 0x02500000 +#define SUNXI_UART1_BASE 0x02500400 +#define SUNXI_UART2_BASE 0x02500800 @@ -108,15 +94,21 @@ index 0000000000..13093085a5 +#define SUNXI_TWI1_BASE 0x02502400 +#define SUNXI_TWI2_BASE 0x02502800 +#define SUNXI_TWI3_BASE 0x02502C00 -+#define SUNXI_SPI0_BASE 0x04025000 -+#define SUNXI_SPI1_BASE 0x04026000 + -+#define SUNXI_RTC_BASE 0x07000000 ++#define SUNXI_SRAMC_BASE 0x03000000 ++/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ ++#define SUNXI_SIDC_BASE 0x03006000 ++#define SUNXI_SID_BASE 0x03006200 ++#define SUNXI_GIC400_BASE 0x03020000 ++ ++#define SUNXI_MMC0_BASE 0x04020000 ++#define SUNXI_MMC1_BASE 0x04021000 ++#define SUNXI_MMC2_BASE 0x04022000 ++ +#define SUNXI_R_CPUCFG_BASE 0x07000400 -+#define SUNXI_PRCM_BASE 0x07010000 -+#define SUNXI_R_WDOG_BASE 0x07020400 -+#define SUNXI_R_UART_BASE 0x07080000 -+#define SUNXI_R_TWI_BASE 0x07081400 ++ ++#define SUNXI_CPUX_BASE 0x09010000 ++#define SUNXI_CPUCFG_BASE 0 + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); @@ -165,7 +157,7 @@ index bb5626d893..e17db8588e 100644 struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ #endif diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig -index b328ce8960..057b0ccd33 100644 +index b328ce8960..60ca1239dd 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -102,7 +102,7 @@ config AXP_PMIC_BUS @@ -177,14 +169,12 @@ index b328ce8960..057b0ccd33 100644 default 0x0 ---help--- Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, -@@ -144,6 +144,16 @@ config SUN50I_GEN_H6 +@@ -144,6 +144,14 @@ config SUN50I_GEN_H6 Select this for sunxi SoCs which have H6 like peripherals, clocks and memory map. +config SUNXI_GEN_NCAT2 + bool -+ select FIT -+ select SPL_LOAD_FIT + select MMC_SUNXI_HAS_NEW_MODE + select SUPPORT_SPL + ---help--- @@ -194,7 +184,7 @@ index b328ce8960..057b0ccd33 100644 config SUNXI_DRAM_DW bool ---help--- -@@ -760,6 +770,7 @@ config VIDEO_SUNXI +@@ -760,6 +768,7 @@ config VIDEO_SUNXI depends on !MACH_SUN9I depends on !MACH_SUN50I depends on !SUN50I_GEN_H6 @@ -202,7 +192,7 @@ index b328ce8960..057b0ccd33 100644 select VIDEO select DISPLAY imply VIDEO_DT_SIMPLEFB -@@ -973,6 +984,7 @@ config SPL_STACK_R_ADDR +@@ -973,6 +982,7 @@ config SPL_STACK_R_ADDR default 0x2fe00000 if MACH_SUN9I default 0x4fe00000 if MACH_SUN50I default 0x4fe00000 if SUN50I_GEN_H6 @@ -223,19 +213,37 @@ index 671211e932..1d4c70ec35 100644 obj-y += timer.o endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c -index ec46ab9279..6d96182226 100644 +index ec46ab9279..51b8e708b0 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c -@@ -176,7 +176,7 @@ static int gpio_init(void) +@@ -176,13 +176,19 @@ static int gpio_init(void) #error Unsupported console port number. Please fix pin mux settings in board.c #endif -#ifdef CONFIG_SUN50I_GEN_H6 -+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) - /* Update PIO power bias configuration by copy hardware detected value */ - val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); - writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); -@@ -481,7 +481,7 @@ void reset_cpu(void) +- /* Update PIO power bias configuration by copy hardware detected value */ +- val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); +- writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); +- val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); +- writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); +-#endif ++ /* ++ * Update PIO power bias configuration by copying the hardware ++ * detected value. ++ */ ++ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || ++ IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) { ++ val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); ++ writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); ++ } ++ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) { ++ val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); ++ writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); ++ } + + return 0; + } +@@ -481,7 +487,7 @@ void reset_cpu(void) /* sun5i sometimes gets stuck without this */ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } @@ -257,6 +265,20 @@ index 3c2af453ab..06bcedca7d 100644 default 0x00060 if ARCH_SUNXI default 0xfffc0000 if ARCH_ZYNQMP default 0x0 +diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c +index 93bbc6916e..5c9b92ccf9 100644 +--- a/drivers/i2c/mvtwsi.c ++++ b/drivers/i2c/mvtwsi.c +@@ -124,7 +124,8 @@ enum mvtwsi_ctrl_register_fields { + * on other platforms, it is a normal r/w bit, which is cleared by writing 0. + */ + +-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) ++#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || \ ++ defined(CONFIG_SUNXI_GEN_NCAT2) + #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 + #else + #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 03e33753fc..a8e590561c 100644 --- a/drivers/mmc/sunxi_mmc.c @@ -307,7 +329,7 @@ index 03e33753fc..a8e590561c 100644 return 0x88; diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h -index 2f8b220f75..04d7aa3d63 100644 +index 61978db6db..8cf9047ff9 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -16,6 +16,9 @@ diff --git a/package/boot/uboot-sunxi/patches/4009-pinctrl-sunxi-add-Allwinner-D1-pinctrl-description.patch b/package/boot/uboot-sunxi/patches/4015-pinctrl-sunxi-add-Allwinner-D1-pinctrl-description.patch similarity index 93% rename from package/boot/uboot-sunxi/patches/4009-pinctrl-sunxi-add-Allwinner-D1-pinctrl-description.patch rename to package/boot/uboot-sunxi/patches/4015-pinctrl-sunxi-add-Allwinner-D1-pinctrl-description.patch index cecf18b805..6dc13a39d5 100644 --- a/package/boot/uboot-sunxi/patches/4009-pinctrl-sunxi-add-Allwinner-D1-pinctrl-description.patch +++ b/package/boot/uboot-sunxi/patches/4015-pinctrl-sunxi-add-Allwinner-D1-pinctrl-description.patch @@ -1,7 +1,7 @@ -From c02a1ec850b5ff48527776589a0407004a92a33e Mon Sep 17 00:00:00 2001 +From 8221f71488b4fb448af0c23d2c9c56bea230584d Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Mon, 5 Sep 2022 16:25:57 +0100 -Subject: [PATCH 4009/4031] pinctrl: sunxi: add Allwinner D1 pinctrl +Date: Fri, 21 Jul 2023 14:45:55 +0100 +Subject: [PATCH 4015/4044] pinctrl: sunxi: add Allwinner D1 pinctrl description Apart from using the new pinctrl MMIO register layout, the Allwinner D1 diff --git a/package/boot/uboot-sunxi/patches/4010-clk-sunxi-Add-support-for-the-D1-CCU.patch b/package/boot/uboot-sunxi/patches/4016-clk-sunxi-Add-support-for-the-D1-CCU.patch similarity index 86% rename from package/boot/uboot-sunxi/patches/4010-clk-sunxi-Add-support-for-the-D1-CCU.patch rename to package/boot/uboot-sunxi/patches/4016-clk-sunxi-Add-support-for-the-D1-CCU.patch index b9459be0ad..dc40f5edfd 100644 --- a/package/boot/uboot-sunxi/patches/4010-clk-sunxi-Add-support-for-the-D1-CCU.patch +++ b/package/boot/uboot-sunxi/patches/4016-clk-sunxi-Add-support-for-the-D1-CCU.patch @@ -1,7 +1,7 @@ -From 67617005348057a6546b99125d64a7dcc440901a Mon Sep 17 00:00:00 2001 +From 716a59d3d21ebb997f345b28b972d8f6e627fe34 Mon Sep 17 00:00:00 2001 From: Samuel Holland -Date: Sat, 30 Apr 2022 22:38:37 -0500 -Subject: [PATCH 4010/4031] clk: sunxi: Add support for the D1 CCU +Date: Fri, 21 Jul 2023 14:45:56 +0100 +Subject: [PATCH 4016/4044] clk: sunxi: Add support for the D1 CCU Since the D1 CCU binding is defined, we can add support for its gates/resets, following the pattern of the existing drivers. @@ -9,13 +9,15 @@ gates/resets, following the pattern of the existing drivers. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Acked-by: Sean Anderson +Signed-off-by: Andre Przywara --- drivers/clk/sunxi/Kconfig | 6 + drivers/clk/sunxi/Makefile | 1 + - drivers/clk/sunxi/clk_d1.c | 101 ++++++++++++++ - include/dt-bindings/clock/sun20i-d1-ccu.h | 156 ++++++++++++++++++++++ - include/dt-bindings/reset/sun20i-d1-ccu.h | 77 +++++++++++ - 5 files changed, 341 insertions(+) + drivers/clk/sunxi/clk_d1.c | 84 ++++++++++++ + drivers/clk/sunxi/clk_sunxi.c | 5 + + include/dt-bindings/clock/sun20i-d1-ccu.h | 158 ++++++++++++++++++++++ + include/dt-bindings/reset/sun20i-d1-ccu.h | 79 +++++++++++ + 6 files changed, 333 insertions(+) create mode 100644 drivers/clk/sunxi/clk_d1.c create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h @@ -51,10 +53,10 @@ index 895da02ebe..90a277489d 100644 obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c new file mode 100644 -index 0000000000..9412b77a54 +index 0000000000..9dae761de8 --- /dev/null +++ b/drivers/clk/sunxi/clk_d1.c -@@ -0,0 +1,101 @@ +@@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Samuel Holland @@ -70,6 +72,8 @@ index 0000000000..9412b77a54 +#include + +static struct ccu_clk_gate d1_gates[] = { ++ [CLK_APB0] = GATE_DUMMY, ++ + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), @@ -131,37 +135,41 @@ index 0000000000..9412b77a54 + [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)), +}; + -+static const struct ccu_desc d1_ccu_desc = { ++const struct ccu_desc d1_ccu_desc = { + .gates = d1_gates, + .resets = d1_resets, ++ .num_gates = ARRAY_SIZE(d1_gates), ++ .num_resets = ARRAY_SIZE(d1_resets), +}; -+ -+static int d1_clk_bind(struct udevice *dev) -+{ -+ return sunxi_reset_bind(dev, ARRAY_SIZE(d1_resets)); -+} -+ -+static const struct udevice_id d1_ccu_ids[] = { +diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c +index ec02a2d037..a0011a35d9 100644 +--- a/drivers/clk/sunxi/clk_sunxi.c ++++ b/drivers/clk/sunxi/clk_sunxi.c +@@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_desc; + extern const struct ccu_desc a80_ccu_desc; + extern const struct ccu_desc a80_mmc_clk_desc; + extern const struct ccu_desc a83t_ccu_desc; ++extern const struct ccu_desc d1_ccu_desc; + extern const struct ccu_desc f1c100s_ccu_desc; + extern const struct ccu_desc h3_ccu_desc; + extern const struct ccu_desc h6_ccu_desc; +@@ -214,6 +215,10 @@ static const struct udevice_id sunxi_clk_ids[] = { + #ifdef CONFIG_CLK_SUNIV_F1C100S + { .compatible = "allwinner,suniv-f1c100s-ccu", + .data = (ulong)&f1c100s_ccu_desc }, ++#endif ++#ifdef CONFIG_CLK_SUN20I_D1 + { .compatible = "allwinner,sun20i-d1-ccu", + .data = (ulong)&d1_ccu_desc }, -+ { } -+}; -+ -+U_BOOT_DRIVER(clk_sun20i_d1) = { -+ .name = "sun20i_d1_ccu", -+ .id = UCLASS_CLK, -+ .of_match = d1_ccu_ids, -+ .priv_auto = sizeof(struct ccu_priv), -+ .ops = &sunxi_clk_ops, -+ .probe = sunxi_clk_probe, -+ .bind = d1_clk_bind, -+}; + #endif + { } + }; diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h new file mode 100644 -index 0000000000..e3ac53315e +index 0000000000..e143b99297 --- /dev/null +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h -@@ -0,0 +1,156 @@ +@@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2020 huangzhenwei@allwinnertech.com @@ -316,14 +324,16 @@ index 0000000000..e3ac53315e +#define CLK_FANOUT0 142 +#define CLK_FANOUT1 143 +#define CLK_FANOUT2 144 ++#define CLK_BUS_CAN0 145 ++#define CLK_BUS_CAN1 146 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h new file mode 100644 -index 0000000000..de9ff52032 +index 0000000000..f8001cf50b --- /dev/null +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h -@@ -0,0 +1,77 @@ +@@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 huangzhenwei@allwinnertech.com @@ -399,6 +409,8 @@ index 0000000000..de9ff52032 +#define RST_BUS_DSP_CFG 63 +#define RST_BUS_DSP_DBG 64 +#define RST_BUS_RISCV_CFG 65 ++#define RST_BUS_CAN0 66 ++#define RST_BUS_CAN1 67 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ -- diff --git a/package/boot/uboot-sunxi/patches/4011-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch b/package/boot/uboot-sunxi/patches/4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch similarity index 91% rename from package/boot/uboot-sunxi/patches/4011-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch rename to package/boot/uboot-sunxi/patches/4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch index 5432f78c6c..9bc22dc183 100644 --- a/package/boot/uboot-sunxi/patches/4011-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch +++ b/package/boot/uboot-sunxi/patches/4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch @@ -1,7 +1,7 @@ -From 90edf658a24549c3f5c568e54caa3230890918d8 Mon Sep 17 00:00:00 2001 +From 8cd51196fec0b7544cb5842dac9f7209542a6a61 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Fri, 2 Dec 2022 20:30:40 +0000 -Subject: [PATCH 4011/4031] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 +Date: Fri, 21 Jul 2023 14:45:57 +0100 +Subject: [PATCH 4017/4044] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL. diff --git a/package/boot/uboot-sunxi/patches/4012-sunxi-clock-support-D1-R528-PLL6-clock.patch b/package/boot/uboot-sunxi/patches/4018-sunxi-clock-support-D1-R528-PLL6-clock.patch similarity index 93% rename from package/boot/uboot-sunxi/patches/4012-sunxi-clock-support-D1-R528-PLL6-clock.patch rename to package/boot/uboot-sunxi/patches/4018-sunxi-clock-support-D1-R528-PLL6-clock.patch index 407b1cc01c..c07f59eb9a 100644 --- a/package/boot/uboot-sunxi/patches/4012-sunxi-clock-support-D1-R528-PLL6-clock.patch +++ b/package/boot/uboot-sunxi/patches/4018-sunxi-clock-support-D1-R528-PLL6-clock.patch @@ -1,7 +1,7 @@ -From 434dce1b0bfd9d3ab3a28352b596d27de3622796 Mon Sep 17 00:00:00 2001 +From 18b787a4cb4edc9b6aa38b55830c9f9f17716000 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Fri, 2 Dec 2022 21:48:19 +0000 -Subject: [PATCH 4012/4031] sunxi: clock: support D1/R528 PLL6 clock +Date: Fri, 21 Jul 2023 14:45:58 +0100 +Subject: [PATCH 4018/4044] sunxi: clock: support D1/R528 PLL6 clock The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is new P0 divider at bits [18:16], and the M divider is 1. diff --git a/package/boot/uboot-sunxi/patches/4019-sunxi-clock-h6-prepare-for-PRCM-less-SoCs.patch b/package/boot/uboot-sunxi/patches/4019-sunxi-clock-h6-prepare-for-PRCM-less-SoCs.patch new file mode 100644 index 0000000000..0ee1c1e2ad --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4019-sunxi-clock-h6-prepare-for-PRCM-less-SoCs.patch @@ -0,0 +1,75 @@ +From c691eece56bd26a66aeebe435dd5179c60073e43 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Fri, 21 Jul 2023 14:45:59 +0100 +Subject: [PATCH 4019/4044] sunxi: clock: h6: prepare for PRCM less SoCs + +The Allwinner D1/R528/T113 SoCs have a very minimal separate +"management" power plane, with almost no device attached to it (so +no r_i2c or r_uart). This means we don't need to flip any clock gates in +the PRCM block, which in fact those SoCs do not have. + +Prepare the code for those SoCs by making the PRCM block optional in the +H6 SPL clock code, which we otherwise share to this new family of SoCs. +If the memory map (cpu.h) does not define the PRCM address, we simply +skip any attempt to program gates there. + +Signed-off-by: Andre Przywara +--- + arch/arm/mach-sunxi/clock_sun50i_h6.c | 22 +++++++++++++++++++--- + 1 file changed, 19 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c +index 607efe6a9c..c3a4623d34 100644 +--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c ++++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c +@@ -4,14 +4,20 @@ + #include + #include + ++#ifndef SUNXI_PRCM_BASE ++#define SUNXI_PRCM_BASE 0 ++#endif ++ + #ifdef CONFIG_SPL_BUILD +-void clock_init_safe(void) ++ ++static void clock_init_safe_prcm(void) + { +- struct sunxi_ccm_reg *const ccm = +- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg *const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + ++ if (!prcm) ++ return; ++ + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { + /* this seems to enable PLLs on H616 */ + setbits_le32(&prcm->sys_pwroff_gating, 0x10); +@@ -27,6 +33,14 @@ void clock_init_safe(void) + /* set PLL VDD LDO output to 1.14 V */ + setbits_le32(&prcm->pll_ldo_cfg, 0x60000); + } ++} ++ ++void clock_init_safe(void) ++{ ++ struct sunxi_ccm_reg *const ccm = ++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; ++ ++ clock_init_safe_prcm(); + + clock_set_pll1(408000000); + +@@ -141,6 +155,8 @@ int clock_twi_onoff(int port, int state) + value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT); + + if (port == 5) { ++ if (!prcm) ++ return -ENODEV; + shift = 0; + ptr = &prcm->twi_gate_reset; + } else { +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4013-Kconfig-sunxi-prepare-for-using-drivers-ram-sunxi.patch b/package/boot/uboot-sunxi/patches/4020-Kconfig-sunxi-prepare-for-using-drivers-ram-sunxi.patch similarity index 74% rename from package/boot/uboot-sunxi/patches/4013-Kconfig-sunxi-prepare-for-using-drivers-ram-sunxi.patch rename to package/boot/uboot-sunxi/patches/4020-Kconfig-sunxi-prepare-for-using-drivers-ram-sunxi.patch index 02d2004f8e..e949d699b8 100644 --- a/package/boot/uboot-sunxi/patches/4013-Kconfig-sunxi-prepare-for-using-drivers-ram-sunxi.patch +++ b/package/boot/uboot-sunxi/patches/4020-Kconfig-sunxi-prepare-for-using-drivers-ram-sunxi.patch @@ -1,7 +1,7 @@ -From af8381ba9b63dd3e79fb874da151d56af68b7930 Mon Sep 17 00:00:00 2001 +From b3afb64d19f297a9bddddaf75e67a88b1be96f90 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Sun, 18 Dec 2022 00:12:07 +0000 -Subject: [PATCH 4013/4031] Kconfig: sunxi: prepare for using drivers/ram/sunxi +Date: Sat, 26 Aug 2023 16:56:03 +0200 +Subject: [PATCH 4020/4044] Kconfig: sunxi: prepare for using drivers/ram/sunxi At the moment all Allwinner DRAM initialisation routines are stored in arch/arm/mach-sunxi, even though those "drivers" are just a giant @@ -20,24 +20,19 @@ depend on that already. Signed-off-by: Andre Przywara --- - drivers/ram/Kconfig | 3 ++- + drivers/ram/Kconfig | 1 + drivers/ram/sunxi/Kconfig | 13 +++++++++++++ - 2 files changed, 15 insertions(+), 1 deletion(-) + 2 files changed, 14 insertions(+) create mode 100644 drivers/ram/sunxi/Kconfig diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig -index e085119963..d162a7f0d9 100644 +index e085119963..636374be59 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig -@@ -108,7 +108,8 @@ config IMXRT_SDRAM - This driver is for the sdram memory interface with the SEMC. - - source "drivers/ram/aspeed/Kconfig" -+source "drivers/ram/octeon/Kconfig" - source "drivers/ram/rockchip/Kconfig" +@@ -112,3 +112,4 @@ source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" --source "drivers/ram/octeon/Kconfig" + source "drivers/ram/octeon/Kconfig" +source "drivers/ram/sunxi/Kconfig" diff --git a/drivers/ram/sunxi/Kconfig b/drivers/ram/sunxi/Kconfig new file mode 100644 diff --git a/package/boot/uboot-sunxi/patches/4014-sunxi-add-R528-T113-s3-D1-s-DRAM-initialisation-code.patch b/package/boot/uboot-sunxi/patches/4021-sunxi-add-R528-T113-s3-D1-s-DRAM-initialisation-code.patch similarity index 82% rename from package/boot/uboot-sunxi/patches/4014-sunxi-add-R528-T113-s3-D1-s-DRAM-initialisation-code.patch rename to package/boot/uboot-sunxi/patches/4021-sunxi-add-R528-T113-s3-D1-s-DRAM-initialisation-code.patch index f65074d07b..288d5fd01b 100644 --- a/package/boot/uboot-sunxi/patches/4014-sunxi-add-R528-T113-s3-D1-s-DRAM-initialisation-code.patch +++ b/package/boot/uboot-sunxi/patches/4021-sunxi-add-R528-T113-s3-D1-s-DRAM-initialisation-code.patch @@ -1,7 +1,7 @@ -From 6da5b94e68464980cb4e3425746d8b3b24590709 Mon Sep 17 00:00:00 2001 +From 96e17af5ca374af5e45422ca56d11f523437d2d2 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Sat, 31 Dec 2022 18:38:21 +0000 -Subject: [PATCH 4014/4031] sunxi: add R528/T113-s3/D1(s) DRAM initialisation +Date: Fri, 21 Jul 2023 14:46:01 +0100 +Subject: [PATCH 4021/4044] sunxi: add R528/T113-s3/D1(s) DRAM initialisation code The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the @@ -22,14 +22,15 @@ delivered via Kconfig, so this code here should work for all supported SoCs and DRAM chips combinations. Signed-off-by: Andre Przywara +Tested-by: Sam Edwards --- drivers/Makefile | 1 + - drivers/ram/Makefile | 2 + - drivers/ram/sunxi/Kconfig | 55 ++ + drivers/ram/Makefile | 3 + + drivers/ram/sunxi/Kconfig | 59 ++ drivers/ram/sunxi/Makefile | 4 + - drivers/ram/sunxi/dram_sun20i_d1.c | 1425 ++++++++++++++++++++++++++++ - drivers/ram/sunxi/dram_sun20i_d1.h | 70 ++ - 6 files changed, 1557 insertions(+) + drivers/ram/sunxi/dram_sun20i_d1.c | 1432 ++++++++++++++++++++++++++++ + drivers/ram/sunxi/dram_sun20i_d1.h | 73 ++ + 6 files changed, 1572 insertions(+) create mode 100644 drivers/ram/sunxi/Makefile create mode 100644 drivers/ram/sunxi/dram_sun20i_d1.c create mode 100644 drivers/ram/sunxi/dram_sun20i_d1.h @@ -47,25 +48,30 @@ index 15d19d0c8a..1542ce7caf 100644 obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile -index 83948e2c43..050c11e840 100644 +index 83948e2c43..ae3cf65fa4 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile -@@ -21,4 +21,6 @@ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o - - obj-$(CONFIG_RAM_SIFIVE) += sifive/ +@@ -10,6 +10,9 @@ obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/ + obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o + obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o +obj-$(CONFIG_DRAM_SUN8I_R528) += sunxi/ + - obj-$(CONFIG_ARCH_OCTEON) += octeon/ ++ + obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ + + obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o diff --git a/drivers/ram/sunxi/Kconfig b/drivers/ram/sunxi/Kconfig -index 97e261de54..36875ddf22 100644 +index 97e261de54..657f47a870 100644 --- a/drivers/ram/sunxi/Kconfig +++ b/drivers/ram/sunxi/Kconfig -@@ -11,3 +11,58 @@ config DRAM_SUN8I_R528 +@@ -11,3 +11,62 @@ config DRAM_SUN8I_R528 default y if MACH_SUN8I_R528 help Select this DRAM controller driver for the R528/T113s SoCs. + ++if DRAM_SUN20I_D1 || DRAM_SUN8I_R528 ++ +config DRAM_SUNXI_ODT_EN + hex "DRAM ODT EN parameter" + default 0x1 @@ -99,27 +105,29 @@ index 97e261de54..36875ddf22 100644 + +choice + prompt "DRAM chip type" -+ default SUNXI_DRAM_DDR3 if DRAM_SUN8I_R528 || DRAM_SUN20I_D1 ++ default SUNXI_DRAM_TYPE_DDR3 if DRAM_SUN8I_R528 || DRAM_SUN20I_D1 + -+config SUNXI_DRAM_DDR2 ++config SUNXI_DRAM_TYPE_DDR2 + bool "DDR2 chips" + -+config SUNXI_DRAM_DDR3 ++config SUNXI_DRAM_TYPE_DDR3 + bool "DDR3 chips" + -+config SUNXI_DRAM_LPDDR2 ++config SUNXI_DRAM_TYPE_LPDDR2 + bool "LPDDR2 chips" + -+config SUNXI_DRAM_LPDDR3 ++config SUNXI_DRAM_TYPE_LPDDR3 + bool "LPDDR3 chips" +endchoice + +config SUNXI_DRAM_TYPE + int -+ default 2 if SUNXI_DRAM_DDR2 -+ default 3 if SUNXI_DRAM_DDR3 -+ default 6 if SUNXI_DRAM_LPDDR2 -+ default 7 if SUNXI_DRAM_LPDDR3 ++ default 2 if SUNXI_DRAM_TYPE_DDR2 ++ default 3 if SUNXI_DRAM_TYPE_DDR3 ++ default 6 if SUNXI_DRAM_TYPE_LPDDR2 ++ default 7 if SUNXI_DRAM_TYPE_LPDDR3 ++ ++endif diff --git a/drivers/ram/sunxi/Makefile b/drivers/ram/sunxi/Makefile new file mode 100644 index 0000000000..d6fb2cf0b6 @@ -132,10 +140,10 @@ index 0000000000..d6fb2cf0b6 +obj-$(CONFIG_DRAM_SUN8I_R528) += dram_sun20i_d1.o diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c new file mode 100644 -index 0000000000..25005ceefb +index 0000000000..c766fc2406 --- /dev/null +++ b/drivers/ram/sunxi/dram_sun20i_d1.c -@@ -0,0 +1,1425 @@ +@@ -0,0 +1,1432 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Allwinner D1/D1s/R528/T113-sx DRAM initialisation @@ -164,7 +172,11 @@ index 0000000000..25005ceefb +#define SUNXI_SID_BASE 0x3006200 +#endif + -+static void sid_read_ldoB_cal(dram_para_t *para) ++#ifndef SUNXI_CCM_BASE ++#define SUNXI_CCM_BASE 0x2001000 ++#endif ++ ++static void sid_read_ldoB_cal(const dram_para_t *para) +{ + uint32_t reg; + @@ -188,7 +200,7 @@ index 0000000000..25005ceefb + clrsetbits_le32(0x3000150, 0xff00, reg << 8); +} + -+static void dram_voltage_set(dram_para_t *para) ++static void dram_voltage_set(const dram_para_t *para) +{ + int vol; + @@ -227,7 +239,7 @@ index 0000000000..25005ceefb + udelay(10); +} + -+static void eye_delay_compensation(dram_para_t *para) // s1 ++static void eye_delay_compensation(const dram_para_t *para) +{ + uint32_t delay; + unsigned long ptr; @@ -284,7 +296,8 @@ index 0000000000..25005ceefb + * timing settings for the specific type of sdram used. Read together with + * an sdram datasheet for context on the various variables. + */ -+static void mctl_set_timing_params(dram_para_t *para) ++static void mctl_set_timing_params(const dram_para_t *para, ++ const dram_config_t *config) +{ + /* DRAM_TPR0 */ + u8 tccd = 2; @@ -331,7 +344,7 @@ index 0000000000..25005ceefb + u32 tdinit2; + u32 tdinit3; + -+ switch (CONFIG_SUNXI_DRAM_TYPE) { ++ switch (para->dram_type) { + case SUNXI_DRAM_TYPE_DDR2: + /* DRAM_TPR0 */ + tfaw = ns_to_t(50); @@ -436,7 +449,7 @@ index 0000000000..25005ceefb + tcke = 3; + tcksrx = 5; + tckesr = 4; -+ if (((para->dram_tpr13 & 0xc) == 0x04) || CONFIG_DRAM_CLK < 912) ++ if (((config->dram_tpr13 & 0xc) == 0x04) || CONFIG_DRAM_CLK < 912) + trd2wr = 5; + else + trd2wr = 6; @@ -614,11 +627,12 @@ index 0000000000..25005ceefb +// Purpose of this routine seems to be to initialize the PLL driving +// the MBUS and sdram. +// -+static int ccu_set_pll_ddr_clk(int index, dram_para_t *para) ++static int ccu_set_pll_ddr_clk(int index, const dram_para_t *para, ++ const dram_config_t *config) +{ + unsigned int val, clk, n; + -+ if (para->dram_tpr13 & BIT(6)) ++ if (config->dram_tpr13 & BIT(6)) + clk = para->dram_tpr9; + else + clk = para->dram_clk; @@ -626,66 +640,60 @@ index 0000000000..25005ceefb + // set VCO clock divider + n = (clk * 2) / 24; + -+ val = readl(0x2001010); -+ val &= 0xfff800fc; // clear dividers -+ val |= (n - 1) << 8; // set PLL division -+ val |= 0xc0000000; // enable PLL and LDO -+ val &= 0xdfffffff; -+ writel(val | 0x20000000, 0x2001010); ++ val = readl(SUNXI_CCM_BASE + 0x10); ++ val &= ~0x0007ff03; // clear dividers ++ val |= (n - 1) << 8; // set PLL division ++ val |= BIT(31) | BIT(30); // enable PLL and LDO ++ writel(val | BIT(29), SUNXI_CCM_BASE + 0x10); + + // wait for PLL to lock -+ while ((readl(0x2001010) & 0x10000000) == 0) { ++ while ((readl(SUNXI_CCM_BASE + 0x10) & BIT(28)) == 0) + ; -+ } + + udelay(20); + + // enable PLL output -+ val = readl(0x2001000); -+ val |= 0x08000000; -+ writel(val, 0x2001000); ++ setbits_le32(SUNXI_CCM_BASE + 0x0, BIT(27)); + + // turn clock gate on -+ val = readl(0x2001800); -+ val &= 0xfcfffcfc; // select DDR clk source, n=1, m=1 -+ val |= 0x80000000; // turn clock on -+ writel(val, 0x2001800); ++ val = readl(SUNXI_CCM_BASE + 0x800); ++ val &= ~0x03000303; // select DDR clk source, n=1, m=1 ++ val |= BIT(31); // turn clock on ++ writel(val, SUNXI_CCM_BASE + 0x800); + + return n * 24; +} + -+// Main purpose of sys_init seems to be to initalise the clocks for -+// the sdram controller. -+// -+static void mctl_sys_init(dram_para_t *para) ++/* Set up the PLL and clock gates for the DRAM controller and MBUS clocks. */ ++static void mctl_sys_init(const dram_para_t *para, const dram_config_t *config) +{ + // assert MBUS reset -+ clrbits_le32(0x2001540, BIT(30)); ++ clrbits_le32(SUNXI_CCM_BASE + 0x540, BIT(30)); + + // turn off sdram clock gate, assert sdram reset -+ clrbits_le32(0x200180c, 0x10001); -+ clrsetbits_le32(0x2001800, BIT(31) | BIT(30), BIT(27)); ++ clrbits_le32(SUNXI_CCM_BASE + 0x80c, 0x10001); ++ clrsetbits_le32(SUNXI_CCM_BASE + 0x800, BIT(31) | BIT(30), BIT(27)); + udelay(10); + + // set ddr pll clock -+ para->dram_clk = ccu_set_pll_ddr_clk(0, para) / 2; ++ ccu_set_pll_ddr_clk(0, para, config); + udelay(100); + dram_disable_all_master(); + + // release sdram reset -+ setbits_le32(0x200180c, BIT(16)); ++ setbits_le32(SUNXI_CCM_BASE + 0x80c, BIT(16)); + + // release MBUS reset -+ setbits_le32(0x2001540, BIT(30)); -+ setbits_le32(0x2001800, BIT(30)); ++ setbits_le32(SUNXI_CCM_BASE + 0x540, BIT(30)); ++ setbits_le32(SUNXI_CCM_BASE + 0x800, BIT(30)); + + udelay(5); + + // turn on sdram clock gate -+ setbits_le32(0x200180c, BIT(0)); ++ setbits_le32(SUNXI_CCM_BASE + 0x80c, BIT(0)); + + // turn dram clock gate on, trigger sdr clock update -+ setbits_le32(0x2001800, BIT(31) | BIT(27)); ++ setbits_le32(SUNXI_CCM_BASE + 0x800, BIT(31) | BIT(27)); + udelay(5); + + // mCTL clock enable @@ -697,7 +705,7 @@ index 0000000000..25005ceefb +// from the dram_para1 and dram_para2 fields to the PHY configuration registers +// (0x3102000, 0x3102004). +// -+static void mctl_com_init(dram_para_t *para) ++static void mctl_com_init(const dram_para_t *para, const dram_config_t *config) +{ + uint32_t val, width; + unsigned long ptr; @@ -709,20 +717,20 @@ index 0000000000..25005ceefb + // set SDRAM type and word width + val = readl(0x3102000) & ~0x00fff000; + val |= (para->dram_type & 0x7) << 16; // DRAM type -+ val |= (~para->dram_para2 & 0x1) << 12; // DQ width ++ val |= (~config->dram_para2 & 0x1) << 12; // DQ width + val |= BIT(22); // ?? + if (para->dram_type == SUNXI_DRAM_TYPE_LPDDR2 || + para->dram_type == SUNXI_DRAM_TYPE_LPDDR3) { + val |= BIT(19); // type 6 and 7 must use 1T + } else { -+ if (para->dram_tpr13 & BIT(5)) ++ if (config->dram_tpr13 & BIT(5)) + val |= BIT(19); + } + writel(val, 0x3102000); + + // init rank / bank / row for single/dual or two different ranks -+ if ((para->dram_para2 & BIT(8)) && -+ ((para->dram_para2 & 0xf000) != 0x1000)) ++ if ((config->dram_para2 & BIT(8)) && ++ ((config->dram_para2 & 0xf000) != 0x1000)) + width = 32; + else + width = 16; @@ -731,12 +739,12 @@ index 0000000000..25005ceefb + for (i = 0; i < width; i += 16) { + val = readl(ptr) & 0xfffff000; + -+ val |= (para->dram_para2 >> 12) & 0x3; // rank -+ val |= ((para->dram_para1 >> (i + 12)) << 2) & 0x4; // bank - 2 -+ val |= (((para->dram_para1 >> (i + 4)) - 1) << 4) & 0xff; // row - 1 ++ val |= (config->dram_para2 >> 12) & 0x3; // rank ++ val |= ((config->dram_para1 >> (i + 12)) << 2) & 0x4; // bank - 2 ++ val |= (((config->dram_para1 >> (i + 4)) - 1) << 4) & 0xff; // row - 1 + + // convert from page size to column addr width - 3 -+ switch ((para->dram_para1 >> i) & 0xf) { ++ switch ((config->dram_para1 >> i) & 0xf) { + case 8: val |= 0xa00; break; + case 4: val |= 0x900; break; + case 2: val |= 0x800; break; @@ -752,7 +760,7 @@ index 0000000000..25005ceefb + writel(val, 0x3103120); + + // set mctl reg 3c4 to zero when using half DQ -+ if (para->dram_para2 & BIT(0)) ++ if (config->dram_para2 & BIT(0)) + writel(0, 0x31033c4); + + // purpose ?? @@ -785,7 +793,8 @@ index 0000000000..25005ceefb + * It is unclear which lines are being remapped. It seems to pick + * table cfg7 for the Nezha board. + */ -+static void mctl_phy_ac_remapping(dram_para_t *para) ++static void mctl_phy_ac_remapping(const dram_para_t *para, ++ const dram_config_t *config) +{ + const uint8_t *cfg; + uint32_t fuse, val; @@ -806,7 +815,7 @@ index 0000000000..25005ceefb + return; + cfg = ac_remapping_tables[6]; + } else { -+ if (para->dram_tpr13 & 0xc0000) { ++ if (config->dram_tpr13 & 0xc0000) { + cfg = ac_remapping_tables[7]; + } else { + switch (fuse) { @@ -846,11 +855,13 @@ index 0000000000..25005ceefb +// Init the controller channel. The key part is placing commands in the main +// command register (PIR, 0x3103000) and checking command status (PGSR0, 0x3103010). +// -+static unsigned int mctl_channel_init(unsigned int ch_index, dram_para_t *para) ++static unsigned int mctl_channel_init(unsigned int ch_index, ++ const dram_para_t *para, ++ const dram_config_t *config) +{ + unsigned int val, dqs_gating_mode; + -+ dqs_gating_mode = (para->dram_tpr13 & 0xc) >> 2; ++ dqs_gating_mode = (config->dram_tpr13 & 0xc) >> 2; + + // set DDR clock to half of CPU clock + clrsetbits_le32(0x310200c, 0xfff, (para->dram_clk / 2) - 1); @@ -891,7 +902,7 @@ index 0000000000..25005ceefb + clrsetbits_le32(0x3103108, 0xc0, 0x80); + + clrsetbits_le32(0x31030bc, 0x107, -+ (((para->dram_tpr13 >> 16) & 0x1f) - 2) | 0x100); ++ (((config->dram_tpr13 >> 16) & 0x1f) - 2) | 0x100); + clrsetbits_le32(0x310311c, BIT(31), BIT(27)); + } else { + clrbits_le32(0x3103108, 0x40); @@ -908,9 +919,9 @@ index 0000000000..25005ceefb + } + + clrsetbits_le32(0x31030c0, 0x0fffffff, -+ (para->dram_para2 & BIT(12)) ? 0x03000001 : 0x01000007); ++ (config->dram_para2 & BIT(12)) ? 0x03000001 : 0x01000007); + -+ if (readl(0x70005d4) & (1 << 16)) { ++ if (readl(0x70005d4) & BIT(16)) { + clrbits_le32(0x7010250, 0x2); + udelay(10); + } @@ -952,7 +963,7 @@ index 0000000000..25005ceefb + while ((readl(0x3103010) & 0x1) == 0) { + } // wait for IDONE + -+ if (readl(0x70005d4) & (1 << 16)) { ++ if (readl(0x70005d4) & BIT(16)) { + clrsetbits_le32(0x310310c, 0x06000000, 0x04000000); + udelay(10); + @@ -1049,39 +1060,39 @@ index 0000000000..25005ceefb + * If there was an error, figure out whether it was half DQ, single rank, + * or both. Set bit 12 and 0 in dram_para2 with the results. + */ -+static int dqs_gate_detect(dram_para_t *para) ++static int dqs_gate_detect(dram_config_t *config) +{ + uint32_t dx0, dx1; + + if ((readl(0x3103010) & BIT(22)) == 0) { -+ para->dram_para2 = (para->dram_para2 & ~0xf) | BIT(12); ++ config->dram_para2 = (config->dram_para2 & ~0xf) | BIT(12); + debug("dual rank and full DQ\n"); + + return 1; + } + -+ dx0 = (readl(0x03103348) & 0x3000000) >> 24; ++ dx0 = (readl(0x3103348) & 0x3000000) >> 24; + if (dx0 == 0) { -+ para->dram_para2 = (para->dram_para2 & ~0xf) | 0x1001; ++ config->dram_para2 = (config->dram_para2 & ~0xf) | 0x1001; + debug("dual rank and half DQ\n"); + + return 1; + } + + if (dx0 == 2) { -+ dx1 = (readl(0x031033c8) & 0x3000000) >> 24; ++ dx1 = (readl(0x31033c8) & 0x3000000) >> 24; + if (dx1 == 2) { -+ para->dram_para2 = para->dram_para2 & ~0xf00f; ++ config->dram_para2 = config->dram_para2 & ~0xf00f; + debug("single rank and full DQ\n"); + } else { -+ para->dram_para2 = (para->dram_para2 & ~0xf00f) | BIT(0); ++ config->dram_para2 = (config->dram_para2 & ~0xf00f) | BIT(0); + debug("single rank and half DQ\n"); + } + + return 1; + } + -+ if ((para->dram_tpr13 & BIT(29)) == 0) ++ if ((config->dram_tpr13 & BIT(29)) == 0) + return 0; + + debug("DX0 state: %d\n", dx0); @@ -1127,15 +1138,15 @@ index 0000000000..25005ceefb + +// Set the Vref mode for the controller +// -+static void mctl_vrefzq_init(dram_para_t *para) ++static void mctl_vrefzq_init(const dram_para_t *para, const dram_config_t *config) +{ -+ if (para->dram_tpr13 & BIT(17)) ++ if (config->dram_tpr13 & BIT(17)) + return; + + clrsetbits_le32(0x3103110, 0x7f7f7f7f, para->dram_tpr5); + + // IOCVR1 -+ if ((para->dram_tpr13 & BIT(16)) == 0) ++ if ((config->dram_tpr13 & BIT(16)) == 0) + clrsetbits_le32(0x3103114, 0x7f, para->dram_tpr6 & 0x7f); +} + @@ -1144,19 +1155,19 @@ index 0000000000..25005ceefb +// establish the actual ram size. The third time is final one, with the final +// settings. +// -+static int mctl_core_init(dram_para_t *para) ++static int mctl_core_init(const dram_para_t *para, const dram_config_t *config) +{ -+ mctl_sys_init(para); ++ mctl_sys_init(para, config); + -+ mctl_vrefzq_init(para); ++ mctl_vrefzq_init(para, config); + -+ mctl_com_init(para); ++ mctl_com_init(para, config); + -+ mctl_phy_ac_remapping(para); ++ mctl_phy_ac_remapping(para, config); + -+ mctl_set_timing_params(para); ++ mctl_set_timing_params(para, config); + -+ return mctl_channel_init(0, para); ++ return mctl_channel_init(0, para, config); +} + +/* @@ -1170,18 +1181,18 @@ index 0000000000..25005ceefb + * BA0-1 and row addresses. Finally, the column address is allocated 13 lines + * and these are tested. The results are placed in dram_para1 and dram_para2. + */ -+static int auto_scan_dram_size(dram_para_t *para) ++static int auto_scan_dram_size(const dram_para_t *para, dram_config_t *config) +{ + unsigned int rval, i, j, rank, maxrank, offs; + unsigned int shft; + unsigned long ptr, mc_work_mode, chk; + -+ if (mctl_core_init(para) == 0) { ++ if (mctl_core_init(para, config) == 0) { + printf("DRAM initialisation error : 0\n"); + return 0; + } + -+ maxrank = (para->dram_para2 & 0xf000) ? 2 : 1; ++ maxrank = (config->dram_para2 & 0xf000) ? 2 : 1; + mc_work_mode = 0x3102000; + offs = 0; + @@ -1213,10 +1224,10 @@ index 0000000000..25005ceefb + + /* Store rows in para 1 */ + shft = offs + 4; -+ rval = para->dram_para1; ++ rval = config->dram_para1; + rval &= ~(0xff << shft); + rval |= i << shft; -+ para->dram_para1 = rval; ++ config->dram_para1 = rval; + + if (rank == 1) /* Set bank mode for rank0 */ + clrsetbits_le32(0x3102000, 0xffc, 0x6a4); @@ -1241,10 +1252,10 @@ index 0000000000..25005ceefb + + /* Store banks in para 1 */ + shft = 12 + offs; -+ rval = para->dram_para1; ++ rval = config->dram_para1; + rval &= ~(0xf << shft); + rval |= j << shft; -+ para->dram_para1 = rval; ++ config->dram_para1 = rval; + + if (rank == 1) /* Set page mode for rank0 */ + clrsetbits_le32(0x3102000, 0xffc, 0xaa0); @@ -1274,10 +1285,10 @@ index 0000000000..25005ceefb + + /* Store page size */ + shft = offs; -+ rval = para->dram_para1; ++ rval = config->dram_para1; + rval &= ~(0xf << shft); + rval |= pgsize << shft; -+ para->dram_para1 = rval; ++ config->dram_para1 = rval; + + // Move to next rank + rank++; @@ -1295,12 +1306,12 @@ index 0000000000..25005ceefb + } + } + if (maxrank == 2) { -+ para->dram_para2 &= 0xfffff0ff; ++ config->dram_para2 &= 0xfffff0ff; + /* note: rval is equal to para->dram_para1 here */ + if ((rval & 0xffff) == (rval >> 16)) { + debug("rank1 config same as rank0\n"); + } else { -+ para->dram_para2 |= BIT(8); ++ config->dram_para2 |= BIT(8); + debug("rank1 config different from rank0\n"); + } + } @@ -1314,27 +1325,28 @@ index 0000000000..25005ceefb + * full or half DQ width. It then resets the parameters to the original values. + * dram_para2 is updated with the rank and width findings. + */ -+static int auto_scan_dram_rank_width(dram_para_t *para) ++static int auto_scan_dram_rank_width(const dram_para_t *para, ++ dram_config_t *config) +{ -+ unsigned int s1 = para->dram_tpr13; -+ unsigned int s2 = para->dram_para1; ++ unsigned int s1 = config->dram_tpr13; ++ unsigned int s2 = config->dram_para1; + -+ para->dram_para1 = 0x00b000b0; -+ para->dram_para2 = (para->dram_para2 & ~0xf) | BIT(12); ++ config->dram_para1 = 0x00b000b0; ++ config->dram_para2 = (config->dram_para2 & ~0xf) | BIT(12); + + /* set DQS probe mode */ -+ para->dram_tpr13 = (para->dram_tpr13 & ~0x8) | BIT(2) | BIT(0); ++ config->dram_tpr13 = (config->dram_tpr13 & ~0x8) | BIT(2) | BIT(0); + -+ mctl_core_init(para); ++ mctl_core_init(para, config); + + if (readl(0x3103010) & BIT(20)) + return 0; + -+ if (dqs_gate_detect(para) == 0) ++ if (dqs_gate_detect(config) == 0) + return 0; + -+ para->dram_tpr13 = s1; -+ para->dram_para1 = s2; ++ config->dram_tpr13 = s1; ++ config->dram_para1 = s2; + + return 1; +} @@ -1345,28 +1357,34 @@ index 0000000000..25005ceefb + * the size of each rank. It then updates dram_tpr13 to reflect that the sizes + * are now known: a re-init will not repeat the autoscan. + */ -+static int auto_scan_dram_config(dram_para_t *para) ++static int auto_scan_dram_config(const dram_para_t *para, ++ dram_config_t *config) +{ -+ if (((para->dram_tpr13 & BIT(14)) == 0) && -+ (auto_scan_dram_rank_width(para) == 0)) { ++ if (((config->dram_tpr13 & BIT(14)) == 0) && ++ (auto_scan_dram_rank_width(para, config) == 0)) { + printf("ERROR: auto scan dram rank & width failed\n"); + return 0; + } + -+ if (((para->dram_tpr13 & BIT(0)) == 0) && -+ (auto_scan_dram_size(para) == 0)) { ++ if (((config->dram_tpr13 & BIT(0)) == 0) && ++ (auto_scan_dram_size(para, config) == 0)) { + printf("ERROR: auto scan dram size failed\n"); + return 0; + } + -+ if ((para->dram_tpr13 & BIT(15)) == 0) -+ para->dram_tpr13 |= BIT(14) | BIT(13) | BIT(1) | BIT(0); ++ if ((config->dram_tpr13 & BIT(15)) == 0) ++ config->dram_tpr13 |= BIT(14) | BIT(13) | BIT(1) | BIT(0); + + return 1; +} + -+int init_DRAM(int type, dram_para_t *para) ++static int init_DRAM(int type, const dram_para_t *para) +{ ++ dram_config_t config = { ++ .dram_para1 = 0x000010d2, ++ .dram_para2 = 0, ++ .dram_tpr13 = CONFIG_DRAM_SUNXI_TPR13, ++ }; + u32 rc, mem_size_mb; + + debug("DRAM BOOT DRIVE INFO: %s\n", "V0.24"); @@ -1378,14 +1396,14 @@ index 0000000000..25005ceefb + debug("DRAMC ZQ value: 0x%x\n", para->dram_zq); + + /* Test ZQ status */ -+ if (para->dram_tpr13 & BIT(16)) { ++ if (config.dram_tpr13 & BIT(16)) { + debug("DRAM only have internal ZQ\n"); + setbits_le32(0x3000160, BIT(8)); + writel(0, 0x3000168); + udelay(10); + } else { + clrbits_le32(0x3000160, 0x3); -+ writel(para->dram_tpr13 & BIT(16), 0x7010254); ++ writel(config.dram_tpr13 & BIT(16), 0x7010254); + udelay(10); + clrsetbits_le32(0x3000160, 0x108, BIT(1)); + udelay(10); @@ -1397,8 +1415,8 @@ index 0000000000..25005ceefb + dram_voltage_set(para); + + /* Set SDRAM controller auto config */ -+ if ((para->dram_tpr13 & BIT(0)) == 0) { -+ if (auto_scan_dram_config(para) == 0) { ++ if ((config.dram_tpr13 & BIT(0)) == 0) { ++ if (auto_scan_dram_config(para, &config) == 0) { + printf("auto_scan_dram_config() FAILED\n"); + return 0; + } @@ -1412,25 +1430,25 @@ index 0000000000..25005ceefb + debug("DRAM ODT value: 0x%x\n", rc); + + /* Init core, final run */ -+ if (mctl_core_init(para) == 0) { ++ if (mctl_core_init(para, &config) == 0) { + printf("DRAM initialisation error: 1\n"); + return 0; + } + + /* Get SDRAM size */ + /* TODO: who ever puts a negative number in the top half? */ -+ rc = para->dram_para2; ++ rc = config.dram_para2; + if (rc & BIT(31)) { + rc = (rc >> 16) & ~BIT(15); + } else { + rc = DRAMC_get_dram_size(); + debug("DRAM: size = %dMB\n", rc); -+ para->dram_para2 = (para->dram_para2 & 0xffffU) | rc << 16; ++ config.dram_para2 = (config.dram_para2 & 0xffffU) | rc << 16; + } + mem_size_mb = rc; + + /* Purpose ?? */ -+ if (para->dram_tpr13 & BIT(30)) { ++ if (config.dram_tpr13 & BIT(30)) { + rc = para->dram_tpr8; + if (rc == 0) + rc = 0x10000200; @@ -1444,7 +1462,7 @@ index 0000000000..25005ceefb + } + + /* Purpose ?? */ -+ if (para->dram_tpr13 & BIT(9)) { ++ if (config.dram_tpr13 & BIT(9)) { + clrsetbits_le32(0x3103100, 0xf000, 0x5000); + } else { + if (para->dram_type != SUNXI_DRAM_TYPE_LPDDR2) @@ -1454,10 +1472,10 @@ index 0000000000..25005ceefb + setbits_le32(0x3103140, BIT(31)); + + /* CHECK: is that really writing to a different register? */ -+ if (para->dram_tpr13 & BIT(8)) ++ if (config.dram_tpr13 & BIT(8)) + writel(readl(0x3103140) | 0x300, 0x31030b8); + -+ if (para->dram_tpr13 & BIT(16)) ++ if (config.dram_tpr13 & BIT(16)) + clrbits_le32(0x3103108, BIT(13)); + else + setbits_le32(0x3103108, BIT(13)); @@ -1467,7 +1485,7 @@ index 0000000000..25005ceefb + clrsetbits_le32(0x310307c, 0xf0000, 0x1000); + + dram_enable_all_master(); -+ if (para->dram_tpr13 & BIT(28)) { ++ if (config.dram_tpr13 & BIT(28)) { + if ((readl(0x70005d4) & BIT(16)) || + dramc_simple_wr_test(mem_size_mb, 4096)) + return 0; @@ -1476,15 +1494,11 @@ index 0000000000..25005ceefb + return mem_size_mb; +} + -+unsigned long sunxi_dram_init(void) -+{ -+ dram_para_t para = { ++ static const dram_para_t para = { + .dram_clk = CONFIG_DRAM_CLK, + .dram_type = CONFIG_SUNXI_DRAM_TYPE, + .dram_zq = CONFIG_DRAM_ZQ, + .dram_odt_en = CONFIG_DRAM_SUNXI_ODT_EN, -+ .dram_para1 = 0x000010d2, -+ .dram_para2 = 0, + .dram_mr0 = 0x1c70, + .dram_mr1 = 0x42, + .dram_mr2 = 0x18, @@ -1502,9 +1516,10 @@ index 0000000000..25005ceefb + .dram_tpr10 = 0, + .dram_tpr11 = CONFIG_DRAM_SUNXI_TPR11, + .dram_tpr12 = CONFIG_DRAM_SUNXI_TPR12, -+ .dram_tpr13 = CONFIG_DRAM_SUNXI_TPR13, + }; + ++unsigned long sunxi_dram_init(void) ++{ + return init_DRAM(0, ¶) * 1024UL * 1024; +}; + @@ -1563,10 +1578,10 @@ index 0000000000..25005ceefb +#endif /* CONFIG_RAM (using driver model) */ diff --git a/drivers/ram/sunxi/dram_sun20i_d1.h b/drivers/ram/sunxi/dram_sun20i_d1.h new file mode 100644 -index 0000000000..89aac9dade +index 0000000000..91383f6cf1 --- /dev/null +++ b/drivers/ram/sunxi/dram_sun20i_d1.h -@@ -0,0 +1,70 @@ +@@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * D1/R528/T113 DRAM controller register and constant defines @@ -1599,35 +1614,38 @@ index 0000000000..89aac9dade + */ +typedef struct dram_para { + /* normal configuration */ -+ u32 dram_clk; -+ u32 dram_type; -+ u32 dram_zq; -+ u32 dram_odt_en; ++ const u32 dram_clk; ++ const u32 dram_type; ++ const u32 dram_zq; ++ const u32 dram_odt_en; + ++ /* timing configuration */ ++ const u32 dram_mr0; ++ const u32 dram_mr1; ++ const u32 dram_mr2; ++ const u32 dram_mr3; ++ const u32 dram_tpr0; //DRAMTMG0 ++ const u32 dram_tpr1; //DRAMTMG1 ++ const u32 dram_tpr2; //DRAMTMG2 ++ const u32 dram_tpr3; //DRAMTMG3 ++ const u32 dram_tpr4; //DRAMTMG4 ++ const u32 dram_tpr5; //DRAMTMG5 ++ const u32 dram_tpr6; //DRAMTMG8 ++ const u32 dram_tpr7; ++ const u32 dram_tpr8; ++ const u32 dram_tpr9; ++ const u32 dram_tpr10; ++ const u32 dram_tpr11; ++ const u32 dram_tpr12; ++} dram_para_t; ++ ++typedef struct dram_config { + /* control configuration */ + u32 dram_para1; + u32 dram_para2; -+ -+ /* timing configuration */ -+ u32 dram_mr0; -+ u32 dram_mr1; -+ u32 dram_mr2; -+ u32 dram_mr3; -+ u32 dram_tpr0; //DRAMTMG0 -+ u32 dram_tpr1; //DRAMTMG1 -+ u32 dram_tpr2; //DRAMTMG2 -+ u32 dram_tpr3; //DRAMTMG3 -+ u32 dram_tpr4; //DRAMTMG4 -+ u32 dram_tpr5; //DRAMTMG5 -+ u32 dram_tpr6; //DRAMTMG8 -+ u32 dram_tpr7; -+ u32 dram_tpr8; -+ u32 dram_tpr9; -+ u32 dram_tpr10; -+ u32 dram_tpr11; -+ u32 dram_tpr12; -+ u32 dram_tpr13; /* contains a bitfield of DRAM setup settings */ -+} dram_para_t; ++ /* contains a bitfield of DRAM setup settings */ ++ u32 dram_tpr13; ++} dram_config_t; + +static inline int ns_to_t(int nanoseconds) +{ diff --git a/package/boot/uboot-sunxi/patches/4015-sunxi-add-early-Allwinner-R528-T113-SoC-support.patch b/package/boot/uboot-sunxi/patches/4022-sunxi-add-Allwinner-R528-T113-SoC-support.patch similarity index 83% rename from package/boot/uboot-sunxi/patches/4015-sunxi-add-early-Allwinner-R528-T113-SoC-support.patch rename to package/boot/uboot-sunxi/patches/4022-sunxi-add-Allwinner-R528-T113-SoC-support.patch index 32eb73ba8f..695926c52d 100644 --- a/package/boot/uboot-sunxi/patches/4015-sunxi-add-early-Allwinner-R528-T113-SoC-support.patch +++ b/package/boot/uboot-sunxi/patches/4022-sunxi-add-Allwinner-R528-T113-SoC-support.patch @@ -1,7 +1,7 @@ -From bc8f569427d231f9cd0f483474af870cafa857e4 Mon Sep 17 00:00:00 2001 +From 2caf5cf5bb2d34f07d4920eb5e4eacd07f66a27b Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Tue, 6 Sep 2022 15:59:57 +0100 -Subject: [PATCH 4015/4031] sunxi: add early Allwinner R528/T113 SoC support +Date: Fri, 21 Jul 2023 14:46:02 +0100 +Subject: [PATCH 4022/4044] sunxi: add Allwinner R528/T113 SoC support This adds the remaining code bits to teach U-Boot about Allwinner's newest SoC generation. This was introduced with the RISC-V based @@ -12,21 +12,19 @@ This adds the new Kconfig stanza, using the two newly introduced symbols for the new SoC generation and pincontroller. It also adds the new symbols to the relavent code places, to set all the hardcoded bits directly. -We just chicken out the DRAM controller code for now with a stub to make -it compile. There is GPLed code out there that can be used, although that -still looks very much like the disassembly/decompile it came from. - Signed-off-by: Andre Przywara +Tested-by: Maksim Kiselev --- arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 9 +++++++-- - arch/arm/mach-sunxi/Kconfig | 10 ++++++++++ + arch/arm/mach-sunxi/Kconfig | 11 +++++++++++ arch/arm/mach-sunxi/board.c | 8 ++++++++ arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 ++ arch/arm/mach-sunxi/cpu_info.c | 2 ++ common/spl/Kconfig | 1 + + drivers/clk/sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 1 + drivers/pinctrl/sunxi/Kconfig | 1 + - 8 files changed, 32 insertions(+), 2 deletions(-) + 9 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 8471e11aa0..a84a57e5b4 100644 @@ -63,10 +61,10 @@ index 8471e11aa0..a84a57e5b4 100644 /* apb2 bit field */ diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig -index 057b0ccd33..142d86afc6 100644 +index 60ca1239dd..77b510cdfe 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig -@@ -318,6 +318,15 @@ config MACH_SUN8I_R40 +@@ -316,6 +316,15 @@ config MACH_SUN8I_R40 select PHY_SUN4I_USB imply SPL_SYS_I2C_LEGACY @@ -82,7 +80,15 @@ index 057b0ccd33..142d86afc6 100644 config MACH_SUN8I_V3S bool "sun8i (Allwinner V3/V3s/S3/S3L)" select CPU_V7A -@@ -622,6 +631,7 @@ config SYS_CONFIG_NAME +@@ -612,6 +621,7 @@ config SYS_CLK_FREQ + default 1008000000 if MACH_SUN9I + default 888000000 if MACH_SUN50I_H6 + default 1008000000 if MACH_SUN50I_H616 ++ default 1008000000 if MACH_SUN8I_R528 + + config SYS_CONFIG_NAME + default "suniv" if MACH_SUNIV +@@ -620,6 +630,7 @@ config SYS_CONFIG_NAME default "sun6i" if MACH_SUN6I default "sun7i" if MACH_SUN7I default "sun8i" if MACH_SUN8I @@ -91,7 +97,7 @@ index 057b0ccd33..142d86afc6 100644 default "sun50i" if MACH_SUN50I default "sun50i" if MACH_SUN50I_H6 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c -index 6d96182226..df4f32d10c 100644 +index 51b8e708b0..8980ffb509 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void) @@ -117,10 +123,10 @@ index 6d96182226..df4f32d10c 100644 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c -index 607efe6a9c..4d5e23a9af 100644 +index c3a4623d34..bf21a71542 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c -@@ -38,7 +38,9 @@ void clock_init_safe(void) +@@ -52,7 +52,9 @@ void clock_init_safe(void) CCM_CPU_AXI_DEFAULT_FACTORS); writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); @@ -155,6 +161,18 @@ index 06bcedca7d..196a250ef9 100644 default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5 default 0x18000 if MACH_SUN9I default 0x8000 if ARCH_SUNXI +diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig +index f65e482ba4..8bdc094489 100644 +--- a/drivers/clk/sunxi/Kconfig ++++ b/drivers/clk/sunxi/Kconfig +@@ -89,6 +89,7 @@ config CLK_SUN8I_H3 + + config CLK_SUN20I_D1 + bool "Clock driver for Allwinner D1" ++ default MACH_SUN8I_R528 + help + This enables common clock driver support for platforms based + on Allwinner D1 SoC. diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index a8e590561c..0837e8bb30 100644 --- a/drivers/mmc/sunxi_mmc.c diff --git a/package/boot/uboot-sunxi/patches/4016-sunxi-refactor-serial-base-addresses-to-avoid-asm-ar.patch b/package/boot/uboot-sunxi/patches/4023-sunxi-refactor-serial-base-addresses-to-avoid-asm-ar.patch similarity index 89% rename from package/boot/uboot-sunxi/patches/4016-sunxi-refactor-serial-base-addresses-to-avoid-asm-ar.patch rename to package/boot/uboot-sunxi/patches/4023-sunxi-refactor-serial-base-addresses-to-avoid-asm-ar.patch index 6b9f8fa2af..387d3e1daa 100644 --- a/package/boot/uboot-sunxi/patches/4016-sunxi-refactor-serial-base-addresses-to-avoid-asm-ar.patch +++ b/package/boot/uboot-sunxi/patches/4023-sunxi-refactor-serial-base-addresses-to-avoid-asm-ar.patch @@ -1,7 +1,7 @@ -From 733d8e8ac84a4936cdd55a688f41dd8de10d870c Mon Sep 17 00:00:00 2001 +From 3322934ace5532df9a783c138471abd479ed2737 Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Sun, 3 Jul 2022 00:14:24 +0100 -Subject: [PATCH 4016/4031] sunxi: refactor serial base addresses to avoid +Date: Fri, 21 Jul 2023 14:46:03 +0100 +Subject: [PATCH 4023/4044] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h At the moment we have each SoC's memory map defined in its own cpu.h, @@ -20,16 +20,17 @@ Signed-off-by: Andre Przywara --- arch/arm/cpu/armv7/sunxi/sram.c | 1 + arch/arm/cpu/armv8/fel_utils.S | 1 + + arch/arm/include/asm/arch-sunxi/boot0.h | 2 ++ arch/arm/include/asm/arch-sunxi/clock.h | 1 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 15 --------- .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 5 --- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 7 ---- - .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 5 --- + .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 4 --- arch/arm/include/asm/arch-sunxi/serial.h | 32 +++++++++++++++++++ arch/arm/mach-sunxi/gtbus_sun9i.c | 1 + arch/arm/mach-sunxi/timer.c | 1 + include/configs/sunxi-common.h | 2 +- - 11 files changed, 38 insertions(+), 33 deletions(-) + 12 files changed, 40 insertions(+), 32 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/serial.h diff --git a/arch/arm/cpu/armv7/sunxi/sram.c b/arch/arm/cpu/armv7/sunxi/sram.c @@ -56,6 +57,19 @@ index 2fe38a1a04..939869b9ff 100644 /* * We don't overwrite save_boot_params() here, to save the FEL state upon +diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h +index 46b7e073b5..8ff7ca9b20 100644 +--- a/arch/arm/include/asm/arch-sunxi/boot0.h ++++ b/arch/arm/include/asm/arch-sunxi/boot0.h +@@ -3,6 +3,8 @@ + * Configuration settings for the Allwinner A64 (sun50i) CPU + */ + ++#include ++ + #if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) + /* reserve space for BOOT0 header information */ + b reset diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 3d34261b0e..fcc8966cb0 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h @@ -150,12 +164,12 @@ index 20025be231..2bf2675d5c 100644 /* Misc. */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h -index 13093085a5..d01508517c 100644 +index b13be2c4e8..961a3b37c9 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h -@@ -27,10 +27,6 @@ - #define SUNXI_MMC1_BASE 0x04021000 - #define SUNXI_MMC2_BASE 0x04022000 +@@ -10,10 +10,6 @@ + #define SUNXI_CCM_BASE 0x02001000 + #define SUNXI_TIMER_BASE 0x02050000 -#define SUNXI_UART0_BASE 0x02500000 -#define SUNXI_UART1_BASE 0x02500400 @@ -164,14 +178,6 @@ index 13093085a5..d01508517c 100644 #define SUNXI_TWI0_BASE 0x02502000 #define SUNXI_TWI1_BASE 0x02502400 #define SUNXI_TWI2_BASE 0x02502800 -@@ -42,7 +38,6 @@ - #define SUNXI_R_CPUCFG_BASE 0x07000400 - #define SUNXI_PRCM_BASE 0x07010000 - #define SUNXI_R_WDOG_BASE 0x07020400 --#define SUNXI_R_UART_BASE 0x07080000 - #define SUNXI_R_TWI_BASE 0x07081400 - - #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-sunxi/serial.h b/arch/arm/include/asm/arch-sunxi/serial.h new file mode 100644 index 0000000000..9386287b65 diff --git a/package/boot/uboot-sunxi/patches/4017-riscv-dts-allwinner-Add-the-D1-D1s-SoC-devicetree.patch b/package/boot/uboot-sunxi/patches/4024-riscv-dts-allwinner-Add-the-D1-D1s-SoC-devicetree.patch similarity index 97% rename from package/boot/uboot-sunxi/patches/4017-riscv-dts-allwinner-Add-the-D1-D1s-SoC-devicetree.patch rename to package/boot/uboot-sunxi/patches/4024-riscv-dts-allwinner-Add-the-D1-D1s-SoC-devicetree.patch index a08a6d126a..3d718843cd 100644 --- a/package/boot/uboot-sunxi/patches/4017-riscv-dts-allwinner-Add-the-D1-D1s-SoC-devicetree.patch +++ b/package/boot/uboot-sunxi/patches/4024-riscv-dts-allwinner-Add-the-D1-D1s-SoC-devicetree.patch @@ -1,7 +1,7 @@ -From d25ac8934d210132b1df15bd63301646eb43d57e Mon Sep 17 00:00:00 2001 +From ebd383f6a25566c6a0e72f702eb826182929cd2b Mon Sep 17 00:00:00 2001 From: Samuel Holland -Date: Wed, 25 Jan 2023 22:57:31 -0600 -Subject: [PATCH 4017/4031] riscv: dts: allwinner: Add the D1/D1s SoC +Date: Fri, 21 Jul 2023 14:46:04 +0100 +Subject: [PATCH 4024/4044] riscv: dts: allwinner: Add the D1/D1s SoC devicetree D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based @@ -31,10 +31,10 @@ Signed-off-by: Samuel Holland arch/riscv/dts/sun20i-d1.dtsi | 66 ++ arch/riscv/dts/sun20i-d1s.dtsi | 76 ++ arch/riscv/dts/sunxi-d1-t113.dtsi | 15 + - arch/riscv/dts/sunxi-d1s-t113.dtsi | 834 +++++++++++++++++++ + arch/riscv/dts/sunxi-d1s-t113.dtsi | 846 +++++++++++++++++++ include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 + include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 + - 7 files changed, 1054 insertions(+) + 7 files changed, 1066 insertions(+) create mode 100644 arch/riscv/dts/sun20i-common-regulators.dtsi create mode 100644 arch/riscv/dts/sun20i-d1.dtsi create mode 100644 arch/riscv/dts/sun20i-d1s.dtsi @@ -254,10 +254,10 @@ index 0000000000..b7156123df +}; diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi new file mode 100644 -index 0000000000..6fadcee780 +index 0000000000..922e8e0e2c --- /dev/null +++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi -@@ -0,0 +1,834 @@ +@@ -0,0 +1,846 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + @@ -471,7 +471,7 @@ index 0000000000..6fadcee780 + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; -+ dma-names = "rx", "tx"; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + @@ -484,7 +484,7 @@ index 0000000000..6fadcee780 + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; -+ dma-names = "rx", "tx"; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + @@ -497,7 +497,7 @@ index 0000000000..6fadcee780 + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; -+ dma-names = "rx", "tx"; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + @@ -510,7 +510,7 @@ index 0000000000..6fadcee780 + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; -+ dma-names = "rx", "tx"; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + @@ -523,7 +523,7 @@ index 0000000000..6fadcee780 + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + dmas = <&dma 18>, <&dma 18>; -+ dma-names = "rx", "tx"; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + @@ -536,7 +536,7 @@ index 0000000000..6fadcee780 + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + dmas = <&dma 19>, <&dma 19>; -+ dma-names = "rx", "tx"; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + @@ -627,6 +627,18 @@ index 0000000000..6fadcee780 + #size-cells = <1>; + }; + ++ crypto: crypto@3040000 { ++ compatible = "allwinner,sun20i-d1-crypto"; ++ reg = <0x3040000 0x800>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CE>, ++ <&ccu CLK_CE>, ++ <&ccu CLK_MBUS_CE>, ++ <&rtc CLK_IOSC>; ++ clock-names = "bus", "mod", "ram", "trng"; ++ resets = <&ccu RST_BUS_CE>; ++ }; ++ + mbus: dram-controller@3102000 { + compatible = "allwinner,sun20i-d1-mbus"; + reg = <0x3102000 0x1000>, diff --git a/package/boot/uboot-sunxi/patches/4018-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch b/package/boot/uboot-sunxi/patches/4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch similarity index 68% rename from package/boot/uboot-sunxi/patches/4018-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch rename to package/boot/uboot-sunxi/patches/4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch index 9da865bdf0..da52b7db19 100644 --- a/package/boot/uboot-sunxi/patches/4018-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch +++ b/package/boot/uboot-sunxi/patches/4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch @@ -1,7 +1,7 @@ -From 3db4754246274bc530d008f54fc686db8425479f Mon Sep 17 00:00:00 2001 +From 32020fad9d2fc6ce8f6e67af2ac7c9c6e7c47dec Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Tue, 3 Jan 2023 16:04:47 +0000 -Subject: [PATCH 4018/4031] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi +Date: Fri, 21 Jul 2023 14:46:05 +0100 +Subject: [PATCH 4025/4044] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi The Allwinner T113-s SoC is apparently using the same (or at least a very similar) die as the D1/D1s, but replaces the single RISC-V core with @@ -11,10 +11,18 @@ just need a DT describing the ARM specific peripherals: the CPU cores, the Generic Timer, the GIC and the PMU. We include the core .dtsi directly from the riscv DT directory. +The ARM core version of the DT specifies the CPUX watchdog as +"reserved", which means it won't be recognised by U-Boot. Override this +in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog, +so that the generic reset driver will work. + Signed-off-by: Andre Przywara +Reviewed-by: Sam Edwards +Tested-by: Sam Edwards --- - arch/arm/dts/sun8i-t113s.dtsi | 59 +++++++++++++++++++++++++++++++++++ - 1 file changed, 59 insertions(+) + arch/arm/dts/sun8i-t113s.dtsi | 59 ++++++++++++++++++++++++++++++++++ + arch/arm/dts/sunxi-u-boot.dtsi | 7 ++++ + 2 files changed, 66 insertions(+) create mode 100644 arch/arm/dts/sun8i-t113s.dtsi diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-t113s.dtsi @@ -82,6 +90,24 @@ index 0000000000..ce00883130 + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; +diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi +index e959eb2a40..27de5b8eac 100644 +--- a/arch/arm/dts/sunxi-u-boot.dtsi ++++ b/arch/arm/dts/sunxi-u-boot.dtsi +@@ -23,6 +23,13 @@ + }; + }; + ++/* Let U-Boot be the firmware layer that controls the watchdog. */ ++#ifdef CONFIG_MACH_SUN8I_R528 ++&wdt { ++ status = "okay"; ++}; ++#endif ++ + &binman { + u-boot-sunxi-with-spl { + filename = "u-boot-sunxi-with-spl.bin"; -- 2.20.1 diff --git a/package/boot/uboot-sunxi/patches/4019-sunxi-add-preliminary-MangoPi-MQ-R-board-support.patch b/package/boot/uboot-sunxi/patches/4026-sunxi-add-MangoPi-MQ-R-board-support.patch similarity index 92% rename from package/boot/uboot-sunxi/patches/4019-sunxi-add-preliminary-MangoPi-MQ-R-board-support.patch rename to package/boot/uboot-sunxi/patches/4026-sunxi-add-MangoPi-MQ-R-board-support.patch index 86bb2f3159..a403d0c74b 100644 --- a/package/boot/uboot-sunxi/patches/4019-sunxi-add-preliminary-MangoPi-MQ-R-board-support.patch +++ b/package/boot/uboot-sunxi/patches/4026-sunxi-add-MangoPi-MQ-R-board-support.patch @@ -1,18 +1,18 @@ -From 61b9b6b87af8e7eed501155803620083f6dff849 Mon Sep 17 00:00:00 2001 +From 3cab8f3bd34a0d16fca67ad10ec2ad413fdc99da Mon Sep 17 00:00:00 2001 From: Andre Przywara -Date: Fri, 2 Dec 2022 16:11:36 +0000 -Subject: [PATCH 4019/4031] sunxi: add preliminary MangoPi MQ-R board support +Date: Fri, 21 Jul 2023 14:46:06 +0100 +Subject: [PATCH 4026/4044] sunxi: add MangoPi MQ-R board support -This includes a preliminary basic DT and a defconfig to get the board -booted. +This copies the T113s specific DTs from the Linux kernel tree +(v6.4-rc1), and adds a defconfig to get the board booted. Signed-off-by: Andre Przywara --- arch/arm/dts/Makefile | 2 + .../arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 +++++ arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi | 126 ++++++++++++++++++ - configs/mangopi_mq_r_defconfig | 17 +++ - 4 files changed, 180 insertions(+) + configs/mangopi_mq_r_defconfig | 15 +++ + 4 files changed, 178 insertions(+) create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts create mode 100644 arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi create mode 100644 configs/mangopi_mq_r_defconfig @@ -205,27 +205,25 @@ index 0000000000..e9bc749488 +}; diff --git a/configs/mangopi_mq_r_defconfig b/configs/mangopi_mq_r_defconfig new file mode 100644 -index 0000000000..28bbfde602 +index 0000000000..66ae639326 --- /dev/null +++ b/configs/mangopi_mq_r_defconfig -@@ -0,0 +1,17 @@ +@@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-mangopi-mq-r-t113" -+CONFIG_SUNXI_MINIMUM_DRAM_MB=128 +CONFIG_SPL=y +CONFIG_MACH_SUN8I_R528=y -+CONFIG_CONS_INDEX=4 -+CONFIG_MMC0_CD_PIN="PF6" -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_DRAM_CLK=792 +CONFIG_DRAM_ZQ=8092667 ++CONFIG_SUNXI_MINIMUM_DRAM_MB=128 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_DRAM_SUNXI_ODT_EN=0 +CONFIG_DRAM_SUNXI_TPR0=0x004a2195 +CONFIG_DRAM_SUNXI_TPR11=0x340000 +CONFIG_DRAM_SUNXI_TPR12=0x46 +CONFIG_DRAM_SUNXI_TPR13=0x34000100 ++CONFIG_CONS_INDEX=4 -- 2.20.1 diff --git a/package/boot/uboot-sunxi/patches/4020-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch b/package/boot/uboot-sunxi/patches/4027-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch similarity index 79% rename from package/boot/uboot-sunxi/patches/4020-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch rename to package/boot/uboot-sunxi/patches/4027-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch index 3c26b0d80a..cd4a7daaef 100644 --- a/package/boot/uboot-sunxi/patches/4020-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch +++ b/package/boot/uboot-sunxi/patches/4027-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch @@ -1,7 +1,7 @@ -From c20401da0fe90a790f47e70cf79f43551adf76b9 Mon Sep 17 00:00:00 2001 +From f9950a4c4cbabde0c07f4b2e3fdeee52b0c1f788 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sat, 3 Jun 2023 00:52:04 +0200 -Subject: [PATCH 4020/4031] sunxi: add uart0_pins on Port E PE2/PE3 on D1s/T133 +Subject: [PATCH 4027/4044] sunxi: add uart0_pins on Port E PE2/PE3 on D1s/T133 Signed-off-by: Zoltan HERPAI --- @@ -9,7 +9,7 @@ Signed-off-by: Zoltan HERPAI 1 file changed, 6 insertions(+) diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi -index 6fadcee780..2b7d54aab4 100644 +index 922e8e0e2c..b1f97bd0bc 100644 --- a/arch/riscv/dts/sunxi-d1s-t113.dtsi +++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi @@ -125,6 +125,12 @@ diff --git a/package/boot/uboot-sunxi/patches/4021-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch b/package/boot/uboot-sunxi/patches/4028-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch similarity index 95% rename from package/boot/uboot-sunxi/patches/4021-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch rename to package/boot/uboot-sunxi/patches/4028-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch index 1e869ddd07..5882c4fb6f 100644 --- a/package/boot/uboot-sunxi/patches/4021-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch +++ b/package/boot/uboot-sunxi/patches/4028-sunxi-add-support-for-MangoPI-MQDual-T113-variant.patch @@ -1,7 +1,7 @@ -From 9c4f13ffba3c53b1d4beb8cdb71f658b80692b15 Mon Sep 17 00:00:00 2001 +From b4f63d64a10847dc64c456ddcf262ac5c5eea616 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sat, 3 Jun 2023 00:52:40 +0200 -Subject: [PATCH 4021/4031] sunxi: add support for MangoPI MQDual T113 variant +Subject: [PATCH 4028/4044] sunxi: add support for MangoPI MQDual T113 variant Signed-off-by: Zoltan HERPAI --- diff --git a/package/boot/uboot-sunxi/patches/4022-sunxi-add-support-for-UART5-in-Port-E-group-on-T133.patch b/package/boot/uboot-sunxi/patches/4029-sunxi-add-support-for-UART5-in-Port-E-group-on-T133.patch similarity index 94% rename from package/boot/uboot-sunxi/patches/4022-sunxi-add-support-for-UART5-in-Port-E-group-on-T133.patch rename to package/boot/uboot-sunxi/patches/4029-sunxi-add-support-for-UART5-in-Port-E-group-on-T133.patch index 8be15ff285..040feb3716 100644 --- a/package/boot/uboot-sunxi/patches/4022-sunxi-add-support-for-UART5-in-Port-E-group-on-T133.patch +++ b/package/boot/uboot-sunxi/patches/4029-sunxi-add-support-for-UART5-in-Port-E-group-on-T133.patch @@ -1,7 +1,7 @@ -From 34ee938e52f219912dd9c2333ce2174860201290 Mon Sep 17 00:00:00 2001 +From c58e825d57bff0f9124f3afbcbad4a5c06d3670f Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sat, 3 Jun 2023 23:41:31 +0200 -Subject: [PATCH 4022/4031] sunxi: add support for UART5 in Port E group on +Subject: [PATCH 4029/4044] sunxi: add support for UART5 in Port E group on T133 Signed-off-by: Zoltan HERPAI @@ -25,7 +25,7 @@ index 9386287b65..48d0f42a3b 100644 #define SUNXI_UART0_BASE 0x01c28000 #define SUNXI_R_UART_BASE 0x01f02800 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c -index df4f32d10c..6a37b33767 100644 +index 8980ffb509..50693d216b 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -175,6 +175,10 @@ static int gpio_init(void) diff --git a/package/boot/uboot-sunxi/patches/4023-sunxi-add-MYIR-MYD-YT113X-board.patch b/package/boot/uboot-sunxi/patches/4030-sunxi-add-MYIR-MYD-YT113X-board.patch similarity index 76% rename from package/boot/uboot-sunxi/patches/4023-sunxi-add-MYIR-MYD-YT113X-board.patch rename to package/boot/uboot-sunxi/patches/4030-sunxi-add-MYIR-MYD-YT113X-board.patch index fe44e8c448..331ddd8822 100644 --- a/package/boot/uboot-sunxi/patches/4023-sunxi-add-MYIR-MYD-YT113X-board.patch +++ b/package/boot/uboot-sunxi/patches/4030-sunxi-add-MYIR-MYD-YT113X-board.patch @@ -1,14 +1,14 @@ -From 8e178708d913eb1f4b40661519944db779d0476b Mon Sep 17 00:00:00 2001 +From 542c6069f64d4e97c68007bb7e22c030ab7f9526 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sun, 4 Jun 2023 00:13:45 +0200 -Subject: [PATCH 4023/4031] sunxi: add MYIR MYD-YT113X board +Subject: [PATCH 4030/4044] sunxi: add MYIR MYD-YT113X board Signed-off-by: Zoltan HERPAI --- arch/arm/dts/Makefile | 3 +- - arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts | 48 ++++++++++++++++++++ - configs/myir_myd_t113x_defconfig | 17 +++++++ - 3 files changed, 67 insertions(+), 1 deletion(-) + arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts | 68 ++++++++++++++++++++ + configs/myir_myd_t113x_defconfig | 19 ++++++ + 3 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts create mode 100644 configs/myir_myd_t113x_defconfig @@ -28,10 +28,10 @@ index 4207f17601..6fb49de59a 100644 sun50i-h5-emlid-neutis-n5-devboard.dtb \ diff --git a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts new file mode 100644 -index 0000000000..1c568b4cee +index 0000000000..afd0d8f532 --- /dev/null +++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts -@@ -0,0 +1,48 @@ +@@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + @@ -63,6 +63,26 @@ index 0000000000..1c568b4cee + cpu-supply = <®_vcc_core>; +}; + ++&mmc2_pins { ++ bias-pull-up; ++ drive-strength = <40>; ++}; ++ ++&mmc2 { ++ pinctrl-0 = <&mmc2_pins>; ++ pinctrl-names = "default"; ++ vmmc-supply = <®_3v3>; ++ non-removable; ++ bus-width = <4>; ++ status = "okay"; ++ ++ emmc: emmc@0 { ++ reg = <0>; ++ compatible = "mmc-card"; ++ broken-hpi; ++ }; ++}; ++ +&pio { + /omit-if-no-ref/ + uart5_pins: uart5-pins { @@ -82,10 +102,10 @@ index 0000000000..1c568b4cee +}; diff --git a/configs/myir_myd_t113x_defconfig b/configs/myir_myd_t113x_defconfig new file mode 100644 -index 0000000000..dc652732e3 +index 0000000000..21f939272a --- /dev/null +++ b/configs/myir_myd_t113x_defconfig -@@ -0,0 +1,17 @@ +@@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-myir-myd-yt113x" @@ -94,6 +114,7 @@ index 0000000000..dc652732e3 +CONFIG_MACH_SUN8I_R528=y +CONFIG_CONS_INDEX=6 +CONFIG_MMC0_CD_PIN="PF6" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_DRAM_CLK=792 @@ -103,6 +124,8 @@ index 0000000000..dc652732e3 +CONFIG_DRAM_SUNXI_TPR11=0x340000 +CONFIG_DRAM_SUNXI_TPR12=0x46 +CONFIG_DRAM_SUNXI_TPR13=0x34000100 ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y -- 2.20.1 diff --git a/package/boot/uboot-sunxi/patches/4024-sunxi-add-support-for-UART3-on-PE-pins.patch b/package/boot/uboot-sunxi/patches/4031-sunxi-add-support-for-UART3-on-PE-pins.patch similarity index 92% rename from package/boot/uboot-sunxi/patches/4024-sunxi-add-support-for-UART3-on-PE-pins.patch rename to package/boot/uboot-sunxi/patches/4031-sunxi-add-support-for-UART3-on-PE-pins.patch index 9b57b684c7..4fa00b9037 100644 --- a/package/boot/uboot-sunxi/patches/4024-sunxi-add-support-for-UART3-on-PE-pins.patch +++ b/package/boot/uboot-sunxi/patches/4031-sunxi-add-support-for-UART3-on-PE-pins.patch @@ -1,7 +1,7 @@ -From 9dd404ee6108f09894d5ff60feedb713284ca617 Mon Sep 17 00:00:00 2001 +From 0c47a295e3d6f4611a152485fac63bb2b64369e8 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sat, 3 Jun 2023 23:57:46 +0200 -Subject: [PATCH 4024/4031] sunxi: add support for UART3 on PE pins +Subject: [PATCH 4031/4044] sunxi: add support for UART3 on PE pins Some boards use Port E pins for muxing the UART3 as console. Add a new Kconfig option allowing to select this (mimicking MMC_PINS_PH). @@ -17,10 +17,10 @@ Signed-off-by: Zoltan HERPAI 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig -index 142d86afc6..59fa62c8d5 100644 +index 77b510cdfe..1ddf496a55 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig -@@ -665,6 +665,12 @@ config UART0_PORT_F +@@ -664,6 +664,12 @@ config UART0_PORT_F at the same time, the system can be only booted in the FEL mode. Only enable this if you really know what you are doing. @@ -34,7 +34,7 @@ index 142d86afc6..59fa62c8d5 100644 bool "Enable workarounds for booting old kernels" ---help--- diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c -index 6a37b33767..5de490feda 100644 +index 50693d216b..85dbad0552 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -168,16 +168,22 @@ static int gpio_init(void) @@ -63,7 +63,7 @@ index 6a37b33767..5de490feda 100644 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ !defined(CONFIG_MACH_SUN8I_R40) diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi -index 2b7d54aab4..d858f21fd2 100644 +index b1f97bd0bc..b72bbc5e43 100644 --- a/arch/riscv/dts/sunxi-d1s-t113.dtsi +++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi @@ -126,6 +126,12 @@ diff --git a/package/boot/uboot-sunxi/patches/4025-sunxi-add-support-for-Rongpin-RP-T113-board.patch b/package/boot/uboot-sunxi/patches/4032-sunxi-add-support-for-Rongpin-RP-T113-board.patch similarity index 96% rename from package/boot/uboot-sunxi/patches/4025-sunxi-add-support-for-Rongpin-RP-T113-board.patch rename to package/boot/uboot-sunxi/patches/4032-sunxi-add-support-for-Rongpin-RP-T113-board.patch index 45cd5300e0..1e814982ec 100644 --- a/package/boot/uboot-sunxi/patches/4025-sunxi-add-support-for-Rongpin-RP-T113-board.patch +++ b/package/boot/uboot-sunxi/patches/4032-sunxi-add-support-for-Rongpin-RP-T113-board.patch @@ -1,7 +1,7 @@ -From d3a69c14de1b3b2e61bfeb421f0f0f4ecec1207e Mon Sep 17 00:00:00 2001 +From 11fe7200d693e88d1f648fd000c327dcc529fa28 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sat, 3 Jun 2023 23:42:33 +0200 -Subject: [PATCH 4025/4031] sunxi: add support for Rongpin RP-T113 board +Subject: [PATCH 4032/4044] sunxi: add support for Rongpin RP-T113 board Signed-off-by: Zoltan HERPAI --- diff --git a/package/boot/uboot-sunxi/patches/4026-net-add-ICPlus-PHY-driver.patch b/package/boot/uboot-sunxi/patches/4033-net-add-ICPlus-PHY-driver.patch similarity index 97% rename from package/boot/uboot-sunxi/patches/4026-net-add-ICPlus-PHY-driver.patch rename to package/boot/uboot-sunxi/patches/4033-net-add-ICPlus-PHY-driver.patch index 7530e946b2..210ff9ea3a 100644 --- a/package/boot/uboot-sunxi/patches/4026-net-add-ICPlus-PHY-driver.patch +++ b/package/boot/uboot-sunxi/patches/4033-net-add-ICPlus-PHY-driver.patch @@ -1,7 +1,7 @@ -From 7dbc707b5911c28724c2f5a220315513bf9ce3f3 Mon Sep 17 00:00:00 2001 +From daa5621013e06419c90bf27b5c88b8036af2b3da Mon Sep 17 00:00:00 2001 From: Yegor Yefremov Date: Wed, 28 Nov 2012 11:15:18 +0100 -Subject: [PATCH 4026/4031] net: add ICPlus PHY driver +Subject: [PATCH 4033/4044] net: add ICPlus PHY driver The driver code was taken from Linux kernel source: drivers/net/phy/icplus.c diff --git a/package/boot/uboot-sunxi/patches/4027-sunxi-enable-emac-on-Rongpin-RP-T113.patch b/package/boot/uboot-sunxi/patches/4034-sunxi-enable-emac-on-Rongpin-RP-T113.patch similarity index 95% rename from package/boot/uboot-sunxi/patches/4027-sunxi-enable-emac-on-Rongpin-RP-T113.patch rename to package/boot/uboot-sunxi/patches/4034-sunxi-enable-emac-on-Rongpin-RP-T113.patch index a93f0bf49f..31ec113d53 100644 --- a/package/boot/uboot-sunxi/patches/4027-sunxi-enable-emac-on-Rongpin-RP-T113.patch +++ b/package/boot/uboot-sunxi/patches/4034-sunxi-enable-emac-on-Rongpin-RP-T113.patch @@ -1,7 +1,7 @@ -From 789c1062934120dcbf4f88a867638f23dcfc1c39 Mon Sep 17 00:00:00 2001 +From 7d987c1284c883d31090e940dbec78fb2a66ea60 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sun, 4 Jun 2023 15:40:42 +0200 -Subject: [PATCH 4027/4031] sunxi: enable emac on Rongpin RP-T113 +Subject: [PATCH 4034/4044] sunxi: enable emac on Rongpin RP-T113 The emac is connected to an IC+ IP101 PHY, for which the driver has been re-added (it was removed in 2014). diff --git a/package/boot/uboot-sunxi/patches/4028-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch b/package/boot/uboot-sunxi/patches/4035-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch similarity index 99% rename from package/boot/uboot-sunxi/patches/4028-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch rename to package/boot/uboot-sunxi/patches/4035-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch index dc3a82aa48..4bc5653cd9 100644 --- a/package/boot/uboot-sunxi/patches/4028-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch +++ b/package/boot/uboot-sunxi/patches/4035-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch @@ -1,7 +1,7 @@ -From 9dd54fb43abdb66b42679eb668612b9e055a962e Mon Sep 17 00:00:00 2001 +From 1b83ab458f7e8971576c9f1ac884eb9e6de4d0cd Mon Sep 17 00:00:00 2001 From: Yanhong Wang Date: Thu, 25 May 2023 17:36:27 +0800 -Subject: [PATCH 4028/4031] net: phy: Add driver for Motorcomm yt8531 gigabit +Subject: [PATCH 4035/4044] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have diff --git a/package/boot/uboot-sunxi/patches/4029-sunxi-enable-gmac-on-MYIR-MYD-YT113X-with-the-YT8531.patch b/package/boot/uboot-sunxi/patches/4036-sunxi-enable-gmac-on-MYIR-MYD-YT113X-with-the-YT8531.patch similarity index 55% rename from package/boot/uboot-sunxi/patches/4029-sunxi-enable-gmac-on-MYIR-MYD-YT113X-with-the-YT8531.patch rename to package/boot/uboot-sunxi/patches/4036-sunxi-enable-gmac-on-MYIR-MYD-YT113X-with-the-YT8531.patch index 2e4654e679..daf42810c6 100644 --- a/package/boot/uboot-sunxi/patches/4029-sunxi-enable-gmac-on-MYIR-MYD-YT113X-with-the-YT8531.patch +++ b/package/boot/uboot-sunxi/patches/4036-sunxi-enable-gmac-on-MYIR-MYD-YT113X-with-the-YT8531.patch @@ -1,7 +1,7 @@ -From 98a8ab5c4b9695d806f5e0d0d8db9935fe7ed6f8 Mon Sep 17 00:00:00 2001 +From 7530416165eb2a6c7378f7bb4a90fdf67439277d Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Mon, 5 Jun 2023 17:57:15 +0200 -Subject: [PATCH 4029/4031] sunxi: enable gmac on MYIR MYD-YT113X with the +Subject: [PATCH 4036/4044] sunxi: enable gmac on MYIR MYD-YT113X with the YT8531 PHY The gmac is connected to a Motorcomm YT8531, for which the driver @@ -11,21 +11,26 @@ Support is not yet added in DTS, only for compile testing. Signed-off-by: Zoltan HERPAI --- - configs/myir_myd_t113x_defconfig | 4 ++++ - 1 file changed, 4 insertions(+) + configs/myir_myd_t113x_defconfig | 10 ++++++++++ + 1 file changed, 10 insertions(+) diff --git a/configs/myir_myd_t113x_defconfig b/configs/myir_myd_t113x_defconfig -index dc652732e3..ad2b59ed70 100644 +index 21f939272a..088196389a 100644 --- a/configs/myir_myd_t113x_defconfig +++ b/configs/myir_myd_t113x_defconfig -@@ -15,3 +15,7 @@ CONFIG_DRAM_SUNXI_TPR0=0x004a2195 - CONFIG_DRAM_SUNXI_TPR11=0x340000 - CONFIG_DRAM_SUNXI_TPR12=0x46 +@@ -17,3 +17,12 @@ CONFIG_DRAM_SUNXI_TPR12=0x46 CONFIG_DRAM_SUNXI_TPR13=0x34000100 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_SUN8I_EMAC=y +CONFIG_RGMII=y +CONFIG_RMII=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_IO_VOLTAGE=y ++CONFIG_SPL_MMC_IO_VOLTAGE=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_SPL_MMC_HS200_SUPPORT=y -- 2.20.1 diff --git a/package/boot/uboot-sunxi/patches/4030-net-phy-backport-and-update-driver-for-Motorcomm-yt8.patch b/package/boot/uboot-sunxi/patches/4037-net-phy-backport-and-update-driver-for-Motorcomm-yt8.patch similarity index 93% rename from package/boot/uboot-sunxi/patches/4030-net-phy-backport-and-update-driver-for-Motorcomm-yt8.patch rename to package/boot/uboot-sunxi/patches/4037-net-phy-backport-and-update-driver-for-Motorcomm-yt8.patch index 4f4ca8d405..f93b764a00 100644 --- a/package/boot/uboot-sunxi/patches/4030-net-phy-backport-and-update-driver-for-Motorcomm-yt8.patch +++ b/package/boot/uboot-sunxi/patches/4037-net-phy-backport-and-update-driver-for-Motorcomm-yt8.patch @@ -1,7 +1,7 @@ -From 099cca9ab11daf77d1b8e5864ebb3b08a41b94fb Mon Sep 17 00:00:00 2001 +From 05b11cc62c2c6e523636143b6db255fa98b77de3 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Mon, 5 Jun 2023 18:15:15 +0200 -Subject: [PATCH 4030/4031] net: phy: backport and update driver for Motorcomm +Subject: [PATCH 4037/4044] net: phy: backport and update driver for Motorcomm yt8531 phy Don't use U_BOOT_PHY_DRIVER yet. diff --git a/package/boot/uboot-sunxi/patches/4031-sunxi-rongpin-rp-t113-add-missing-gpio.h-include.patch b/package/boot/uboot-sunxi/patches/4038-sunxi-rongpin-rp-t113-add-missing-gpio.h-include.patch similarity index 83% rename from package/boot/uboot-sunxi/patches/4031-sunxi-rongpin-rp-t113-add-missing-gpio.h-include.patch rename to package/boot/uboot-sunxi/patches/4038-sunxi-rongpin-rp-t113-add-missing-gpio.h-include.patch index 805d6f526a..7040d88717 100644 --- a/package/boot/uboot-sunxi/patches/4031-sunxi-rongpin-rp-t113-add-missing-gpio.h-include.patch +++ b/package/boot/uboot-sunxi/patches/4038-sunxi-rongpin-rp-t113-add-missing-gpio.h-include.patch @@ -1,7 +1,7 @@ -From 4481a2790ed667a206203ecf3fd8f8bbcf35d062 Mon Sep 17 00:00:00 2001 +From 808463e5b8f77b2daaa9a2a7d8aefbdbbad16141 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Mon, 5 Jun 2023 18:29:41 +0200 -Subject: [PATCH 4031/4031] sunxi: rongpin-rp-t113: add missing gpio.h include +Subject: [PATCH 4038/4044] sunxi: rongpin-rp-t113: add missing gpio.h include Signed-off-by: Zoltan HERPAI --- diff --git a/package/boot/uboot-sunxi/patches/4039-sunxi-SPL-SPI-Add-SPI-boot-support-for-the-Allwinner.patch b/package/boot/uboot-sunxi/patches/4039-sunxi-SPL-SPI-Add-SPI-boot-support-for-the-Allwinner.patch new file mode 100644 index 0000000000..64bcc72db4 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4039-sunxi-SPL-SPI-Add-SPI-boot-support-for-the-Allwinner.patch @@ -0,0 +1,206 @@ +From 2392217ef179219a41246e883a52dc64fcfede2a Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Fri, 19 May 2023 16:40:07 +0300 +Subject: [PATCH 4039/4044] sunxi: SPL SPI: Add SPI boot support for the + Allwinner R528/T113 SoCs + +R528/T113 SoCs uses the same SPI IP as the H6, also have the same clocks +and reset bits layout, but the CCU base is different. Another difference +is that the new SoCs do not have a clock divider inside. Instead of this +we should configure sample mode depending on input clock rate. + +The pin assignment is also different: the H6 uses PC0, the R528/T113 PC4 +instead. This makes for a change in spi0_pinmux_setup() routine. + +This patch extends the H6/H616 #ifdef guards to also cover the R528/T113, +using the shared CONFIG_SUNXI_GEN_NCAT2 and CONFIG_MACH_SUN8I_R528 +symbols. Also use CONFIG_SUNXI_GEN_NCAT2 symbol for the Kconfig +dependency. + +Signed-off-by: Maxim Kiselev +Tested-by: Sam Edwards +--- + arch/arm/mach-sunxi/Kconfig | 2 +- + arch/arm/mach-sunxi/spl_spi_sunxi.c | 78 +++++++++++++++++++++-------- + 2 files changed, 58 insertions(+), 22 deletions(-) + +diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig +index 1ddf496a55..d914066298 100644 +--- a/arch/arm/mach-sunxi/Kconfig ++++ b/arch/arm/mach-sunxi/Kconfig +@@ -1003,7 +1003,7 @@ config SPL_STACK_R_ADDR + + config SPL_SPI_SUNXI + bool "Support for SPI Flash on Allwinner SoCs in SPL" +- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV ++ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2 + help + Enable support for SPI Flash. This option allows SPL to read from + sunxi SPI Flash. It uses the same method as the boot ROM, so does +diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c +index c2410dd7bb..3cfbf56d59 100644 +--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c ++++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c +@@ -73,18 +73,27 @@ + #define SUN6I_CTL_ENABLE BIT(0) + #define SUN6I_CTL_MASTER BIT(1) + #define SUN6I_CTL_SRST BIT(31) ++#define SUN6I_TCR_SDM BIT(13) + #define SUN6I_TCR_XCH BIT(31) + + /*****************************************************************************/ + +-#define CCM_AHB_GATING0 (0x01C20000 + 0x60) +-#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) +-#ifdef CONFIG_SUN50I_GEN_H6 +-#define CCM_SPI0_CLK (0x03001000 + 0x940) ++#if defined(CONFIG_SUN50I_GEN_H6) ++#define CCM_BASE 0x03001000 ++#elif defined(CONFIG_SUNXI_GEN_NCAT2) ++#define CCM_BASE 0x02001000 + #else +-#define CCM_SPI0_CLK (0x01C20000 + 0xA0) ++#define CCM_BASE 0x01C20000 + #endif +-#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) ++ ++#define CCM_AHB_GATING0 (CCM_BASE + 0x60) ++#define CCM_H6_SPI_BGR_REG (CCM_BASE + 0x96c) ++#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) ++#define CCM_SPI0_CLK (CCM_BASE + 0x940) ++#else ++#define CCM_SPI0_CLK (CCM_BASE + 0xA0) ++#endif ++#define SUN6I_BUS_SOFT_RST_REG0 (CCM_BASE + 0x2C0) + + #define AHB_RESET_SPI0_SHIFT 20 + #define AHB_GATE_OFFSET_SPI0 20 +@@ -102,17 +111,22 @@ + */ + static void spi0_pinmux_setup(unsigned int pin_function) + { +- /* All chips use PC0 and PC2. */ +- sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); ++ /* All chips use PC2. And all chips use PC0, except R528/T113 */ ++ if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) ++ sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); ++ + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); + +- /* All chips except H6 and H616 use PC1. */ +- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) ++ /* All chips except H6/H616/R528/T113 use PC1. */ ++ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && ++ !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); + +- if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) ++ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || ++ IS_ENABLED(CONFIG_MACH_SUN8I_R528)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); +- if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) ++ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || ++ IS_ENABLED(CONFIG_MACH_SUN8I_R528)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); + + /* Older generations use PC23 for CS, newer ones use PC3. */ +@@ -126,7 +140,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) + static bool is_sun6i_gen_spi(void) + { + return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || +- IS_ENABLED(CONFIG_SUN50I_GEN_H6); ++ IS_ENABLED(CONFIG_SUN50I_GEN_H6) || ++ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2); + } + + static uintptr_t spi0_base_address(void) +@@ -137,6 +152,9 @@ static uintptr_t spi0_base_address(void) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + return 0x05010000; + ++ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) ++ return 0x04025000; ++ + if (!is_sun6i_gen_spi() || + IS_ENABLED(CONFIG_MACH_SUNIV)) + return 0x01C05000; +@@ -152,23 +170,30 @@ static void spi0_enable_clock(void) + uintptr_t base = spi0_base_address(); + + /* Deassert SPI0 reset on SUN6I */ +- if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) ++ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || ++ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); + else if (is_sun6i_gen_spi()) + setbits_le32(SUN6I_BUS_SOFT_RST_REG0, + (1 << AHB_RESET_SPI0_SHIFT)); + + /* Open the SPI0 gate */ +- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) ++ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && ++ !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + + if (IS_ENABLED(CONFIG_MACH_SUNIV)) { + /* Divide by 32, clock source is AHB clock 200MHz */ + writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL); + } else { +- /* Divide by 4 */ +- writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? +- SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); ++ /* New SoCs do not have a clock divider inside */ ++ if (!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { ++ /* Divide by 4 */ ++ writel(SPI0_CLK_DIV_BY_4, ++ base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : ++ SUN4I_SPI0_CCTL)); ++ } ++ + /* 24MHz from OSC24M */ + writel((1 << 31), CCM_SPI0_CLK); + } +@@ -180,6 +205,14 @@ static void spi0_enable_clock(void) + /* Wait for completion */ + while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + ; ++ ++ /* ++ * For new SoCs we should configure sample mode depending on ++ * input clock. As 24MHz from OSC24M is used, we could use ++ * normal sample mode by setting SDM bit in the TCR register ++ */ ++ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) ++ setbits_le32(base + SUN6I_SPI0_TCR, SUN6I_TCR_SDM); + } else { + /* Enable SPI in the master mode and reset FIFO */ + setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | +@@ -206,11 +239,13 @@ static void spi0_disable_clock(void) + writel(0, CCM_SPI0_CLK); + + /* Close the SPI0 gate */ +- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) ++ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && ++ !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + + /* Assert SPI0 reset on SUN6I */ +- if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) ++ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || ++ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); + else if (is_sun6i_gen_spi()) + clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, +@@ -224,7 +259,8 @@ static void spi0_init(void) + if (IS_ENABLED(CONFIG_MACH_SUN50I) || + IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + pin_function = SUN50I_GPC_SPI0; +- else if (IS_ENABLED(CONFIG_MACH_SUNIV)) ++ else if (IS_ENABLED(CONFIG_MACH_SUNIV) || ++ IS_ENABLED(CONFIG_MACH_SUN8I_R528)) + pin_function = SUNIV_GPC_SPI0; + + spi0_pinmux_setup(pin_function); +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4040-spi-sunxi-Add-support-for-R329-D1-R528-T113-SPI-cont.patch b/package/boot/uboot-sunxi/patches/4040-spi-sunxi-Add-support-for-R329-D1-R528-T113-SPI-cont.patch new file mode 100644 index 0000000000..373e784c1f --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4040-spi-sunxi-Add-support-for-R329-D1-R528-T113-SPI-cont.patch @@ -0,0 +1,122 @@ +From 805c9053f77e86e442f7a76832ea259695918a8c Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Fri, 19 May 2023 16:40:08 +0300 +Subject: [PATCH 4040/4044] spi: sunxi: Add support for R329/D1/R528/T113 SPI + controller + +These SoCs have two SPI controllers that are quite similar to the SPI +on previous Allwinner SoCs. The main difference is that new SoCs +don't have a clock divider (SPI_CCR register) inside SPI IP. + +Instead SPI sample mode should be configured depending on the input clock. + +For now SPI input clock source selection is not supported by this driver, +and only HOSC@24MHz can be used as input clock. Therefore, according to +the, manual we could change the SPI sample mode from delay half +cycle(default) to normal. + +This patch adds a quirk for this kind of SPI controllers + +Signed-off-by: Maxim Kiselev +Tested-by: Sam Edwards +--- + drivers/spi/spi-sunxi.c | 34 +++++++++++++++++++++++++++++++++- + 1 file changed, 33 insertions(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c +index c56d82d998..9ec6b359e2 100644 +--- a/drivers/spi/spi-sunxi.c ++++ b/drivers/spi/spi-sunxi.c +@@ -117,6 +117,8 @@ enum sun4i_spi_bits { + SPI_TCR_XCH, + SPI_TCR_CS_MANUAL, + SPI_TCR_CS_LEVEL, ++ SPI_TCR_SDC, ++ SPI_TCR_SDM, + SPI_FCR_TF_RST, + SPI_FCR_RF_RST, + SPI_FSR_RF_CNT_MASK, +@@ -128,6 +130,7 @@ struct sun4i_spi_variant { + u32 fifo_depth; + bool has_soft_reset; + bool has_burst_ctl; ++ bool has_clk_ctl; + }; + + struct sun4i_spi_plat { +@@ -302,7 +305,19 @@ static int sun4i_spi_claim_bus(struct udevice *dev) + setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) | + SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW)); + +- sun4i_spi_set_speed_mode(dev->parent); ++ if (priv->variant->has_clk_ctl) { ++ sun4i_spi_set_speed_mode(dev->parent); ++ } else { ++ /* ++ * At this moment there is no ability to change input clock. ++ * Therefore, we can only use default HOSC@24MHz clock and ++ * set SPI sampling mode to normal ++ */ ++ clrsetbits_le32(SPI_REG(priv, SPI_TCR), ++ SPI_BIT(priv, SPI_TCR_SDC) | ++ SPI_BIT(priv, SPI_TCR_SDM), ++ SPI_BIT(priv, SPI_TCR_SDM)); ++ } + + return 0; + } +@@ -516,6 +531,8 @@ static const u32 sun6i_spi_bits[] = { + [SPI_TCR_CS_MASK] = 0x30, + [SPI_TCR_CS_MANUAL] = BIT(6), + [SPI_TCR_CS_LEVEL] = BIT(7), ++ [SPI_TCR_SDC] = BIT(11), ++ [SPI_TCR_SDM] = BIT(13), + [SPI_TCR_XCH] = BIT(31), + [SPI_FCR_RF_RST] = BIT(15), + [SPI_FCR_TF_RST] = BIT(31), +@@ -526,6 +543,7 @@ static const struct sun4i_spi_variant sun4i_a10_spi_variant = { + .regs = sun4i_spi_regs, + .bits = sun4i_spi_bits, + .fifo_depth = 64, ++ .has_clk_ctl = true, + }; + + static const struct sun4i_spi_variant sun6i_a31_spi_variant = { +@@ -534,6 +552,7 @@ static const struct sun4i_spi_variant sun6i_a31_spi_variant = { + .fifo_depth = 128, + .has_soft_reset = true, + .has_burst_ctl = true, ++ .has_clk_ctl = true, + }; + + static const struct sun4i_spi_variant sun8i_h3_spi_variant = { +@@ -542,6 +561,15 @@ static const struct sun4i_spi_variant sun8i_h3_spi_variant = { + .fifo_depth = 64, + .has_soft_reset = true, + .has_burst_ctl = true, ++ .has_clk_ctl = true, ++}; ++ ++static const struct sun4i_spi_variant sun50i_r329_spi_variant = { ++ .regs = sun6i_spi_regs, ++ .bits = sun6i_spi_bits, ++ .fifo_depth = 64, ++ .has_soft_reset = true, ++ .has_burst_ctl = true, + }; + + static const struct udevice_id sun4i_spi_ids[] = { +@@ -557,6 +585,10 @@ static const struct udevice_id sun4i_spi_ids[] = { + .compatible = "allwinner,sun8i-h3-spi", + .data = (ulong)&sun8i_h3_spi_variant, + }, ++ { ++ .compatible = "allwinner,sun50i-r329-spi", ++ .data = (ulong)&sun50i_r329_spi_variant, ++ }, + { /* sentinel */ } + }; + +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4041-riscv-dts-allwinner-d1-Add-SPI-controllers-node.patch b/package/boot/uboot-sunxi/patches/4041-riscv-dts-allwinner-d1-Add-SPI-controllers-node.patch new file mode 100644 index 0000000000..90c015a31a --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4041-riscv-dts-allwinner-d1-Add-SPI-controllers-node.patch @@ -0,0 +1,77 @@ +From ae59ce94c3dd062bd6f371cef729664fea5c8c71 Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Fri, 19 May 2023 16:40:09 +0300 +Subject: [PATCH 4041/4044] riscv: dts: allwinner: d1: Add SPI controllers node + +Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have +an optional SPI flash that connects to the SPI0 controller. + +This controller is the same for R329/D1/R528/T113s SoCs and +should be supported by the sun50i-r329-spi driver. + +So let's add its DT nodes. + +Signed-off-by: Maxim Kiselev +Reviewed-by: Sam Edwards +--- + arch/riscv/dts/sunxi-d1s-t113.dtsi | 37 ++++++++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi +index b72bbc5e43..324353905f 100644 +--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi +@@ -108,6 +108,12 @@ + function = "emac"; + }; + ++ /omit-if-no-ref/ ++ spi0_pins: spi0-pins { ++ pins = "PC2", "PC3", "PC4", "PC5"; ++ function = "spi0"; ++ }; ++ + /omit-if-no-ref/ + uart1_pg6_pins: uart1-pg6-pins { + pins = "PG6", "PG7"; +@@ -459,6 +465,37 @@ + #size-cells = <0>; + }; + ++ spi0: spi@4025000 { ++ compatible = "allwinner,sun20i-d1-spi", ++ "allwinner,sun50i-r329-spi"; ++ reg = <0x04025000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma 22>, <&dma 22>; ++ dma-names = "rx", "tx"; ++ resets = <&ccu RST_BUS_SPI0>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ spi1: spi@4026000 { ++ compatible = "allwinner,sun20i-d1-spi-dbi", ++ "allwinner,sun50i-r329-spi-dbi", ++ "allwinner,sun50i-r329-spi"; ++ reg = <0x04026000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma 23>, <&dma 23>; ++ dma-names = "rx", "tx"; ++ resets = <&ccu RST_BUS_SPI1>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + usb_otg: usb@4100000 { + compatible = "allwinner,sun20i-d1-musb", + "allwinner,sun8i-a33-musb"; +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4201-myir-spi.patch b/package/boot/uboot-sunxi/patches/4042-sunxi-add-MYIR-MYD-YT113X-SPI-board.patch similarity index 61% rename from package/boot/uboot-sunxi/patches/4201-myir-spi.patch rename to package/boot/uboot-sunxi/patches/4042-sunxi-add-MYIR-MYD-YT113X-SPI-board.patch index 0d1dde5aff..b4e50e868d 100644 --- a/package/boot/uboot-sunxi/patches/4201-myir-spi.patch +++ b/package/boot/uboot-sunxi/patches/4042-sunxi-add-MYIR-MYD-YT113X-SPI-board.patch @@ -1,7 +1,24 @@ -diff -ruN u-boot-2023.04/arch/arm/dts/Makefile spi/arch/arm/dts/Makefile ---- u-boot-2023.04/arch/arm/dts/Makefile 2023-07-20 13:58:39.714010154 +0200 -+++ spi/arch/arm/dts/Makefile 2023-07-20 14:46:44.403569974 +0200 -@@ -715,6 +715,7 @@ +From 433545eafc6867a9b468bb9cd805bce36e172cda Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 29 Jul 2023 11:23:47 +0200 +Subject: [PATCH 4042/4044] sunxi: add MYIR MYD-YT113X-SPI board + +Instead of eMMC, this board sports a 256Mb SPI NAND flash. + +Signed-off-by: Zoltan HERPAI +--- + arch/arm/dts/Makefile | 1 + + .../dts/sun8i-t113s-myir-myd-yt113x-spi.dts | 59 +++++++++++++++++++ + configs/myir_myd_t113x-spi_defconfig | 38 ++++++++++++ + 3 files changed, 98 insertions(+) + create mode 100644 arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts + create mode 100644 configs/myir_myd_t113x-spi_defconfig + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index be89021657..267f7bc07e 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -714,6 +714,7 @@ dtb-$(CONFIG_MACH_SUN8I_R528) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t113s-mangopi-mqdual-t113.dtb \ sun8i-t113s-myir-myd-yt113x.dtb \ @@ -9,9 +26,11 @@ diff -ruN u-boot-2023.04/arch/arm/dts/Makefile spi/arch/arm/dts/Makefile sun8i-t113s-rongpin-rp-t113.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-bananapi-m2-plus.dtb \ -diff -ruN u-boot-2023.04/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts spi/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts ---- u-boot-2023.04/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts 1970-01-01 01:00:00.000000000 +0100 -+++ spi/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts 2023-07-20 14:52:36.468334540 +0200 +diff --git a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts +new file mode 100644 +index 0000000000..f72bab29a6 +--- /dev/null ++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. @@ -69,13 +88,15 @@ diff -ruN u-boot-2023.04/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts spi/ar + spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; -+ spi-max-frequency = <52000000>; ++ spi-max-frequency = <52000000>; + }; +}; -diff -ruN u-boot-2023.04/configs/myir_myd_t113x-spi_defconfig spi/configs/myir_myd_t113x-spi_defconfig ---- u-boot-2023.04/configs/myir_myd_t113x-spi_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ spi/configs/myir_myd_t113x-spi_defconfig 2023-07-20 14:33:59.790587258 +0200 -@@ -0,0 +1,37 @@ +diff --git a/configs/myir_myd_t113x-spi_defconfig b/configs/myir_myd_t113x-spi_defconfig +new file mode 100644 +index 0000000000..a433fe0449 +--- /dev/null ++++ b/configs/myir_myd_t113x-spi_defconfig +@@ -0,0 +1,38 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-myir-myd-yt113x-spi" @@ -95,6 +116,7 @@ diff -ruN u-boot-2023.04/configs/myir_myd_t113x-spi_defconfig spi/configs/myir_m +CONFIG_DRAM_SUNXI_TPR11=0x340000 +CONFIG_DRAM_SUNXI_TPR12=0x46 +CONFIG_DRAM_SUNXI_TPR13=0x34000100 ++CONFIG_CLK_SUN20I_D1=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_SUN8I_EMAC=y +CONFIG_RGMII=y @@ -113,3 +135,6 @@ diff -ruN u-boot-2023.04/configs/myir_myd_t113x-spi_defconfig spi/configs/myir_m +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI=y +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4043-sunxi-add-support-for-emac-on-PG-pins.patch b/package/boot/uboot-sunxi/patches/4043-sunxi-add-support-for-emac-on-PG-pins.patch new file mode 100644 index 0000000000..67359734b0 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4043-sunxi-add-support-for-emac-on-PG-pins.patch @@ -0,0 +1,34 @@ +From 7e690876a4d143df61950c4c60c56dc27d8fb0e2 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 29 Jul 2023 11:29:26 +0200 +Subject: [PATCH 4043/4044] sunxi: add support for emac on PG pins + +Some boards use Port G pins for muxing EMAC. + +Signed-off-by: Zoltan HERPAI +--- + arch/riscv/dts/sunxi-d1s-t113.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi +index 324353905f..2426c71f25 100644 +--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi +@@ -101,6 +101,14 @@ + function = "emac"; + }; + ++ /omit-if-no-ref/ ++ rgmii_pg_pins: rgmii-pg-pins { ++ pins = "PG0", "PG1", "PG2", "PG3", "PG4", ++ "PG5", "PG6", "PG7", "PG8", "PG9", ++ "PG11", "PG12", "PG13", "PG14", "PG15"; ++ function = "emac"; ++ }; ++ + /omit-if-no-ref/ + rmii_pe_pins: rmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4044-sunxi-add-ethernet-support-on-MYIR-MYD-YT113X-SPI.patch b/package/boot/uboot-sunxi/patches/4044-sunxi-add-ethernet-support-on-MYIR-MYD-YT113X-SPI.patch new file mode 100644 index 0000000000..58dc35bb3d --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4044-sunxi-add-ethernet-support-on-MYIR-MYD-YT113X-SPI.patch @@ -0,0 +1,62 @@ +From d664819e1142f0f44945ed31d62e666146639403 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 29 Jul 2023 11:34:19 +0200 +Subject: [PATCH 4044/4044] sunxi: add ethernet support on MYIR MYD-YT113X-SPI + +Signed-off-by: Zoltan HERPAI +--- + .../dts/sun8i-t113s-myir-myd-yt113x-spi.dts | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts +index f72bab29a6..431d5593d6 100644 +--- a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts ++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts +@@ -19,6 +19,23 @@ + chosen { + stdout-path = "serial5:115200n8"; + }; ++ ++ reg_vcc5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ /* SY8008 DC/DC regulator on the board */ ++ reg_3v3: regulator-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v>; ++ }; + }; + + &cpu0 { +@@ -57,3 +74,20 @@ + spi-max-frequency = <52000000>; + }; + }; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pg_pins>; ++ phy-supply = <®_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii-id"; ++ ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@4 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <4>; ++ }; ++}; +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4045-mtd-spi-nand-backport-from-upstream-kernel.patch b/package/boot/uboot-sunxi/patches/4045-mtd-spi-nand-backport-from-upstream-kernel.patch new file mode 100644 index 0000000000..36eef6db28 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4045-mtd-spi-nand-backport-from-upstream-kernel.patch @@ -0,0 +1,1569 @@ +From d44bacf6dab96824f23f06d264271d370f2f4431 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 27 Jul 2022 16:36:13 +0800 +Subject: [PATCH 46/46] mtd: spi-nand: backport from upstream kernel + +Backport new features from upstream kernel + +Signed-off-by: Weijie Gao +--- + drivers/mtd/nand/spi/Kconfig | 8 + + drivers/mtd/nand/spi/core.c | 101 ++++++---- + drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++---- + drivers/mtd/nand/spi/macronix.c | 173 +++++++++++++--- + drivers/mtd/nand/spi/micron.c | 50 ++--- + drivers/mtd/nand/spi/toshiba.c | 66 +++--- + drivers/mtd/nand/spi/winbond.c | 171 +++++++++++++--- + include/linux/mtd/spinand.h | 86 +++++--- + 8 files changed, 753 insertions(+), 224 deletions(-) + +diff --git a/drivers/mtd/nand/spi/Kconfig b/drivers/mtd/nand/spi/Kconfig +index 0777dfdf0a..bbd0981968 100644 +--- a/drivers/mtd/nand/spi/Kconfig ++++ b/drivers/mtd/nand/spi/Kconfig +@@ -5,3 +5,11 @@ menuconfig MTD_SPI_NAND + select SPI_MEM + help + This is the framework for the SPI NAND device drivers. ++ ++config MTD_SPI_NAND_W25N01KV ++ tristate "Winbond W25N01KV Support" ++ select MTD_SPI_NAND ++ default n ++ help ++ Winbond W25N01KV share the same ID with W25N01GV. However, they have ++ different attributes. +diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c +index 134bf22c80..46ce48e0ea 100644 +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #else +@@ -451,10 +452,11 @@ out: + return status & STATUS_BUSY ? -ETIMEDOUT : 0; + } + +-static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf) ++static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, ++ u8 ndummy, u8 *buf) + { +- struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf, +- SPINAND_MAX_ID_LEN); ++ struct spi_mem_op op = SPINAND_READID_OP( ++ naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); + int ret; + + ret = spi_mem_exec_op(spinand->slave, &op); +@@ -464,18 +466,6 @@ static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf) + return ret; + } + +-static int spinand_reset_op(struct spinand_device *spinand) +-{ +- struct spi_mem_op op = SPINAND_RESET_OP; +- int ret; +- +- ret = spi_mem_exec_op(spinand->slave, &op); +- if (ret) +- return ret; +- +- return spinand_wait(spinand, NULL); +-} +- + static int spinand_lock_block(struct spinand_device *spinand, u8 lock) + { + return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); +@@ -836,24 +826,63 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { + &winbond_spinand_manufacturer, + }; + +-static int spinand_manufacturer_detect(struct spinand_device *spinand) ++static int spinand_manufacturer_match(struct spinand_device *spinand, ++ enum spinand_readid_method rdid_method) + { ++ u8 *id = spinand->id.data; + unsigned int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) { +- ret = spinand_manufacturers[i]->ops->detect(spinand); +- if (ret > 0) { +- spinand->manufacturer = spinand_manufacturers[i]; +- return 0; +- } else if (ret < 0) { +- return ret; +- } ++ const struct spinand_manufacturer *manufacturer = ++ spinand_manufacturers[i]; ++ ++ if (id[0] != manufacturer->id) ++ continue; ++ ++ ret = spinand_match_and_init(spinand, ++ manufacturer->chips, ++ manufacturer->nchips, ++ rdid_method); ++ if (ret < 0) ++ continue; ++ ++ spinand->manufacturer = manufacturer; ++ return 0; + } + + return -ENOTSUPP; + } + ++static int spinand_id_detect(struct spinand_device *spinand) ++{ ++ u8 *id = spinand->id.data; ++ int ret; ++ ++ ret = spinand_read_id_op(spinand, 0, 0, id); ++ if (ret) ++ return ret; ++ ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE); ++ if (!ret) ++ return 0; ++ ++ ret = spinand_read_id_op(spinand, 1, 0, id); ++ if (ret) ++ return ret; ++ ret = spinand_manufacturer_match(spinand, ++ SPINAND_READID_METHOD_OPCODE_ADDR); ++ if (!ret) ++ return 0; ++ ++ ret = spinand_read_id_op(spinand, 0, 1, id); ++ if (ret) ++ return ret; ++ ret = spinand_manufacturer_match(spinand, ++ SPINAND_READID_METHOD_OPCODE_DUMMY); ++ ++ return ret; ++} ++ + static int spinand_manufacturer_init(struct spinand_device *spinand) + { + if (spinand->manufacturer->ops->init) +@@ -909,9 +938,9 @@ spinand_select_op_variant(struct spinand_device *spinand, + * @spinand: SPI NAND object + * @table: SPI NAND device description table + * @table_size: size of the device description table ++ * @rdid_method: read id method to match + * +- * Should be used by SPI NAND manufacturer drivers when they want to find a +- * match between a device ID retrieved through the READ_ID command and an ++ * Match between a device ID retrieved through the READ_ID command and an + * entry in the SPI NAND description table. If a match is found, the spinand + * object will be initialized with information provided by the matching + * spinand_info entry. +@@ -920,8 +949,10 @@ spinand_select_op_variant(struct spinand_device *spinand, + */ + int spinand_match_and_init(struct spinand_device *spinand, + const struct spinand_info *table, +- unsigned int table_size, u8 devid) ++ unsigned int table_size, ++ enum spinand_readid_method rdid_method) + { ++ u8 *id = spinand->id.data; + struct nand_device *nand = spinand_to_nand(spinand); + unsigned int i; + +@@ -929,13 +960,17 @@ int spinand_match_and_init(struct spinand_device *spinand, + const struct spinand_info *info = &table[i]; + const struct spi_mem_op *op; + +- if (devid != info->devid) ++ if (rdid_method != info->devid.method) ++ continue; ++ ++ if (memcmp(id + 1, info->devid.id, info->devid.len)) + continue; + + nand->memorg = table[i].memorg; + nand->eccreq = table[i].eccreq; + spinand->eccinfo = table[i].eccinfo; + spinand->flags = table[i].flags; ++ spinand->id.len = 1 + table[i].devid.len; + spinand->select_target = table[i].select_target; + + op = spinand_select_op_variant(spinand, +@@ -967,17 +1002,7 @@ static int spinand_detect(struct spinand_device *spinand) + struct nand_device *nand = spinand_to_nand(spinand); + int ret; + +- ret = spinand_reset_op(spinand); +- if (ret) +- return ret; +- +- ret = spinand_read_id_op(spinand, spinand->id.data); +- if (ret) +- return ret; +- +- spinand->id.len = SPINAND_MAX_ID_LEN; +- +- ret = spinand_manufacturer_detect(spinand); ++ ret = spinand_id_detect(spinand); + if (ret) { + dev_err(spinand->slave->dev, "unknown raw ID %*phN\n", + SPINAND_MAX_ID_LEN, spinand->id.data); +diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c +index a2c93486f4..5357f02ddc 100644 +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -22,8 +22,13 @@ + + #define GD5FXGQXXEXXG_REG_STATUS2 0xf0 + ++#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4) ++#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4) ++#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4) ++#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4) ++ + /* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */ +-static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants, ++static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), +@@ -31,8 +36,17 @@ static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +-/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */ +-static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants, ++static SPINAND_OP_VARIANTS(read_cache_variants_f, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); ++ ++/* For Q5 devices, QUADIO use different dummy byte settings */ ++/* Q5 1Gb */ ++static SPINAND_OP_VARIANTS(dummy2_read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), +@@ -40,6 +54,15 @@ static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + ++/* Q5 2Gb & 4Gb */ ++static SPINAND_OP_VARIANTS(dummy4_read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ + static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); +@@ -48,7 +71,65 @@ static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +-static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section, ++static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 8; ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ if (section) { ++ region->offset = 16 * section; ++ region->length = 8; ++ } else { ++ /* section 0 has one byte reserved for bad block mark */ ++ region->offset = 1; ++ region->length = 7; ++ } ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = { ++ .ecc = gd5fxgq4xa_ooblayout_ecc, ++ .rfree = gd5fxgq4xa_ooblayout_free, ++}; ++ ++static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ switch (status & STATUS_ECC_MASK) { ++ case STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS: ++ /* 1-7 bits are flipped. return the maximum. */ ++ return 7; ++ ++ case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS: ++ return 8; ++ ++ case STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ default: ++ break; ++ } ++ ++ return -EINVAL; ++} ++ ++static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) + { + if (section) +@@ -60,7 +141,7 @@ static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section, + return 0; + } + +-static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section, ++static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) + { + if (section) +@@ -73,7 +154,13 @@ static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section, + return 0; + } + +-static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand, ++/* Valid for Q4/Q5 and Q6 (untested) devices */ ++static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = { ++ .ecc = gd5fxgqx_variant2_ooblayout_ecc, ++ .rfree = gd5fxgqx_variant2_ooblayout_free, ++}; ++ ++static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, + u8 status) + { + u8 status2; +@@ -152,59 +239,214 @@ static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, + return -EINVAL; + } + +-static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = { +- .ecc = gd5fxgqxxexxg_ooblayout_ecc, +- .rfree = gd5fxgqxxexxg_ooblayout_free, ++static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) { ++ case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS: ++ return 3; ++ ++ case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */ ++ return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2; ++ } ++ ++ return -EINVAL; ++} ++ ++static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 8; ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 6; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops esmt_1_ooblayout = { ++ .ecc = esmt_1_ooblayout_ecc, ++ .rfree = esmt_1_ooblayout_free, + }; + + static const struct spinand_info gigadevice_spinand_table[] = { +- SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, +- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), ++ SPINAND_INFO("F50L1G41LB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), +- SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants, ++ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, +- SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout, +- gd5fxgq4xexxg_ecc_get_status)), +- SPINAND_INFO("GD5F1GQ5UExxG", 0x51, ++ SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)), ++ SPINAND_INFO("GD5F1GQ4xA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, ++ gd5fxgq4xa_ecc_get_status)), ++ SPINAND_INFO("GD5F2GQ4xA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, ++ gd5fxgq4xa_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ4xA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4), ++ NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, ++ gd5fxgq4xa_ecc_get_status)), ++ SPINAND_INFO("GD5F1GQ4UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq4uexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F1GQ4UFxxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq4ufxxg_ecc_get_status)), ++ SPINAND_INFO("GD5F1GQ5UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), +- SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, ++ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, +- SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout, ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F2GQ5UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ6UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F1GM7UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq4uexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F2GM7UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq4uexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F4GM8UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq4uexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F1GQ5UExxH", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F2GQ5UExxH", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ6UExxH", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), ++ NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq5xexxg_ecc_get_status)), + }; + +-static int gigadevice_spinand_detect(struct spinand_device *spinand) +-{ +- u8 *id = spinand->id.data; +- int ret; +- +- /* +- * For GD NANDs, There is an address byte needed to shift in before IDs +- * are read out, so the first byte in raw_id is dummy. +- */ +- if (id[1] != SPINAND_MFR_GIGADEVICE) +- return 0; +- +- ret = spinand_match_and_init(spinand, gigadevice_spinand_table, +- ARRAY_SIZE(gigadevice_spinand_table), +- id[2]); +- if (ret) +- return ret; +- +- return 1; +-} +- + static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { +- .detect = gigadevice_spinand_detect, + }; + + const struct spinand_manufacturer gigadevice_spinand_manufacturer = { + .id = SPINAND_MFR_GIGADEVICE, + .name = "GigaDevice", ++ .chips = gigadevice_spinand_table, ++ .nchips = ARRAY_SIZE(gigadevice_spinand_table), + .ops = &gigadevice_spinand_manuf_ops, + }; +diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c +index 6d643a8000..34e622d6e9 100644 +--- a/drivers/mtd/nand/spi/macronix.c ++++ b/drivers/mtd/nand/spi/macronix.c +@@ -105,7 +105,8 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, + } + + static const struct spinand_info macronix_spinand_table[] = { +- SPINAND_INFO("MX35LF1GE4AB", 0x12, ++ SPINAND_INFO("MX35LF1GE4AB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -114,7 +115,8 @@ static const struct spinand_info macronix_spinand_table[] = { + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), +- SPINAND_INFO("MX35LF2GE4AB", 0x22, ++ SPINAND_INFO("MX35LF2GE4AB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22), + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -122,7 +124,96 @@ static const struct spinand_info macronix_spinand_table[] = { + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), +- SPINAND_INFO("MX35UF4GE4AD", 0xb7, ++ SPINAND_INFO("MX35LF2GE4AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35LF4GE4AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37), ++ NAND_MEMORG(1, 4096, 128, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35LF1G24AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), ++ SPINAND_INFO("MX35LF2G24AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), ++ SPINAND_INFO("MX35LF4G24AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), ++ NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), ++ SPINAND_INFO("MX31LF1GE4BC", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX31UF1GE4BC", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ ++ SPINAND_INFO("MX35LF2G14AC", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35UF4G24AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5), ++ NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35UF4GE4AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -131,7 +222,28 @@ static const struct spinand_info macronix_spinand_table[] = { + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), +- SPINAND_INFO("MX35UF2GE4AD", 0xa6, ++ SPINAND_INFO("MX35UF2G14AC", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35UF2G24AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35UF2GE4AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6), + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -140,16 +252,38 @@ static const struct spinand_info macronix_spinand_table[] = { + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), +- SPINAND_INFO("MX35UF2GE4AC", 0xa2, ++ SPINAND_INFO("MX35UF2GE4AC", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2), + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), + NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35UF1G14AC", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35UF1G24AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), +- SPINAND_INFO("MX35UF1GE4AD", 0x96, ++ SPINAND_INFO("MX35UF1GE4AD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -158,7 +292,8 @@ static const struct spinand_info macronix_spinand_table[] = { + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), +- SPINAND_INFO("MX35UF1GE4AC", 0x92, ++ SPINAND_INFO("MX35UF1GE4AC", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -170,33 +305,13 @@ static const struct spinand_info macronix_spinand_table[] = { + + }; + +-static int macronix_spinand_detect(struct spinand_device *spinand) +-{ +- u8 *id = spinand->id.data; +- int ret; +- +- /* +- * Macronix SPI NAND read ID needs a dummy byte, so the first byte in +- * raw_id is garbage. +- */ +- if (id[1] != SPINAND_MFR_MACRONIX) +- return 0; +- +- ret = spinand_match_and_init(spinand, macronix_spinand_table, +- ARRAY_SIZE(macronix_spinand_table), +- id[2]); +- if (ret) +- return ret; +- +- return 1; +-} +- + static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = { +- .detect = macronix_spinand_detect, + }; + + const struct spinand_manufacturer macronix_spinand_manufacturer = { + .id = SPINAND_MFR_MACRONIX, + .name = "Macronix", ++ .chips = macronix_spinand_table, ++ .nchips = ARRAY_SIZE(macronix_spinand_table), + .ops = ¯onix_spinand_manuf_ops, + }; +diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c +index 6bacf14aaf..cecd3db958 100644 +--- a/drivers/mtd/nand/spi/micron.c ++++ b/drivers/mtd/nand/spi/micron.c +@@ -120,7 +120,8 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand, + + static const struct spinand_info micron_spinand_table[] = { + /* M79A 2Gb 3.3V */ +- SPINAND_INFO("MT29F2G01ABAGD", 0x24, ++ SPINAND_INFO("MT29F2G01ABAGD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -130,7 +131,8 @@ static const struct spinand_info micron_spinand_table[] = { + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M79A 2Gb 1.8V */ +- SPINAND_INFO("MT29F2G01ABBGD", 0x25, ++ SPINAND_INFO("MT29F2G01ABBGD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -140,7 +142,8 @@ static const struct spinand_info micron_spinand_table[] = { + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M78A 1Gb 3.3V */ +- SPINAND_INFO("MT29F1G01ABAFD", 0x14, ++ SPINAND_INFO("MT29F1G01ABAFD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -150,7 +153,8 @@ static const struct spinand_info micron_spinand_table[] = { + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M78A 1Gb 1.8V */ +- SPINAND_INFO("MT29F1G01ABAFD", 0x15, ++ SPINAND_INFO("MT29F1G01ABAFD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -160,7 +164,8 @@ static const struct spinand_info micron_spinand_table[] = { + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M79A 4Gb 3.3V */ +- SPINAND_INFO("MT29F4G01ADAGD", 0x36, ++ SPINAND_INFO("MT29F4G01ADAGD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36), + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -171,7 +176,8 @@ static const struct spinand_info micron_spinand_table[] = { + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), + /* M70A 4Gb 3.3V */ +- SPINAND_INFO("MT29F4G01ABAFD", 0x34, ++ SPINAND_INFO("MT29F4G01ABAFD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -181,7 +187,8 @@ static const struct spinand_info micron_spinand_table[] = { + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M70A 4Gb 1.8V */ +- SPINAND_INFO("MT29F4G01ABBFD", 0x35, ++ SPINAND_INFO("MT29F4G01ABBFD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -191,7 +198,8 @@ static const struct spinand_info micron_spinand_table[] = { + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M70A 8Gb 3.3V */ +- SPINAND_INFO("MT29F8G01ADAFD", 0x46, ++ SPINAND_INFO("MT29F8G01ADAFD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -202,7 +210,8 @@ static const struct spinand_info micron_spinand_table[] = { + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), + /* M70A 8Gb 1.8V */ +- SPINAND_INFO("MT29F8G01ADBFD", 0x47, ++ SPINAND_INFO("MT29F8G01ADBFD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -214,26 +223,6 @@ static const struct spinand_info micron_spinand_table[] = { + SPINAND_SELECT_TARGET(micron_select_target)), + }; + +-static int micron_spinand_detect(struct spinand_device *spinand) +-{ +- u8 *id = spinand->id.data; +- int ret; +- +- /* +- * Micron SPI NAND read ID need a dummy byte, +- * so the first byte in raw_id is dummy. +- */ +- if (id[1] != SPINAND_MFR_MICRON) +- return 0; +- +- ret = spinand_match_and_init(spinand, micron_spinand_table, +- ARRAY_SIZE(micron_spinand_table), id[2]); +- if (ret) +- return ret; +- +- return 1; +-} +- + static int micron_spinand_init(struct spinand_device *spinand) + { + /* +@@ -248,12 +237,13 @@ static int micron_spinand_init(struct spinand_device *spinand) + } + + static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { +- .detect = micron_spinand_detect, + .init = micron_spinand_init, + }; + + const struct spinand_manufacturer micron_spinand_manufacturer = { + .id = SPINAND_MFR_MICRON, + .name = "Micron", ++ .chips = micron_spinand_table, ++ .nchips = ARRAY_SIZE(micron_spinand_table), + .ops = µn_spinand_manuf_ops, + }; +diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c +index c2cd3b426b..e057b08c70 100644 +--- a/drivers/mtd/nand/spi/toshiba.c ++++ b/drivers/mtd/nand/spi/toshiba.c +@@ -111,7 +111,8 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand, + + static const struct spinand_info toshiba_spinand_table[] = { + /* 3.3V 1Gb (1st generation) */ +- SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2, ++ SPINAND_INFO("TC58CVG0S3HRAIG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -121,7 +122,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 3.3V 2Gb (1st generation) */ +- SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB, ++ SPINAND_INFO("TC58CVG1S3HRAIG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB), + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -131,7 +133,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 3.3V 4Gb (1st generation) */ +- SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD, ++ SPINAND_INFO("TC58CVG2S0HRAIG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -141,7 +144,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 1Gb (1st generation) */ +- SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2, ++ SPINAND_INFO("TC58CYG0S3HRAIG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -151,7 +155,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 2Gb (1st generation) */ +- SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB, ++ SPINAND_INFO("TC58CYG1S3HRAIG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB), + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -161,7 +166,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 4Gb (1st generation) */ +- SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD, ++ SPINAND_INFO("TC58CYG2S0HRAIG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -176,7 +182,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + * QE_BIT. + */ + /* 3.3V 1Gb (2nd generation) */ +- SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2, ++ SPINAND_INFO("TC58CVG0S3HRAIJ", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -186,7 +193,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 3.3V 2Gb (2nd generation) */ +- SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB, ++ SPINAND_INFO("TC58CVG1S3HRAIJ", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB), + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -196,7 +204,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 3.3V 4Gb (2nd generation) */ +- SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED, ++ SPINAND_INFO("TC58CVG2S0HRAIJ", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -206,7 +215,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 3.3V 8Gb (2nd generation) */ +- SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4, ++ SPINAND_INFO("TH58CVG3S0HRAIJ", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4), + NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -216,7 +226,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 1Gb (2nd generation) */ +- SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2, ++ SPINAND_INFO("TC58CYG0S3HRAIJ", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -226,7 +237,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 2Gb (2nd generation) */ +- SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB, ++ SPINAND_INFO("TC58CYG1S3HRAIJ", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB), + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -236,7 +248,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 4Gb (2nd generation) */ +- SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD, ++ SPINAND_INFO("TC58CYG2S0HRAIJ", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -246,7 +259,8 @@ static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 8Gb (2nd generation) */ +- SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4, ++ SPINAND_INFO("TH58CYG3S0HRAIJ", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4), + NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -257,33 +271,13 @@ static const struct spinand_info toshiba_spinand_table[] = { + tx58cxgxsxraix_ecc_get_status)), + }; + +-static int toshiba_spinand_detect(struct spinand_device *spinand) +-{ +- u8 *id = spinand->id.data; +- int ret; +- +- /* +- * Toshiba SPI NAND read ID needs a dummy byte, +- * so the first byte in id is garbage. +- */ +- if (id[1] != SPINAND_MFR_TOSHIBA) +- return 0; +- +- ret = spinand_match_and_init(spinand, toshiba_spinand_table, +- ARRAY_SIZE(toshiba_spinand_table), +- id[2]); +- if (ret) +- return ret; +- +- return 1; +-} +- + static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { +- .detect = toshiba_spinand_detect, + }; + + const struct spinand_manufacturer toshiba_spinand_manufacturer = { + .id = SPINAND_MFR_TOSHIBA, + .name = "Toshiba", ++ .chips = toshiba_spinand_table, ++ .nchips = ARRAY_SIZE(toshiba_spinand_table), + .ops = &toshiba_spinand_manuf_ops, + }; +diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c +index c119486efb..7a108cb3e6 100644 +--- a/drivers/mtd/nand/spi/winbond.c ++++ b/drivers/mtd/nand/spi/winbond.c +@@ -19,6 +19,25 @@ + + #define WINBOND_CFG_BUF_READ BIT(3) + ++#define W25N02_N04KV_STATUS_ECC_MASK (3 << 4) ++#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS (0 << 4) ++#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS (1 << 4) ++#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4) ++#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR (2 << 4) ++ ++#define W25N01_M02GV_STATUS_ECC_MASK (3 << 4) ++#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS (0 << 4) ++#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4) ++#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4) ++ ++#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV) ++#define W25N01KV_STATUS_ECC_MASK (3 << 4) ++#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4) ++#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4) ++#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4) ++#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4) ++#endif ++ + static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), +@@ -35,6 +54,35 @@ static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + ++static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 64; ++ region->length = 16; ++ ++ return 0; ++} ++ ++static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 14; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = { ++ .ecc = w25n02kv_n04kv_ooblayout_ecc, ++ .rfree = w25n02kv_n04kv_ooblayout_free, ++}; ++ + static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) + { +@@ -78,8 +126,63 @@ static int w25m02gv_select_target(struct spinand_device *spinand, + return spi_mem_exec_op(spinand->slave, &op); + } + ++#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV) ++static int w25n01kv_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ switch (status & W25N01KV_STATUS_ECC_MASK) { ++ case W25N01KV_STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case W25N01KV_STATUS_ECC_1_3_BITFLIPS: ++ return 3; ++ ++ case W25N01KV_STATUS_ECC_4_BITFLIPS: ++ return 4; ++ ++ case W25N01KV_STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ default: ++ break; ++ } ++ ++ return -EINVAL; ++} ++#endif ++ ++static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ switch (status & W25N02_N04KV_STATUS_ECC_MASK) { ++ case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS: ++ return 3; ++ ++ case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS: ++ return 4; ++ ++ /* W25N02_N04KV_use internal 8bit ECC algorithm. ++ * But the ECC strength is 4 bit requried. ++ * Return 3 if the bit bit flip count less than 5. ++ * Return 4 if the bit bit flip count more than 5 to 8. ++ */ ++ ++ case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ default: ++ break; ++ } ++ ++ return -EINVAL; ++} ++ + static const struct spinand_info winbond_spinand_table[] = { +- SPINAND_INFO("W25M02GV", 0xAB, ++ SPINAND_INFO("W25M02GV", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21), + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2), + NAND_ECCREQ(1, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -88,7 +191,19 @@ static const struct spinand_info winbond_spinand_table[] = { + 0, + SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), + SPINAND_SELECT_TARGET(w25m02gv_select_target)), +- SPINAND_INFO("W25N01GV", 0xAA, ++#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV) ++ SPINAND_INFO("W25N01KV", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21), ++ NAND_MEMORG(1, 2048, 96, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)), ++#else ++ SPINAND_INFO("W25N01GV", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21), + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(1, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +@@ -96,32 +211,31 @@ static const struct spinand_info winbond_spinand_table[] = { + &update_cache_variants), + 0, + SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), +-}; +- +-/** +- * winbond_spinand_detect - initialize device related part in spinand_device +- * struct if it is a Winbond device. +- * @spinand: SPI NAND device structure +- */ +-static int winbond_spinand_detect(struct spinand_device *spinand) +-{ +- u8 *id = spinand->id.data; +- int ret; +- +- /* +- * Winbond SPI NAND read ID need a dummy byte, +- * so the first byte in raw_id is dummy. ++#endif ++ SPINAND_INFO("W25N02KV", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, ++ w25n02kv_n04kv_ecc_get_status)), ++ /* W25N04KV has 2-die(lun), however, it can select die automatically. ++ * Treat it as single die here and double block size. + */ +- if (id[1] != SPINAND_MFR_WINBOND) +- return 0; +- +- ret = spinand_match_and_init(spinand, winbond_spinand_table, +- ARRAY_SIZE(winbond_spinand_table), id[2]); +- if (ret) +- return ret; +- +- return 1; +-} ++ SPINAND_INFO("W25N04KV", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, ++ w25n02kv_n04kv_ecc_get_status)), ++}; + + static int winbond_spinand_init(struct spinand_device *spinand) + { +@@ -142,12 +256,13 @@ static int winbond_spinand_init(struct spinand_device *spinand) + } + + static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { +- .detect = winbond_spinand_detect, + .init = winbond_spinand_init, + }; + + const struct spinand_manufacturer winbond_spinand_manufacturer = { + .id = SPINAND_MFR_WINBOND, + .name = "Winbond", ++ .chips = winbond_spinand_table, ++ .nchips = ARRAY_SIZE(winbond_spinand_table), + .ops = &winbond_spinand_manuf_ops, + }; +diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h +index 15bcd59f34..3a138f977e 100644 +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -39,15 +39,15 @@ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +-#define SPINAND_READID_OP(ndummy, buf, len) \ ++#define SPINAND_READID_OP(naddr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ +- SPI_MEM_OP_NO_ADDR, \ ++ SPI_MEM_OP_ADDR(naddr, 0, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 1)) + + #define SPINAND_SET_FEATURE_OP(reg, valptr) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ +- SPI_MEM_OP_ADDR(1, reg, 1), \ ++ SPI_MEM_OP_ADDR(1, reg, 1), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, valptr, 1)) + +@@ -75,18 +75,36 @@ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 1)) + ++#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len)\ ++ SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ ++ SPI_MEM_OP_ADDR(3, addr, 1), \ ++ SPI_MEM_OP_DUMMY(ndummy, 1), \ ++ SPI_MEM_OP_DATA_IN(len, buf, 1)) ++ + #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ + SPI_MEM_OP_ADDR(2, addr, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 2)) + ++#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \ ++ SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ ++ SPI_MEM_OP_ADDR(3, addr, 1), \ ++ SPI_MEM_OP_DUMMY(ndummy, 1), \ ++ SPI_MEM_OP_DATA_IN(len, buf, 2)) ++ + #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ + SPI_MEM_OP_ADDR(2, addr, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 4)) + ++#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \ ++ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ ++ SPI_MEM_OP_ADDR(3, addr, 1), \ ++ SPI_MEM_OP_DUMMY(ndummy, 1), \ ++ SPI_MEM_OP_DATA_IN(len, buf, 4)) ++ + #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ + SPI_MEM_OP_ADDR(2, addr, 2), \ +@@ -153,37 +171,46 @@ struct spinand_device; + * @data: buffer containing the id bytes. Currently 4 bytes large, but can + * be extended if required + * @len: ID length +- * +- * struct_spinand_id->data contains all bytes returned after a READ_ID command, +- * including dummy bytes if the chip does not emit ID bytes right after the +- * READ_ID command. The responsibility to extract real ID bytes is left to +- * struct_manufacurer_ops->detect(). + */ + struct spinand_id { + u8 data[SPINAND_MAX_ID_LEN]; + int len; + }; + ++enum spinand_readid_method { ++ SPINAND_READID_METHOD_OPCODE, ++ SPINAND_READID_METHOD_OPCODE_ADDR, ++ SPINAND_READID_METHOD_OPCODE_DUMMY, ++}; ++ ++/** ++ * struct spinand_devid - SPI NAND device id structure ++ * @id: device id of current chip ++ * @len: number of bytes in device id ++ * @method: method to read chip id ++ * There are 3 possible variants: ++ * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately ++ * after read_id opcode. ++ * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after ++ * read_id opcode + 1-byte address. ++ * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after ++ * read_id opcode + 1 dummy byte. ++ */ ++struct spinand_devid { ++ const u8 *id; ++ const u8 len; ++ const enum spinand_readid_method method; ++}; ++ + /** + * struct manufacurer_ops - SPI NAND manufacturer specific operations +- * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed +- * the core calls the struct_manufacurer_ops->detect() hook of each +- * registered manufacturer until one of them return 1. Note that +- * the first thing to check in this hook is that the manufacturer ID +- * in struct_spinand_device->id matches the manufacturer whose +- * ->detect() hook has been called. Should return 1 if there's a +- * match, 0 if the manufacturer ID does not match and a negative +- * error code otherwise. When true is returned, the core assumes +- * that properties of the NAND chip (spinand->base.memorg and +- * spinand->base.eccreq) have been filled + * @init: initialize a SPI NAND device + * @cleanup: cleanup a SPI NAND device + * + * Each SPI NAND manufacturer driver should implement this interface so that +- * NAND chips coming from this vendor can be detected and initialized properly. ++ * NAND chips coming from this vendor can be initialized properly. + */ + struct spinand_manufacturer_ops { +- int (*detect)(struct spinand_device *spinand); + int (*init)(struct spinand_device *spinand); + void (*cleanup)(struct spinand_device *spinand); + }; +@@ -192,11 +219,16 @@ struct spinand_manufacturer_ops { + * struct spinand_manufacturer - SPI NAND manufacturer instance + * @id: manufacturer ID + * @name: manufacturer name ++ * @devid_len: number of bytes in device ID ++ * @chips: supported SPI NANDs under current manufacturer ++ * @nchips: number of SPI NANDs available in chips array + * @ops: manufacturer operations + */ + struct spinand_manufacturer { + u8 id; + char *name; ++ const struct spinand_info *chips; ++ const size_t nchips; + const struct spinand_manufacturer_ops *ops; + }; + +@@ -268,7 +300,7 @@ struct spinand_ecc_info { + */ + struct spinand_info { + const char *model; +- u8 devid; ++ struct spinand_devid devid; + u32 flags; + struct nand_memory_organization memorg; + struct nand_ecc_req eccreq; +@@ -282,6 +314,13 @@ struct spinand_info { + unsigned int target); + }; + ++#define SPINAND_ID(__method, ...) \ ++ { \ ++ .id = (const u8[]){ __VA_ARGS__ }, \ ++ .len = sizeof((u8[]){ __VA_ARGS__ }), \ ++ .method = __method, \ ++ } ++ + #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ + { \ + .read_cache = __read, \ +@@ -440,9 +479,10 @@ static inline void spinand_set_ofnode(struct spinand_device *spinand, + } + #endif /* __UBOOT__ */ + +-int spinand_match_and_init(struct spinand_device *dev, ++int spinand_match_and_init(struct spinand_device *spinand, + const struct spinand_info *table, +- unsigned int table_size, u8 devid); ++ unsigned int table_size, ++ enum spinand_readid_method rdid_method); + + int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); + int spinand_select_target(struct spinand_device *spinand, unsigned int target); +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4046-arm-dts-add-partition-table-for-MYIR-MYD-YT113X-SPI.patch b/package/boot/uboot-sunxi/patches/4046-arm-dts-add-partition-table-for-MYIR-MYD-YT113X-SPI.patch new file mode 100644 index 0000000000..132505fab5 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4046-arm-dts-add-partition-table-for-MYIR-MYD-YT113X-SPI.patch @@ -0,0 +1,60 @@ +From b943ca1bd3580393f1525cb021c9a2051c9f1958 Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 26 Aug 2023 17:45:03 +0200 +Subject: [PATCH 4046/4047] arm: dts: add partition table for MYIR + MYD-YT113X-SPI + +The original bootloader reports the following as the partition table: + +device nand0 , # parts = 4 + #: name size offset mask_flags + 0: boot0 0x00100000 0x00000000 1 + 1: uboot 0x00300000 0x00100000 1 + 2: secure_storage 0x00100000 0x00400000 1 + 3: sys 0x0fb00000 0x00500000 0 + +Signed-off-by: Zoltan HERPAI +--- + .../dts/sun8i-t113s-myir-myd-yt113x-spi.dts | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts +index 431d5593d6..a5fd8c6bea 100644 +--- a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts ++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts +@@ -72,6 +72,32 @@ + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "boot0"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "uboot"; ++ reg = <0x0 0x300000>; ++ }; ++ ++ partition@400000 { ++ label = "secure_storage"; ++ reg = <0x0 0x400000>; ++ }; ++ ++ partition@500000 { ++ label = "sys"; ++ reg = <0x0 0xfb00000>; ++ }; ++ }; + }; + }; + +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4047-configs-enable-UBI-support-for-MYIR-MYD-YT113X-SPI.patch b/package/boot/uboot-sunxi/patches/4047-configs-enable-UBI-support-for-MYIR-MYD-YT113X-SPI.patch new file mode 100644 index 0000000000..0fab7507a0 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4047-configs-enable-UBI-support-for-MYIR-MYD-YT113X-SPI.patch @@ -0,0 +1,22 @@ +From a6fbb8f2e7555c2fdd3e42d9e46523eb2d03d83a Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 26 Aug 2023 17:46:22 +0200 +Subject: [PATCH 4047/4047] configs: enable UBI support for MYIR MYD-YT113X-SPI + +Signed-off-by: Zoltan HERPAI +--- + configs/myir_myd_t113x-spi_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/myir_myd_t113x-spi_defconfig b/configs/myir_myd_t113x-spi_defconfig +index a433fe0449..d7b9a9bbcf 100644 +--- a/configs/myir_myd_t113x-spi_defconfig ++++ b/configs/myir_myd_t113x-spi_defconfig +@@ -36,3 +36,4 @@ CONFIG_SPI_FLASH_WINBOND=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set + CONFIG_SPI_FLASH_MTD=y + CONFIG_SPI=y ++CONFIG_MTD_UBI_FASTMAP=y +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4048-sunxi-r528-d1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch b/package/boot/uboot-sunxi/patches/4048-sunxi-r528-d1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch new file mode 100644 index 0000000000..a07fb474c8 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/4048-sunxi-r528-d1-t113-add-SDC2-pinmux-on-PC2-7-pins.patch @@ -0,0 +1,31 @@ +From bbc0d9a9ee7da3b64d70010e79098c1ca24c351c Mon Sep 17 00:00:00 2001 +From: Zoltan HERPAI +Date: Sat, 26 Aug 2023 21:09:17 +0200 +Subject: [PATCH 4048/4048] sunxi: r528/d1/t113: add SDC2 pinmux on PC2-7 pins + +Signed-off-by: Zoltan HERPAI +--- + board/sunxi/board.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 661137f43c..c00629f9b5 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -424,6 +424,13 @@ static void mmc_pinmux_setup(int sdc) + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); ++#elif defined(CONFIG_MACH_SUN8I_R528) ++ /* SDC2: PC2-PC7 */ ++ for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) { ++ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); ++ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); ++ sunxi_gpio_set_drv(pin, 2); ++ } + #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) + /* SDC2: PC5-PC6, PC8-PC16 */ + for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { +-- +2.20.1 + diff --git a/package/boot/uboot-sunxi/patches/4100-SQUASH-ME.patch b/package/boot/uboot-sunxi/patches/4100-SQUASH-ME.patch deleted file mode 100644 index 22bb1dd185..0000000000 --- a/package/boot/uboot-sunxi/patches/4100-SQUASH-ME.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 6ab5a9624210408ea57e957c3ebbafd35ece224d Mon Sep 17 00:00:00 2001 -From: Sam Edwards -Date: Thu, 1 Jun 2023 15:48:11 -0600 -Subject: [PATCH 4100/4103] SQUASH ME - -This patch contains only register defs for cpu_sunxi_ncat2.h, and should -be combined (as appropriate) into: - -sunxi: introduce NCAT2 generation model ---- - arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h -index d01508517c..25f71bbccd 100644 ---- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h -+++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h -@@ -17,6 +17,9 @@ - #define SUNXI_SIDC_BASE 0x03006000 - #define SUNXI_SID_BASE 0x03006200 - #define SUNXI_TIMER_BASE 0x02050000 -+#define SUNXI_GIC400_BASE 0x03020000 -+#define SUNXI_CPUX_BASE 0x09010000 -+#define SUNXI_CPUCFG_BASE 0 - - #ifdef CONFIG_MACH_SUN50I_H6 - #define SUNXI_DRAM_COM_BASE 0x04002000 -@@ -34,11 +37,11 @@ - #define SUNXI_SPI0_BASE 0x04025000 - #define SUNXI_SPI1_BASE 0x04026000 - --#define SUNXI_RTC_BASE 0x07000000 - #define SUNXI_R_CPUCFG_BASE 0x07000400 - #define SUNXI_PRCM_BASE 0x07010000 - #define SUNXI_R_WDOG_BASE 0x07020400 --#define SUNXI_R_TWI_BASE 0x07081400 -+#define SUNXI_R_TWI_BASE 0x07020800 -+#define SUNXI_RTC_BASE 0x07090000 - - #ifndef __ASSEMBLY__ - void sunxi_board_init(void); --- -2.20.1 - diff --git a/package/boot/uboot-sunxi/patches/4101-sunxi-psci-clean-away-preprocessor-macros.patch b/package/boot/uboot-sunxi/patches/4101-sunxi-psci-clean-away-preprocessor-macros.patch deleted file mode 100644 index 842e47c9e8..0000000000 --- a/package/boot/uboot-sunxi/patches/4101-sunxi-psci-clean-away-preprocessor-macros.patch +++ /dev/null @@ -1,148 +0,0 @@ -From a183878133f04cb53810e2e70cb39169efde27c4 Mon Sep 17 00:00:00 2001 -From: Sam Edwards -Date: Thu, 1 Jun 2023 15:48:12 -0600 -Subject: [PATCH 4101/4103] sunxi: psci: clean away preprocessor macros - -This patch restructures psci.c to get away from the "many different -function definitions switched by #ifdef" paradigm to the preferred style -of having a single function definition with `if (IS_ENABLED(...))` to -make the optimizer include only the appropriate function bodies instead. - -There are no functional changes here. - -Signed-off-by: Sam Edwards ---- - arch/arm/cpu/armv7/sunxi/psci.c | 94 ++++++++++++++------------------- - 1 file changed, 41 insertions(+), 53 deletions(-) - -diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c -index e1d3638b5c..7809b074f8 100644 ---- a/arch/arm/cpu/armv7/sunxi/psci.c -+++ b/arch/arm/cpu/armv7/sunxi/psci.c -@@ -76,28 +76,24 @@ static void __secure __mdelay(u32 ms) - isb(); - } - --static void __secure clamp_release(u32 __maybe_unused *clamp) -+static void __secure clamp_release(u32 *clamp) - { --#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ -- defined(CONFIG_MACH_SUN8I_H3) || \ -- defined(CONFIG_MACH_SUN8I_R40) -- u32 tmp = 0x1ff; -- do { -- tmp >>= 1; -- writel(tmp, clamp); -- } while (tmp); -- -- __mdelay(10); --#endif -+ if (clamp) { -+ u32 tmp = 0x1ff; -+ do { -+ tmp >>= 1; -+ writel(tmp, clamp); -+ } while (tmp); -+ -+ __mdelay(10); -+ } - } - --static void __secure clamp_set(u32 __maybe_unused *clamp) -+static void __secure clamp_set(u32 *clamp) - { --#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ -- defined(CONFIG_MACH_SUN8I_H3) || \ -- defined(CONFIG_MACH_SUN8I_R40) -- writel(0xff, clamp); --#endif -+ if (clamp) { -+ writel(0xff, clamp); -+ } - } - - static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, -@@ -118,53 +114,45 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, - } - } - --#ifdef CONFIG_MACH_SUN8I_R40 --/* secondary core entry address is programmed differently on R40 */ - static void __secure sunxi_set_entry_address(void *entry) - { -- writel((u32)entry, -- SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); --} --#else --static void __secure sunxi_set_entry_address(void *entry) --{ -- struct sunxi_cpucfg_reg *cpucfg = -- (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; -+ /* secondary core entry address is programmed differently on R40 */ -+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { -+ writel((u32)entry, -+ SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); -+ } else { -+ struct sunxi_cpucfg_reg *cpucfg = -+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; - -- writel((u32)entry, &cpucfg->priv0); -+ writel((u32)entry, &cpucfg->priv0); -+ } - } --#endif - --#ifdef CONFIG_MACH_SUN7I --/* sun7i (A20) is different from other single cluster SoCs */ --static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on) --{ -- struct sunxi_cpucfg_reg *cpucfg = -- (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; -- -- sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, -- on, 0); --} --#elif defined CONFIG_MACH_SUN8I_R40 - static void __secure sunxi_cpu_set_power(int cpu, bool on) - { - struct sunxi_cpucfg_reg *cpucfg = - (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; - -- sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu), -- (void *)cpucfg + SUN8I_R40_PWROFF, -- on, cpu); --} --#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */ --static void __secure sunxi_cpu_set_power(int cpu, bool on) --{ -- struct sunxi_prcm_reg *prcm = -- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; -+ /* sun7i (A20) is different from other single cluster SoCs */ -+ if (IS_ENABLED(CONFIG_MACH_SUN7I)) { -+ sunxi_power_switch(NULL, &cpucfg->cpu1_pwroff, on, 0); -+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { -+ sunxi_power_switch(NULL, (void *)cpucfg + SUN8I_R40_PWROFF, -+ on, cpu); -+ } else { -+#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2) -+ struct sunxi_prcm_reg *prcm = -+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - -- sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, -- on, cpu); -+ u32 *clamp = &prcm->cpu_pwr_clamp[cpu]; -+ if (IS_ENABLED(CONFIG_MACH_SUN6I) || -+ IS_ENABLED(CONFIG_MACH_SUN8I_H3)) -+ clamp = NULL; -+ -+ sunxi_power_switch(clamp, &prcm->cpu_pwroff, on, cpu); -+#endif -+ } - } --#endif /* CONFIG_MACH_SUN7I */ - - void __secure sunxi_cpu_power_off(u32 cpuid) - { --- -2.20.1 - diff --git a/package/boot/uboot-sunxi/patches/4102-sunxi-psci-refactor-register-access-to-separate-func.patch b/package/boot/uboot-sunxi/patches/4102-sunxi-psci-refactor-register-access-to-separate-func.patch deleted file mode 100644 index 926bb7f8cd..0000000000 --- a/package/boot/uboot-sunxi/patches/4102-sunxi-psci-refactor-register-access-to-separate-func.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 1422f560d647d466f2b99fbc917ac4f6a1d3af38 Mon Sep 17 00:00:00 2001 -From: Sam Edwards -Date: Thu, 1 Jun 2023 15:48:13 -0600 -Subject: [PATCH 4102/4103] sunxi: psci: refactor register access to separate - functions - -This is to prepare for R528, which does not have the typical -"CPUCFG" block; it has a "CPUX" block which provides these -same functions but is organized differently. - -Moving the hardware-access bits to their own functions separates the -logic from the hardware so we can reuse the same logic. - -Signed-off-by: Sam Edwards ---- - arch/arm/cpu/armv7/sunxi/psci.c | 66 +++++++++++++++++++++++---------- - 1 file changed, 47 insertions(+), 19 deletions(-) - -diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c -index 7809b074f8..94120e7526 100644 ---- a/arch/arm/cpu/armv7/sunxi/psci.c -+++ b/arch/arm/cpu/armv7/sunxi/psci.c -@@ -114,7 +114,7 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, - } - } - --static void __secure sunxi_set_entry_address(void *entry) -+static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry) - { - /* secondary core entry address is programmed differently on R40 */ - if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { -@@ -154,30 +154,60 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on) - } - } - --void __secure sunxi_cpu_power_off(u32 cpuid) -+static void __secure sunxi_cpu_set_reset(int cpu, bool reset) -+{ -+ struct sunxi_cpucfg_reg *cpucfg = -+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; -+ -+ writel(reset ? 0b00 : 0b11, &cpucfg->cpu[cpu].rst); -+} -+ -+static void __secure sunxi_cpu_set_locking(int cpu, bool lock) - { - struct sunxi_cpucfg_reg *cpucfg = - (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; -+ -+ if (lock) -+ clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); -+ else -+ setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); -+} -+ -+static bool __secure sunxi_cpu_poll_wfi(int cpu) -+{ -+ struct sunxi_cpucfg_reg *cpucfg = -+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; -+ -+ return !!(readl(&cpucfg->cpu[cpu].status) & BIT(2)); -+} -+ -+static void __secure sunxi_cpu_invalidate_cache(int cpu) -+{ -+ struct sunxi_cpucfg_reg *cpucfg = -+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; -+ -+ clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu)); -+} -+ -+void __secure sunxi_cpu_power_off(u32 cpuid) -+{ - u32 cpu = cpuid & 0x3; - - /* Wait for the core to enter WFI */ -- while (1) { -- if (readl(&cpucfg->cpu[cpu].status) & BIT(2)) -- break; -+ while (!sunxi_cpu_poll_wfi(cpu)) - __mdelay(1); -- } - - /* Assert reset on target CPU */ -- writel(0, &cpucfg->cpu[cpu].rst); -+ sunxi_cpu_set_reset(cpu, true); - - /* Lock CPU (Disable external debug access) */ -- clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); -+ sunxi_cpu_set_locking(cpu, true); - - /* Power down CPU */ - sunxi_cpu_set_power(cpuid, false); - -- /* Unlock CPU (Disable external debug access) */ -- setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); -+ /* Unlock CPU (Reenable external debug access) */ -+ sunxi_cpu_set_locking(cpu, false); - } - - static u32 __secure cp15_read_scr(void) -@@ -234,33 +264,31 @@ out: - int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc, - u32 context_id) - { -- struct sunxi_cpucfg_reg *cpucfg = -- (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; - u32 cpu = (mpidr & 0x3); - - /* store target PC and context id */ - psci_save(cpu, pc, context_id); - - /* Set secondary core power on PC */ -- sunxi_set_entry_address(&psci_cpu_entry); -+ sunxi_cpu_set_entry(cpu, &psci_cpu_entry); - - /* Assert reset on target CPU */ -- writel(0, &cpucfg->cpu[cpu].rst); -+ sunxi_cpu_set_reset(cpu, true); - - /* Invalidate L1 cache */ -- clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu)); -+ sunxi_cpu_invalidate_cache(cpu); - - /* Lock CPU (Disable external debug access) */ -- clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); -+ sunxi_cpu_set_locking(cpu, true); - - /* Power up target CPU */ - sunxi_cpu_set_power(cpu, true); - - /* De-assert reset on target CPU */ -- writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst); -+ sunxi_cpu_set_reset(cpu, false); - -- /* Unlock CPU (Disable external debug access) */ -- setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); -+ /* Unlock CPU (Reenable external debug access) */ -+ sunxi_cpu_set_locking(cpu, false); - - return ARM_PSCI_RET_SUCCESS; - } --- -2.20.1 - diff --git a/package/boot/uboot-sunxi/patches/4103-sunxi-psci-implement-PSCI-on-R528.patch b/package/boot/uboot-sunxi/patches/4103-sunxi-psci-implement-PSCI-on-R528.patch deleted file mode 100644 index e57d6b8492..0000000000 --- a/package/boot/uboot-sunxi/patches/4103-sunxi-psci-implement-PSCI-on-R528.patch +++ /dev/null @@ -1,154 +0,0 @@ -From bc42c4edff3af5b31702989527c4adb691838084 Mon Sep 17 00:00:00 2001 -From: Sam Edwards -Date: Thu, 1 Jun 2023 15:48:14 -0600 -Subject: [PATCH 4103/4103] sunxi: psci: implement PSCI on R528 - -This patch adds the necessary code to make nonsec booting and PSCI -secondary core management functional on the R528/T113. - -Signed-off-by: Sam Edwards -Tested-by: Maksim Kiselev ---- - arch/arm/cpu/armv7/sunxi/psci.c | 47 ++++++++++++++++++++++++++++++++- - arch/arm/mach-sunxi/Kconfig | 2 ++ - include/configs/sunxi-common.h | 8 ++++++ - 3 files changed, 56 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c -index 94120e7526..f3c1c459c2 100644 ---- a/arch/arm/cpu/armv7/sunxi/psci.c -+++ b/arch/arm/cpu/armv7/sunxi/psci.c -@@ -38,6 +38,19 @@ - #define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4) - #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc) - -+/* -+ * R528 is also different, as it has both cores powered up (but held in reset -+ * state) after the SoC is reset. Like the R40, it uses a "soft" entry point -+ * address register, but unlike the R40, it uses a newer "CPUX" block to manage -+ * CPU state, rather than the older CPUCFG system. -+ */ -+#define SUN8I_R528_SOFT_ENTRY (0x1c8) -+#define SUN8I_R528_C0_RST_CTRL (0x0000) -+#define SUN8I_R528_C0_CTRL_REG0 (0x0010) -+#define SUN8I_R528_C0_CPU_STATUS (0x0080) -+ -+#define SUN8I_R528_C0_STATUS_STANDBYWFI (16) -+ - static void __secure cp15_write_cntp_tval(u32 tval) - { - asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval)); -@@ -116,10 +129,13 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, - - static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry) - { -- /* secondary core entry address is programmed differently on R40 */ -+ /* secondary core entry address is programmed differently on R40/528 */ - if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { - writel((u32)entry, - SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); -+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { -+ writel((u32)entry, -+ SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY); - } else { - struct sunxi_cpucfg_reg *cpucfg = - (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; -@@ -139,6 +155,8 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on) - } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { - sunxi_power_switch(NULL, (void *)cpucfg + SUN8I_R40_PWROFF, - on, cpu); -+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { -+ /* R528 leaves both cores powered up, manages them via reset */ - } else { - #if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2) - struct sunxi_prcm_reg *prcm = -@@ -159,6 +177,17 @@ static void __secure sunxi_cpu_set_reset(int cpu, bool reset) - struct sunxi_cpucfg_reg *cpucfg = - (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; - -+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { -+ if (reset) { -+ clrbits_le32(SUNXI_CPUX_BASE + SUN8I_R528_C0_RST_CTRL, -+ BIT(cpu)); -+ } else { -+ setbits_le32(SUNXI_CPUX_BASE + SUN8I_R528_C0_RST_CTRL, -+ BIT(cpu)); -+ } -+ return; -+ } -+ - writel(reset ? 0b00 : 0b11, &cpucfg->cpu[cpu].rst); - } - -@@ -167,6 +196,11 @@ static void __secure sunxi_cpu_set_locking(int cpu, bool lock) - struct sunxi_cpucfg_reg *cpucfg = - (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; - -+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { -+ /* Not required on R528 */ -+ return; -+ } -+ - if (lock) - clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); - else -@@ -178,6 +212,11 @@ static bool __secure sunxi_cpu_poll_wfi(int cpu) - struct sunxi_cpucfg_reg *cpucfg = - (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; - -+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { -+ return !!(readl(SUNXI_CPUX_BASE + SUN8I_R528_C0_CPU_STATUS) & -+ BIT(SUN8I_R528_C0_STATUS_STANDBYWFI + cpu)); -+ } -+ - return !!(readl(&cpucfg->cpu[cpu].status) & BIT(2)); - } - -@@ -186,6 +225,12 @@ static void __secure sunxi_cpu_invalidate_cache(int cpu) - struct sunxi_cpucfg_reg *cpucfg = - (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; - -+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) { -+ clrbits_le32(SUNXI_CPUX_BASE + SUN8I_R528_C0_CTRL_REG0, -+ BIT(cpu)); -+ return; -+ } -+ - clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu)); - } - -diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig -index 59fa62c8d5..1d126a00ec 100644 ---- a/arch/arm/mach-sunxi/Kconfig -+++ b/arch/arm/mach-sunxi/Kconfig -@@ -321,6 +321,8 @@ config MACH_SUN8I_R40 - config MACH_SUN8I_R528 - bool "sun8i (Allwinner R528)" - select CPU_V7A -+ select CPU_V7_HAS_NONSEC -+ select ARCH_SUPPORT_PSCI - select SUNXI_GEN_NCAT2 - select SUNXI_NEW_PINCTRL - select MMC_SUNXI_HAS_NEW_MODE -diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h -index 2a8c54a7a8..0f6086e54f 100644 ---- a/include/configs/sunxi-common.h -+++ b/include/configs/sunxi-common.h -@@ -34,6 +34,14 @@ - - /* CPU */ - -+/* -+ * Newer ARM SoCs have moved the GIC, but have not updated their ARM cores to -+ * reflect the correct address in CBAR/PERIPHBASE. -+ */ -+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) -+#define CFG_ARM_GIC_BASE_ADDRESS 0x03020000 -+#endif -+ - /* - * The DRAM Base differs between some models. We cannot use macros for the - * CONFIG_FOO defines which contain the DRAM base address since they end --- -2.20.1 - diff --git a/package/boot/uboot-sunxi/patches/4200-spi.patch b/package/boot/uboot-sunxi/patches/4200-spi.patch deleted file mode 100644 index c4d20f5ebf..0000000000 --- a/package/boot/uboot-sunxi/patches/4200-spi.patch +++ /dev/null @@ -1,751 +0,0 @@ -From patchwork Fri May 19 13:40:07 2023 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Maksim Kiselev -X-Patchwork-Id: 1783781 -X-Patchwork-Delegate: andre.przywara@arm.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: legolas.ozlabs.org; - dkim=pass (2048-bit key; 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- Fri, 19 May 2023 06:40:31 -0700 (PDT) -Received: from localhost.localdomain ([176.221.215.212]) - by smtp.gmail.com with ESMTPSA id - l5-20020adfe585000000b002f7780eee10sm5315421wrm.59.2023.05.19.06.40.30 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Fri, 19 May 2023 06:40:30 -0700 (PDT) -From: Maxim Kiselev -To: u-boot@lists.denx.de -Cc: Maxim Kiselev , - Jagan Teki , - Andre Przywara , Rick Chen , - Leo -Subject: [RFC PATCH v1 1/3] sunxi: SPL SPI: Add SPI boot support for the - Allwinner R528/T113 SoCs -Date: Fri, 19 May 2023 16:40:07 +0300 -Message-Id: <20230519134010.3102343-2-bigunclemax@gmail.com> -X-Mailer: git-send-email 2.39.2 -In-Reply-To: <20230519134010.3102343-1-bigunclemax@gmail.com> -References: <20230519134010.3102343-1-bigunclemax@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -R528/T113 SoCs uses the same SPI IP as the H6, also have the same clocks -and reset bits layout, but the CCU base is different. Another difference -is that the new SoCs do not have a clock divider inside. Instead of this -we should configure sample mode depending on input clock rate. - -The pin assignment is also different: the H6 uses PC0, the R528/T113 PC4 -instead. This makes for a change in spi0_pinmux_setup() routine. - -This patch extends the H6/H616 #ifdef guards to also cover the R528/T113, -using the shared CONFIG_SUNXI_GEN_NCAT2 and CONFIG_MACH_SUN8I_R528 -symbols. Also use CONFIG_SUNXI_GEN_NCAT2 symbol for the Kconfig -dependency. - -Signed-off-by: Maxim Kiselev -Tested-by: Sam Edwards ---- - arch/arm/mach-sunxi/Kconfig | 2 +- - arch/arm/mach-sunxi/spl_spi_sunxi.c | 78 +++++++++++++++++++++-------- - 2 files changed, 58 insertions(+), 22 deletions(-) - -diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig -index 142d86afc6..210dd41176 100644 ---- a/arch/arm/mach-sunxi/Kconfig -+++ b/arch/arm/mach-sunxi/Kconfig -@@ -998,7 +998,7 @@ config SPL_STACK_R_ADDR - - config SPL_SPI_SUNXI - bool "Support for SPI Flash on Allwinner SoCs in SPL" -- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV -+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2 - help - Enable support for SPI Flash. This option allows SPL to read from - sunxi SPI Flash. It uses the same method as the boot ROM, so does -diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c -index c2410dd7bb..3cfbf56d59 100644 ---- a/arch/arm/mach-sunxi/spl_spi_sunxi.c -+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c -@@ -73,18 +73,27 @@ - #define SUN6I_CTL_ENABLE BIT(0) - #define SUN6I_CTL_MASTER BIT(1) - #define SUN6I_CTL_SRST BIT(31) -+#define SUN6I_TCR_SDM BIT(13) - #define SUN6I_TCR_XCH BIT(31) - - /*****************************************************************************/ - --#define CCM_AHB_GATING0 (0x01C20000 + 0x60) --#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) --#ifdef CONFIG_SUN50I_GEN_H6 --#define CCM_SPI0_CLK (0x03001000 + 0x940) -+#if defined(CONFIG_SUN50I_GEN_H6) -+#define CCM_BASE 0x03001000 -+#elif defined(CONFIG_SUNXI_GEN_NCAT2) -+#define CCM_BASE 0x02001000 - #else --#define CCM_SPI0_CLK (0x01C20000 + 0xA0) -+#define CCM_BASE 0x01C20000 - #endif --#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) -+ -+#define CCM_AHB_GATING0 (CCM_BASE + 0x60) -+#define CCM_H6_SPI_BGR_REG (CCM_BASE + 0x96c) -+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) -+#define CCM_SPI0_CLK (CCM_BASE + 0x940) -+#else -+#define CCM_SPI0_CLK (CCM_BASE + 0xA0) -+#endif -+#define SUN6I_BUS_SOFT_RST_REG0 (CCM_BASE + 0x2C0) - - #define AHB_RESET_SPI0_SHIFT 20 - #define AHB_GATE_OFFSET_SPI0 20 -@@ -102,17 +111,22 @@ - */ - static void spi0_pinmux_setup(unsigned int pin_function) - { -- /* All chips use PC0 and PC2. */ -- sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); -+ /* All chips use PC2. And all chips use PC0, except R528/T113 */ -+ if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) -+ sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); -+ - sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - -- /* All chips except H6 and H616 use PC1. */ -- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) -+ /* All chips except H6/H616/R528/T113 use PC1. */ -+ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && -+ !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - -- if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) -+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || -+ IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); -- if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) -+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || -+ IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); - - /* Older generations use PC23 for CS, newer ones use PC3. */ -@@ -126,7 +140,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) - static bool is_sun6i_gen_spi(void) - { - return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || -- IS_ENABLED(CONFIG_SUN50I_GEN_H6); -+ IS_ENABLED(CONFIG_SUN50I_GEN_H6) || -+ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2); - } - - static uintptr_t spi0_base_address(void) -@@ -137,6 +152,9 @@ static uintptr_t spi0_base_address(void) - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) - return 0x05010000; - -+ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) -+ return 0x04025000; -+ - if (!is_sun6i_gen_spi() || - IS_ENABLED(CONFIG_MACH_SUNIV)) - return 0x01C05000; -@@ -152,23 +170,30 @@ static void spi0_enable_clock(void) - uintptr_t base = spi0_base_address(); - - /* Deassert SPI0 reset on SUN6I */ -- if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) -+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || -+ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) - setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); - else if (is_sun6i_gen_spi()) - setbits_le32(SUN6I_BUS_SOFT_RST_REG0, - (1 << AHB_RESET_SPI0_SHIFT)); - - /* Open the SPI0 gate */ -- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) -+ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && -+ !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) - setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); - - if (IS_ENABLED(CONFIG_MACH_SUNIV)) { - /* Divide by 32, clock source is AHB clock 200MHz */ - writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL); - } else { -- /* Divide by 4 */ -- writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? -- SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); -+ /* New SoCs do not have a clock divider inside */ -+ if (!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { -+ /* Divide by 4 */ -+ writel(SPI0_CLK_DIV_BY_4, -+ base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : -+ SUN4I_SPI0_CCTL)); -+ } -+ - /* 24MHz from OSC24M */ - writel((1 << 31), CCM_SPI0_CLK); - } -@@ -180,6 +205,14 @@ static void spi0_enable_clock(void) - /* Wait for completion */ - while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) - ; -+ -+ /* -+ * For new SoCs we should configure sample mode depending on -+ * input clock. As 24MHz from OSC24M is used, we could use -+ * normal sample mode by setting SDM bit in the TCR register -+ */ -+ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) -+ setbits_le32(base + SUN6I_SPI0_TCR, SUN6I_TCR_SDM); - } else { - /* Enable SPI in the master mode and reset FIFO */ - setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | -@@ -206,11 +239,13 @@ static void spi0_disable_clock(void) - writel(0, CCM_SPI0_CLK); - - /* Close the SPI0 gate */ -- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) -+ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && -+ !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) - clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); - - /* Assert SPI0 reset on SUN6I */ -- if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) -+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || -+ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) - clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); - else if (is_sun6i_gen_spi()) - clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, -@@ -224,7 +259,8 @@ static void spi0_init(void) - if (IS_ENABLED(CONFIG_MACH_SUN50I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6)) - pin_function = SUN50I_GPC_SPI0; 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- Fri, 19 May 2023 06:40:36 -0700 (PDT) -Received: from localhost.localdomain ([176.221.215.212]) - by smtp.gmail.com with ESMTPSA id - l5-20020adfe585000000b002f7780eee10sm5315421wrm.59.2023.05.19.06.40.35 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Fri, 19 May 2023 06:40:35 -0700 (PDT) -From: Maxim Kiselev -To: u-boot@lists.denx.de -Cc: Maxim Kiselev , - Jagan Teki , - Andre Przywara , Rick Chen , - Leo -Subject: [RFC PATCH v1 2/3] spi: sunxi: Add support for R329/D1/R528/T113 SPI - controller -Date: Fri, 19 May 2023 16:40:08 +0300 -Message-Id: <20230519134010.3102343-3-bigunclemax@gmail.com> -X-Mailer: git-send-email 2.39.2 -In-Reply-To: <20230519134010.3102343-1-bigunclemax@gmail.com> -References: <20230519134010.3102343-1-bigunclemax@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -These SoCs have two SPI controllers that are quite similar to the SPI -on previous Allwinner SoCs. The main difference is that new SoCs -don't have a clock divider (SPI_CCR register) inside SPI IP. - -Instead SPI sample mode should be configured depending on the input clock. - -For now SPI input clock source selection is not supported by this driver, -and only HOSC@24MHz can be used as input clock. Therefore, according to -the, manual we could change the SPI sample mode from delay half -cycle(default) to normal. - -This patch adds a quirk for this kind of SPI controllers - -Signed-off-by: Maxim Kiselev -Tested-by: Sam Edwards ---- - drivers/spi/spi-sunxi.c | 34 +++++++++++++++++++++++++++++++++- - 1 file changed, 33 insertions(+), 1 deletion(-) - -diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c -index c56d82d998..9ec6b359e2 100644 ---- a/drivers/spi/spi-sunxi.c -+++ b/drivers/spi/spi-sunxi.c -@@ -117,6 +117,8 @@ enum sun4i_spi_bits { - SPI_TCR_XCH, - SPI_TCR_CS_MANUAL, - SPI_TCR_CS_LEVEL, -+ SPI_TCR_SDC, -+ SPI_TCR_SDM, - SPI_FCR_TF_RST, - SPI_FCR_RF_RST, - SPI_FSR_RF_CNT_MASK, -@@ -128,6 +130,7 @@ struct sun4i_spi_variant { - u32 fifo_depth; - bool has_soft_reset; - bool has_burst_ctl; -+ bool has_clk_ctl; - }; - - struct sun4i_spi_plat { -@@ -302,7 +305,19 @@ static int sun4i_spi_claim_bus(struct udevice *dev) - setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) | - SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW)); - -- sun4i_spi_set_speed_mode(dev->parent); -+ if (priv->variant->has_clk_ctl) { -+ sun4i_spi_set_speed_mode(dev->parent); -+ } else { -+ /* -+ * At this moment there is no ability to change input clock. -+ * Therefore, we can only use default HOSC@24MHz clock and -+ * set SPI sampling mode to normal -+ */ -+ clrsetbits_le32(SPI_REG(priv, SPI_TCR), -+ SPI_BIT(priv, SPI_TCR_SDC) | -+ SPI_BIT(priv, SPI_TCR_SDM), -+ SPI_BIT(priv, SPI_TCR_SDM)); -+ } - - return 0; - } -@@ -516,6 +531,8 @@ static const u32 sun6i_spi_bits[] = { - [SPI_TCR_CS_MASK] = 0x30, - [SPI_TCR_CS_MANUAL] = BIT(6), - [SPI_TCR_CS_LEVEL] = BIT(7), -+ [SPI_TCR_SDC] = BIT(11), -+ [SPI_TCR_SDM] = BIT(13), - [SPI_TCR_XCH] = BIT(31), - [SPI_FCR_RF_RST] = BIT(15), - [SPI_FCR_TF_RST] = BIT(31), -@@ -526,6 +543,7 @@ static const struct sun4i_spi_variant sun4i_a10_spi_variant = { - .regs = sun4i_spi_regs, - .bits = sun4i_spi_bits, - .fifo_depth = 64, -+ .has_clk_ctl = true, - }; - - static const struct sun4i_spi_variant sun6i_a31_spi_variant = { -@@ -534,6 +552,7 @@ static const struct sun4i_spi_variant sun6i_a31_spi_variant = { - .fifo_depth = 128, - .has_soft_reset = true, - .has_burst_ctl = true, -+ .has_clk_ctl = true, - }; - - static const struct sun4i_spi_variant sun8i_h3_spi_variant = { -@@ -542,6 +561,15 @@ static const struct sun4i_spi_variant sun8i_h3_spi_variant = { - .fifo_depth = 64, - .has_soft_reset = true, - .has_burst_ctl = true, -+ .has_clk_ctl = true, -+}; -+ -+static const struct sun4i_spi_variant sun50i_r329_spi_variant = { -+ .regs = sun6i_spi_regs, -+ .bits = sun6i_spi_bits, -+ .fifo_depth = 64, -+ .has_soft_reset = true, -+ .has_burst_ctl = true, - }; - - static const struct udevice_id sun4i_spi_ids[] = { -@@ -557,6 +585,10 @@ static const struct udevice_id sun4i_spi_ids[] = { - .compatible = "allwinner,sun8i-h3-spi", - .data = (ulong)&sun8i_h3_spi_variant, - }, -+ { -+ .compatible = "allwinner,sun50i-r329-spi", -+ .data = (ulong)&sun50i_r329_spi_variant, -+ }, - { /* sentinel */ } - }; - - -From patchwork Fri May 19 13:40:09 2023 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Maksim Kiselev -X-Patchwork-Id: 1783783 -X-Patchwork-Delegate: andre.przywara@arm.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; 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- Fri, 19 May 2023 06:40:39 -0700 (PDT) -From: Maxim Kiselev -To: u-boot@lists.denx.de -Cc: Maxim Kiselev , - Jagan Teki , - Andre Przywara , Rick Chen , - Leo -Subject: [RFC PATCH v1 3/3] riscv: dts: allwinner: d1: Add SPI controllers - node -Date: Fri, 19 May 2023 16:40:09 +0300 -Message-Id: <20230519134010.3102343-4-bigunclemax@gmail.com> -X-Mailer: git-send-email 2.39.2 -In-Reply-To: <20230519134010.3102343-1-bigunclemax@gmail.com> -References: <20230519134010.3102343-1-bigunclemax@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have -an optional SPI flash that connects to the SPI0 controller. - -This controller is the same for R329/D1/R528/T113s SoCs and -should be supported by the sun50i-r329-spi driver. - -So let's add its DT nodes. - -Signed-off-by: Maxim Kiselev -Reviewed-by: Sam Edwards ---- - arch/riscv/dts/sunxi-d1s-t113.dtsi | 37 ++++++++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - -diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi -index a7c95f59a0..094ad0e460 100644 ---- a/arch/riscv/dts/sunxi-d1s-t113.dtsi -+++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi -@@ -123,6 +123,12 @@ - function = "emac"; - }; - -+ /omit-if-no-ref/ -+ spi0_pins: spi0-pins { -+ pins = "PC2", "PC3", "PC4", "PC5"; -+ function = "spi0"; -+ }; -+ - /omit-if-no-ref/ - uart1_pg6_pins: uart1-pg6-pins { - pins = "PG6", "PG7"; -@@ -456,6 +462,37 @@ - #size-cells = <0>; - }; - -+ spi0: spi@4025000 { -+ compatible = "allwinner,sun20i-d1-spi", -+ "allwinner,sun50i-r329-spi"; -+ reg = <0x04025000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; -+ clock-names = "ahb", "mod"; -+ dmas = <&dma 22>, <&dma 22>; -+ dma-names = "rx", "tx"; -+ resets = <&ccu RST_BUS_SPI0>; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ spi1: spi@4026000 { -+ compatible = "allwinner,sun20i-d1-spi-dbi", -+ "allwinner,sun50i-r329-spi-dbi", -+ "allwinner,sun50i-r329-spi"; -+ reg = <0x04026000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; -+ clock-names = "ahb", "mod"; -+ dmas = <&dma 23>, <&dma 23>; -+ dma-names = "rx", "tx"; -+ resets = <&ccu RST_BUS_SPI1>; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ - usb_otg: usb@4100000 { - compatible = "allwinner,sun20i-d1-musb", - "allwinner,sun8i-a33-musb"; -- 2.30.2