# KBUILD_MODULES := 1
#endif
+define size_check
+ actual=$$( wc -c $1 | awk '{print $$1}'); \
+ limit=$$( printf "%d" $2 ); \
+ if test $$actual -gt $$limit; then \
+ echo "$1 exceeds file size limit:" >&2; \
+ echo " limit: $$limit bytes" >&2; \
+ echo " actual: $$actual bytes" >&2; \
+ echo " excess: $$((actual - limit)) bytes" >&2; \
+ exit 1; \
+ fi
+endef
+export size_check
+
export KBUILD_MODULES KBUILD_BUILTIN
export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
#########################################################################
ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
-BOARD_SIZE_CHECK = \
- @actual=`wc -c $@ | awk '{print $$1}'`; \
- limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
- if test $$actual -gt $$limit; then \
- echo "$@ exceeds file size limit:" >&2 ; \
- echo " limit: $$limit bytes" >&2 ; \
- echo " actual: $$actual bytes" >&2 ; \
- echo " excess: $$((actual - limit)) bytes" >&2; \
- exit 1; \
- fi
+BOARD_SIZE_CHECK= @ $(call size_check,$@,$(CONFIG_BOARD_SIZE_LIMIT))
else
BOARD_SIZE_CHECK =
endif
+ifneq ($(CONFIG_SPL_SIZE_LIMIT),0)
+SPL_SIZE_CHECK = @$(call size_check,$@,$$(tools/spl_size_limit))
+else
+SPL_SIZE_CHECK =
+endif
+
# Statically apply RELA-style relocations (currently arm64 only)
# This is useful for arm64 where static relocation needs to be performed on
# the raw binary, but certain simulators only accept an ELF file (but don't
%.imx: %.bin
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+ $(BOARD_SIZE_CHECK)
%.vyb: %.imx
$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
spl/u-boot-spl.bin: spl/u-boot-spl
@:
+ $(SPL_SIZE_CHECK)
+
spl/u-boot-spl: tools prepare \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
envtools: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools/env
+tools-only: export TOOLS_ONLY=y
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
status = "okay";
u-boot,dm-spl;
};
+
+&sdhci {
+ u-boot,dm-spl;
+};
-/*
- * Copyright 2018 Logic PD, Inc.
- * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
/ {
keyboard {
debounce-interval = <10>;
wakeup-source;
};
+
btn3 {
gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
label = "btn3";
leds {
compatible = "gpio-leds";
- gen_led0 {
+ gen-led0 {
label = "led0";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led0>;
linux,default-trigger = "cpu0";
};
- gen_led1 {
+ gen-led1 {
label = "led1";
gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
};
- gen_led2 {
+ gen-led2 {
label = "led2";
gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- gen_led3 {
+ gen-led3 {
label = "led3";
gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
};
- reg_usb_otg_vbus: regulator-otg-vbus@0 {
+ reg_usb_otg_vbus: regulator-otg-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_otg>;
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- reg_usb_h1_vbus: regulator-usbh1vbus@1 {
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
};
- reg_3v3: regulator-3v3@2 {
+ reg_3v3: regulator-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_3v3>;
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
enable-active-high;
regulator-always-on;
};
- reg_enet: regulator-ethernet@3 {
+ reg_enet: regulator-ethernet {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_pwr>;
+ pinctrl-0 = <&pinctrl_reg_enet>;
compatible = "regulator-fixed";
regulator-name = "ethernet-supply";
regulator-min-microvolt = <3300000>;
vin-supply = <&sw4_reg>;
};
- reg_audio: regulator-audio@4 {
+ reg_audio: regulator-audio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_audio>;
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
- regulator-always-on;
vin-supply = <®_3v3>;
};
- reg_hdmi: regulator-hdmi@5 {
+ reg_hdmi: regulator-hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_hdmi>;
compatible = "regulator-fixed";
vin-supply = <®_3v3>;
};
- reg_uart3: regulator-uart3@6 {
+ reg_uart3: regulator-uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_uart3>;
compatible = "regulator-fixed";
vin-supply = <®_3v3>;
};
- reg_1v8: regulator-1v8@7 {
+ reg_1v8: regulator-1v8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_1v8>;
compatible = "regulator-fixed";
vin-supply = <®_3v3>;
};
- reg_pcie: regulator@8 {
+ reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie_reg>;
- regulator-name = "MPCIE_3V3";
+ pinctrl-0 = <&pinctrl_reg_pcie>;
+ regulator-name = "mpcie_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
- mipi_pwr: regulator@9 {
+ reg_mipi: regulator-mipi {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mipi_pwr>;
+ pinctrl-0 = <&pinctrl_reg_mipi>;
regulator-name = "mipi_pwr_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
- audio-codec = <&codec>;
+ audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
status = "disabled";
};
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&usbh1 {
- vbus-supply = <®_usb_h1_vbus>;
- status = "okay";
-};
-
-&usbotg {
- vbus-supply = <®_usb_otg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- disable-over-current;
- status = "okay";
-};
-
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
phy-supply = <®_enet>;
status = "okay";
};
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- no-1-8-v;
- keep-power-in-suspend;
- status = "okay";
-};
-
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
- codec: wm8962@1a {
+ wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
reg = <0x10>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
- DOVDD-supply = <&mipi_pwr>;
- AVDD-supply = <&mipi_pwr>;
- DVDD-supply = <&mipi_pwr>;
+ DOVDD-supply = <®_mipi>;
+ AVDD-supply = <®_mipi>;
+ DVDD-supply = <®_mipi>;
reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
};
};
+&ipu1_csi1_from_mipi_vc1 {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
+
&mipi_csi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
- status = "okay";
vpcie-supply = <®_pcie>;
- /* fsl,max-link-speed = <2>; */
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
};
&ssi2 {
status = "okay";
};
-&iomuxc {
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <®_3v3>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
>;
};
- pinctrl_i2c1: i2c1 {
+ pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
>;
};
- pinctrl_enet_pwr: enet_pwr {
+ pinctrl_enet: enetgrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
>;
};
- pinctrl_mipi_pwr: pwr_mipi {
- fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_led0: led0grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
};
pinctrl_ov5640: ov5640grp {
>;
};
- pinctrl_reg_hdmi: reg_hdmi {
+ pinctrl_pcf8574: pcf8575grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
>;
};
- pinctrl_uart3: uart3grp {
+ pinctrl_pcie: pciegrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
- MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
- >;
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
};
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
- >;
+ pinctrl_reg_1v8: reg1v8grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ >;
};
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
- >;
- };
-
- pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
- >;
+ pinctrl_reg_3v3: reg3v3grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
+ >;
};
- pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
+ pinctrl_reg_audio: reg-audiogrp {
fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
>;
};
- pinctrl_enet: enetgrp {
+ pinctrl_reg_enet: reg-enetgrp {
fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
>;
};
- pinctrl_reg_audio: audio-reg {
+ pinctrl_reg_hdmi: reg-hdmigrp {
fsl,pins = <
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
>;
};
- pinctrl_pcie: pcie {
- fsl,pins = <
- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
- >;
+ pinctrl_reg_mipi: reg-mipigrp {
+ fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
};
- pinctrl_pcie_reg: pciereggrp {
+ pinctrl_reg_pcie: reg-pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
- pinctrl_pcf8574: pcf8575-pins {
+ pinctrl_reg_uart3: reguart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_reg_usb_h1_vbus: usbh1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
- pinctrl_lcd: lcdgrp {
+ pinctrl_reg_usb_otg: reg-usb-otggrp {
fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */
- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */
- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
- pinctrl_pwm3: pwm3grp {
+ pinctrl_uart3: uart3grp {
fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
};
- pinctrl_reg_uart3: uart3reg {
+ pinctrl_usbotg: usbotggrp {
fsl,pins = <
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
>;
};
- pinctrl_reg_3v3: reg-3v3 {
+ pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
>;
};
- pinctrl_reg_1v8: reg-1v8 {
+ pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
fsl,pins = <
- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
- pinctrl_led0: led0 {
+ pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
fsl,pins = <
- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
>;
};
+
};
-/*
- * Copyright 2018 Logic PD
- * This file is adapted from imx6qdl-sabresd.dtsi.
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
stdout-path = &uart1;
};
- memory {
+ memory@10000000 {
+ device_type = "memory";
reg = <0x10000000 0x80000000>;
};
};
};
-/* Reroute power feeding the CPU to come from the external PMIC */
-®_arm
-{
- vin-supply = <&sw1a_reg>;
-};
-
-®_soc
-{
- vin-supply = <&sw1c_reg>;
-};
-
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- status = "okay";
nand-on-flash-bbt;
+ status = "okay";
};
&i2c3 {
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
- pmic: pfuze100@08 {
+ pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulator-max-microvolt = <3300000>;
regulator-name = "gen_3v3";
regulator-boot-on;
- /* regulator-always-on; */
};
sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-name = "sw3a_vddr";
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-name = "sw3b_vddr";
regulator-boot-on;
regulator-always-on;
vgen3_reg: vgen3 {
regulator-name = "gen_vadj_0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
};
vgen5_reg: vgen5 {
- regulator-name = "gen_adj_1";
- regulator-min-microvolt = <3300000>;
+ regulator-name = "gen_vadj_1";
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
- temp_sense0: tmp102@4a {
+ temperature-sensor@49 {
compatible = "ti,tmp102";
- reg = <0x4a>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tempsense>;
+ reg = <0x49>;
interrupt-parent = <&gpio6>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
- temp_sense1: tmp102@49 {
+ temperature-sensor@4a {
compatible = "ti,tmp102";
- reg = <0x49>;
+ reg = <0x4a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tempsense>;
interrupt-parent = <&gpio6>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
- mfg_eeprom: at24@51 {
+ eeprom@51 {
compatible = "atmel,24c64";
pagesize = <32>;
- read-only;
+ read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x51>;
};
- user_eeprom: at24@52 {
+ eeprom@52 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x52>;
};
};
+/* Reroute power feeding the CPU to come from the external PMIC */
+®_arm
+{
+ vin-supply = <&sw1a_reg>;
+};
+
+®_soc
+{
+ vin-supply = <&sw1c_reg>;
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
- pinctrl_hog: hoggrp {
+ pinctrl_gpmi_nand: gpmi-nandgrp {
fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = < /* Enable ARM Debugger */
MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
>;
};
- pinctrl_gpmi_nand: gpminandgrp {
+ pinctrl_i2c3: i2c3grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
- pinctrl_i2c3: i2c3grp {
+ pinctrl_tempsense: tempsensegrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
>;
};
-
- pinctrl_tempsense: tempsensegrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */
- >;
- };
};
&snvs_poweroff {
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
uart-has-rtscts;
+ status = "okay";
+
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_usdhc1>;
non-removable;
keep-power-in-suspend;
- enable-sdio-wakeup;
- status = "okay";
+ wakeup-source;
vmmc-supply = <&sw2_reg>;
+ status = "okay";
};
&usdhc3 {
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <®_wl18xx_vmmc>;
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
+ status = "okay";
+
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
-/*
- * Copyright 2018 Logic PD, Inc.
- * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6-logicpd-baseboard.dtsi"
/ {
- model = "Logic PD i.MX6QD SOM-M3 (HDMI)";
+ model = "Logic PD i.MX6QD SOM-M3";
compatible = "fsl,imx6q";
- backlight: backlight_lvds {
+ backlight: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm3 0 20000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
power-supply = <®_lcd>;
};
+ panel-lvds0 {
+ compatible = "okaya,rs800480t-7x0gp";
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
reg_lcd: regulator-lcd {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_reg>;
startup-delay-us = <500000>;
};
- lcd_reset: lcd_reset {
+ reg_lcd_reset: regulator-lcd-reset {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_reset>;
compatible = "regulator-fixed";
regulator-always-on;
vin-supply = <®_lcd>;
};
+};
- panel-lvds0 {
- compatible = "ampire,am800480b3tmqw";
- backlight = <&backlight>;
-
- port {
- panel_in_lvds0: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
- };
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
&hdmi {
status = "okay";
};
-&i2c1 {
- ili_touch: ilitouch@26 {
- compatible = "ili,ili2117a";
- reg = <0x26>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touchscreen>;
- interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
- ili2117a,poll-period = <10>;
- ili2117a,max-touch = <2>;
- };
-};
-
-®_hdmi {
- regulator-always-on;
-};
-
&ldb {
status = "okay";
port@4 {
reg = <4>;
-
lvds0_out: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
-&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
- <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
- <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
-};
-
&pwm3 {
status = "okay";
};
-&usdhc2 {
- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+®_hdmi {
+ regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */
};
&iomuxc {
pinctrl_lcd_reset: lcdreset {
fsl,pins = <
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
>;
};
>;
};
};
-
reg = <0x0 0x80000000 0x0 0x80000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05>;
avdd-pex-pll-supply = <&vdd_1v05>;
reg = <0x80000000 0x80000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;
reg = <0x80000000 0x80000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;
interrupt-parent = <&lic>;
- pcie-controller@01003000 {
+ pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x01003000 0x00000800 /* PADS registers */
power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;
};
- pcie-controller@10003000 {
+ pcie@10003000 {
status = "okay";
pci@1,0 {
power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
};
- pcie-controller@10003000 {
+ pcie@10003000 {
status = "okay";
pci@1,0 {
};
aliases {
+ ethernet = "/ethernet@2490000";
mmc0 = "/sdhci@3460000";
mmc1 = "/sdhci@3400000";
i2c0 = "/bpmp/i2c";
ethernet@2490000 {
status = "okay";
phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
};
i2c@3160000 {
#interrupt-cells = <2>;
};
- pcie-controller@10003000 {
+ pcie@10003000 {
compatible = "nvidia,tegra186-pcie";
device_type = "pci";
reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
nvidia,sys-clock-req-active-high;
};
- pcie-controller@80003000 {
+ pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;
spi-max-frequency = <25000000>;
};
- pcie-controller@80003000 {
+ pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;
reset-names = "fuse";
};
- pcie-controller@80003000 {
+ pcie@80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
reg = <0x80003000 0x00000800 /* PADS registers */
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
pci@1,0 {
#address-cells = <2>;
#size-cells = <2>;
- pcie-controller@01003000 {
+ pcie@1003000 {
compatible = "nvidia,tegra210-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
reg = <0x80000000 0x40000000>;
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
avdd-pexa-supply = <&vdd2_reg>;
vdd-pexa-supply = <&vdd2_reg>;
reg = <0x80000000 0x7ff00000>;
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
avdd-pexa-supply = <&ldo1_reg>;
reg = <0x80000000 0x40000000>;
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
compatible = "nvidia,tegra30";
interrupt-parent = <&lic>;
- pcie-controller@00003000 {
+ pcie@3000 {
compatible = "nvidia,tegra30-pcie";
device_type = "pci";
reg = <0x00003000 0x00000800 /* PADS registers */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 NVIDIA Corporation. All rights reserved.
+ */
+
+#ifndef _TEGRA_CBOOT_H_
+#define _TEGRA_CBOOT_H_
+
+#ifdef CONFIG_ARM64
+extern unsigned long cboot_boot_x0;
+
+void cboot_save_boot_params(unsigned long x0, unsigned long x1,
+ unsigned long x2, unsigned long x3);
+int cboot_dram_init(void);
+int cboot_dram_init_banksize(void);
+ulong cboot_get_usable_ram_top(ulong total_size);
+int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]);
+#else
+static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1,
+ unsigned long x2, unsigned long x3)
+{
+}
+
+static inline int cboot_dram_init(void)
+{
+ return -ENOSYS;
+}
+
+static inline int cboot_dram_init_banksize(void)
+{
+ return -ENOSYS;
+}
+
+static inline ulong cboot_get_usable_ram_top(ulong total_size)
+{
+ return 0;
+}
+
+static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN])
+{
+ return -ENOSYS;
+}
+#endif
+
+#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2019
* NVIDIA Corporation <www.nvidia.com>
*/
/* APBDEV_PMC_CNTRL2_0 0x440 */
#define HOLD_CKE_LOW_EN (1 << 12)
+/* PMC read/write functions */
+u32 tegra_pmc_readl(unsigned long offset);
+void tegra_pmc_writel(u32 value, unsigned long offset);
+
+#define PMC_CNTRL 0x0
+#define PMC_CNTRL_MAIN_RST BIT(4)
+
+#if IS_ENABLED(CONFIG_TEGRA186)
+# define PMC_SCRATCH0 0x32000
+#else
+# define PMC_SCRATCH0 0x00050
+#endif
+
+/* for secure PMC */
+#define TEGRA_SMC_PMC 0xc2fffe00
+#define TEGRA_SMC_PMC_READ 0xaa
+#define TEGRA_SMC_PMC_WRITE 0xbb
+
#endif /* PMC_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_PMU_H_
+#define _TEGRA_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA_PMU_H_ */
#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+ defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \
+ defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210)
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
+#else
+#define NV_PA_PMC_BASE 0xc360000
+#endif
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA114_PMU_H_
-#define _TEGRA114_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _TEGRA114_PMU_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2013
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA124_PMU_H_
-#define _TEGRA124_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _TEGRA124_PMU_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _ARCH_PMU_H_
-#define _ARCH_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _ARCH_PMU_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA210_PMU_H_
-#define _TEGRA210_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _TEGRA210_PMU_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA30_PMU_H_
-#define _TEGRA30_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _TEGRA30_PMU_H_ */
#endif
tmp = readl(&pmc->mor);
+/*
+ * some boards have an external oscillator with driving.
+ * in this case we need to disable the internal SoC driving (bypass mode)
+ */
+#if defined(CONFIG_SPL_AT91_MCK_BYPASS)
+ tmp |= AT91_PMC_MOR_OSCBYPASS;
+#else
tmp &= ~AT91_PMC_MOR_OSCBYPASS;
+#endif
tmp &= ~AT91_PMC_MOR_KEY(0xff);
tmp |= AT91_PMC_MOR_KEY(0x37);
writel(tmp, &pmc->mor);
source "board/lego/ev3/Kconfig"
config SPL_LDSCRIPT
- default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390
default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
endif
obj-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
endif
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- */
-
-#include <config.h>
-
-#define MDSTAT_STATE 0x3f
-
-.globl lowlevel_init
-lowlevel_init:
-#ifdef CONFIG_SOC_DM644X
-
- /*-------------------------------------------------------*
- * Mask all IRQs by setting all bits in the EINT default *
- *-------------------------------------------------------*/
- mov r1, $0
- ldr r0, =EINT_ENABLE0
- str r1, [r0]
- ldr r0, =EINT_ENABLE1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Put the GEM in reset *
- *------------------------------------------------------*/
-
- /* Put the GEM in reset */
- ldr r8, PSC_GEM_FLAG_CLEAR
- ldr r6, MDCTL_GEM
- ldr r7, [r6]
- and r7, r7, r8
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x02
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x02
- bne checkStatClkStopGem
-
- /* Check for GEM Reset Completion */
-checkGemStatClkStop:
- ldr r6, MDSTAT_GEM
- ldr r7, [r6]
- ands r7, r7, $0x100
- bne checkGemStatClkStop
-
- /* Do this for enabling a WDT initiated reset this is a workaround
- for a chip bug. Not required under normal situations */
- ldr r6, P1394
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * Enable L1 & L2 Memories in Fast mode *
- *------------------------------------------------------*/
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, MMARG_BRF0
- ldr r10, MMARG_BRF0_VAL
- str r10, [r6]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * DDR2 PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r10, $0
- ldr r6, PLL2_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r10, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-WaitPPL2Loop:
- subs r10, r10, $1
- bne WaitPPL2Loop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL2_PLLM
- mov r2, $0x17 /* 162 MHz */
- str r2, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV2
- mov r3, $0x01
- str r3, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV1
- mov r4, $0x0b /* 54 MHz */
- str r4, [r6]
-
- /* PLL2 DIV2 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV2
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop_0:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop_0
-
- /* PLL2 DIV1 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV1
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0x218
-ResetPPL2Loop:
- subs r10, r10, $1
- bne ResetPPL2Loop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-PLL2Lock:
- subs r10, r10, $1
- bne PLL2Lock
-
- /* Enable the PLL */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x01
- str r8, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkStop
-
- /*------------------------------------------------------*
- * Program DDR2 MMRs for 162MHz Setting *
- *------------------------------------------------------*/
-
- /* Program PHY Control Register */
- ldr r6, DDRCTL
- ldr r7, DDRCTL_VAL
- str r7, [r6]
-
- /* Program SDRAM Bank Config Register */
- ldr r6, SDCFG
- ldr r7, SDCFG_VAL
- str r7, [r6]
-
- /* Program SDRAM TIM-0 Config Register */
- ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL_162MHz
- str r7, [r6]
-
- /* Program SDRAM TIM-1 Config Register */
- ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL_162MHz
- str r7, [r6]
-
- /* Program the SDRAM Bank Config Control Register */
- ldr r10, MASK_VAL
- ldr r8, SDCFG
- ldr r9, SDCFG_VAL
- and r9, r9, r10
- str r9, [r8]
-
- /* Program SDRAM SDREF Config Register */
- ldr r6, SDREF
- ldr r7, SDREF_VAL
- str r7, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Issue a Dummy DDR2 read/write */
- ldr r8, DDR2_START_ADDR
- ldr r7, DUMMY_VAL
- str r7, [r8]
- ldr r7, [r8]
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x01
- bne checkDDRStatClkStop2
-
- /*------------------------------------------------------*
- * Turn DDR2 Controller Clocks On *
- *------------------------------------------------------*/
-
- /* Enable the DDR2 LPSC Module */
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkEn2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkEn2
-
- /* DDR Writes and Reads */
- ldr r6, CFGTEST
- mov r3, $0x01
- str r3, [r6]
-
- /*------------------------------------------------------*
- * System PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r2, $0
- ldr r6, PLL1_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r2, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-
-WaitLoop:
- subs r10, r10, $1
- bne WaitLoop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Disable the PLL */
- orr r8, r8, $0x10
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL1_PLLM
- mov r3, $0x15 /* For 594MHz */
- str r3, [r6]
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0xff
-
-ResetLoop:
- subs r10, r10, $1
- bne ResetLoop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL1_CTL
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-
-PLL1Lock:
- subs r10, r10, $1
- bne PLL1Lock
-
- /* Enable the PLL */
- orr r8, r8, $0x01
- str r8, [r6]
-
- nop
- nop
- nop
- nop
-
- /*------------------------------------------------------*
- * AEMIF configuration for NOR Flash (double check) *
- *------------------------------------------------------*/
- ldr r0, _PINMUX0
- ldr r1, _DEV_SETTING
- str r1, [r0]
-
- ldr r0, WAITCFG
- ldr r1, WAITCFG_VAL
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
-
- ldr r0, ACFG3
- ldr r1, ACFG3_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG4
- ldr r1, ACFG4_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG5
- ldr r1, ACFG5_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- /*--------------------------------------*
- * VTP manual Calibration *
- *--------------------------------------*/
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR0
- str r1, [r0]
-
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR1
- str r1, [r0]
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTPLock:
- subs r10, r10, $1
- bne VTPLock
-
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, DDRVTPR
- ldr r7, [r6]
- mov r8, r7, LSL #32-10
- mov r8, r8, LSR #32-10 /* grab low 10 bits */
- ldr r7, VTP_RECAL
- orr r8, r7, r8
- ldr r7, VTP_EN
- orr r8, r7, r8
- str r8, [r0]
-
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTP1Lock:
- subs r10, r10, $1
- bne VTP1Lock
-
- ldr r1, [r0]
- ldr r2, VTP_MASK
- and r2, r1, r2
- str r2, [r0]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*
- * Call board-specific lowlevel init.
- * That MUST be present and THAT returns
- * back to arch calling code with "mov pc, lr."
- */
- b dv_board_init
-
-.ltorg
-
-_PINMUX0:
- .word 0x01c40000 /* Device Configuration Registers */
-_PINMUX1:
- .word 0x01c40004 /* Device Configuration Registers */
-
-_DEV_SETTING:
- .word 0x00000c1f
-
-WAITCFG:
- .word 0x01e00004
-WAITCFG_VAL:
- .word 0
-ACFG3:
- .word 0x01e00014
-ACFG3_VAL:
- .word 0x3ffffffd
-ACFG4:
- .word 0x01e00018
-ACFG4_VAL:
- .word 0x3ffffffd
-ACFG5:
- .word 0x01e0001c
-ACFG5_VAL:
- .word 0x3ffffffd
-
-MDCTL_DDR2:
- .word 0x01c41a34
-MDSTAT_DDR2:
- .word 0x01c41834
-
-PTCMD:
- .word 0x01c41120
-PTSTAT:
- .word 0x01c41128
-
-EINT_ENABLE0:
- .word 0x01c48018
-EINT_ENABLE1:
- .word 0x01c4801c
-
-PSC_FLAG_CLEAR:
- .word 0xffffffe0
-PSC_GEM_FLAG_CLEAR:
- .word 0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
- .word 0x200000e4
-DDRCTL_VAL:
- .word 0x50006405
-SDREF:
- .word 0x2000000c
-SDREF_VAL:
- .word 0x000005c3
-SDCFG:
- .word 0x20000008
-SDCFG_VAL:
-#ifdef DDR_4BANKS
- .word 0x00178622
-#elif defined DDR_8BANKS
- .word 0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
- .word 0x20000010
-SDTIM0_VAL_162MHz:
- .word 0x28923211
-SDTIM1:
- .word 0x20000014
-SDTIM1_VAL_162MHz:
- .word 0x0016c722
-VTPIOCR:
- .word 0x200000f0 /* VTP IO Control register */
-DDRVTPR:
- .word 0x01c42030 /* DDR VPTR MMR */
-VTP_MMR0:
- .word 0x201f
-VTP_MMR1:
- .word 0xa01f
-DFT_ENABLE:
- .word 0x01c4004c
-VTP_LOCK_COUNT:
- .word 0x5b0
-VTP_MASK:
- .word 0xffffdfff
-VTP_RECAL:
- .word 0x08000
-VTP_EN:
- .word 0x02000
-CFGTEST:
- .word 0x80010000
-MASK_VAL:
- .word 0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
- .word 0x01c41a9c
-MDSTAT_GEM:
- .word 0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
- .word 0x01c41a20
-
-PLL_CLKSRC_MASK:
- .word 0xfffffeff /* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
- .word 0xffffffdf /* Select the PLLEN source */
-PLL_BYPASS_MASK:
- .word 0xfffffffe /* Put the PLL in BYPASS */
-PLL_RESET_MASK:
- .word 0xfffffff7 /* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
- .word 0xfffffffd /* PLL Power up Mask Bit */
-PLL_DISABLE_ENABLE_MASK:
- .word 0xffffffef /* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
- .word 0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
- .word 0x01c40900
-PLL1_PLLM:
- .word 0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
- .word 0x01c40d00
-PLL2_PLLM:
- .word 0x01c40d10
-PLL2_DIV1:
- .word 0x01c40d18
-PLL2_DIV2:
- .word 0x01c40d1c
-PLL2_PLLCMD:
- .word 0x01c40d38
-PLL2_PLLSTAT:
- .word 0x01c40d3c
-PLL2_DIV_MASK:
- .word 0xffff7fff
-
-MMARG_BRF0:
- .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
- .word 0x00444400
-
-DDR2_START_ADDR:
- .word 0x80000000
-DUMMY_VAL:
- .word 0xa55aa55a
-#else /* CONFIG_SOC_DM644X */
- mov pc, lr
-#endif
}
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
-void spl_board_init(void)
+void board_init_f(ulong dummy)
{
arch_cpu_init();
+
+ spl_early_init();
+
preloader_console_init();
}
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
endif
-ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
-BOARD_SIZE_CHECK = \
- @actual=`wc -c $@ | awk '{print $$1}'`; \
- limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
- if test $$actual -gt $$limit; then \
- echo "$@ exceeds file size limit:" >&2 ; \
- echo " limit: $$limit bytes" >&2 ; \
- echo " actual: $$actual bytes" >&2 ; \
- echo " excess: $$((actual - limit)) bytes" >&2; \
- exit 1; \
- fi
-else
-BOARD_SIZE_CHECK =
-endif
-
PLUGIN = board/$(BOARDDIR)/plugin
ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
- $(BOARD_SIZE_CHECK)
ifeq ($(CONFIG_OF_SEPARATE),y)
MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
#endif
#ifdef CONFIG_DM_GPIO
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+/* Manually initialize GPIO banks when OF_CONTROL doesn't */
static const struct omap_gpio_platdata omap34xx_gpio[] = {
{ 0, OMAP34XX_GPIO1_BASE },
{ 1, OMAP34XX_GPIO2_BASE },
{ "gpio_omap", &omap34xx_gpio[4] },
{ "gpio_omap", &omap34xx_gpio[5] },
};
-
+#endif
#else
static const struct gpio_bank gpio_bank_34xx[6] = {
return timebase_h << 32 | timebase_l;
}
-static uint64_t usec_to_tick(unsigned int usec)
-{
- uint64_t tick = usec;
- tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000);
- return tick;
-}
-
void rockchip_udelay(unsigned int usec)
{
uint64_t tmp;
config SPL_SERIAL_SUPPORT
default y
+config TEGRA_CLKRST
+ bool
+
+config TEGRA_GP_PADCTRL
+ bool
+
config TEGRA_IVC
bool "Tegra IVC protocol"
help
U-Boot, it is typically used for communication between the main CPU
and various auxiliary processors.
+config TEGRA_MC
+ bool
+
+config TEGRA_PINCTRL
+ bool
+
+config TEGRA_PMC
+ bool
+
+config TEGRA_PMC_SECURE
+ bool
+ depends on TEGRA_PMC
+
config TEGRA_COMMON
bool "Tegra common options"
select BINMAN
select SPL
select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
+ select TEGRA_CLKRST
select TEGRA_COMMON
select TEGRA_GPIO
+ select TEGRA_GP_PADCTRL
+ select TEGRA_MC
select TEGRA_NO_BPMP
+ select TEGRA_PINCTRL
+ select TEGRA_PMC
config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
select ARM64
select LINUX_KERNEL_IMAGE_HEADER
+ select POSITION_INDEPENDENT
select TEGRA_COMMON
if TEGRA_ARMV8_COMMON
config TEGRA210
bool "Tegra210 family"
select TEGRA_ARMV8_COMMON
+ select TEGRA_CLKRST
select TEGRA_GPIO
+ select TEGRA_GP_PADCTRL
+ select TEGRA_MC
select TEGRA_NO_BPMP
+ select TEGRA_PINCTRL
+ select TEGRA_PMC
+ select TEGRA_PMC_SECURE
config TEGRA186
bool "Tegra186 family"
config TEGRA_DISCONNECT_UDC_ON_BOOT
bool "Disconnect USB device mode controller on boot"
+ depends on CI_UDC
default y
help
When loading U-Boot into RAM over USB protocols using tools such as
# SPDX-License-Identifier: GPL-2.0+
#
-# (C) Copyright 2010-2015 Nvidia Corporation.
+# (C) Copyright 2010-2019 Nvidia Corporation.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_TEGRA186
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += cpu.o
obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
endif
-obj-y += ap.o
+obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o
obj-y += board.o board2.o
obj-y += cache.o
-obj-y += clock.o
-obj-y += pinmux-common.o
-obj-y += powergate.o
+obj-$(CONFIG_TEGRA_CLKRST) += clock.o
+obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o
+obj-$(CONFIG_TEGRA_PMC) += powergate.o
obj-y += xusb-padctl-dummy.o
-endif
-obj-$(CONFIG_ARM64) += arm64-mmu.o
+obj-$(CONFIG_ARM64) += arm64-mmu.o cboot.o
obj-y += dt-setup.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
obj-$(CONFIG_TEGRA_GPU) += gpu.o
obj-$(CONFIG_TEGRA_IVC) += ivc.o
-obj-y += lowlevel_init.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+obj-y += pmc.o
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
#include <ns16550.h>
#include <spl.h>
#include <asm/io.h>
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
+#endif
+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
#include <asm/arch/funcmux.h>
+#endif
+#if IS_ENABLED(CONFIG_TEGRA_MC)
#include <asm/arch/mc.h>
+#endif
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/cboot.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/warmboot.h>
static bool from_spl __attribute__ ((section(".data")));
#ifndef CONFIG_SPL_BUILD
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
{
from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
+
+ /*
+ * The logic for this is somewhat indirect. The purpose of the marker
+ * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
+ * was loaded from a read-only instance of itself, which is something
+ * that can happen in secure boot setups. So basically the presence
+ * of the marker is an indication that U-Boot was loaded by one such
+ * special variant of U-Boot. Conversely, the absence of the marker
+ * indicates that this instance of U-Boot was loaded by something
+ * other than a special U-Boot. This could be SPL, but it could just
+ * as well be one of any number of other first stage bootloaders.
+ */
+ if (from_spl)
+ cboot_save_boot_params(r0, r1, r2, r3);
+
save_boot_params_ret();
}
#endif
}
#endif
+#if IS_ENABLED(CONFIG_TEGRA_MC)
/* Read the RAM size directly from the memory controller */
static phys_size_t query_sdram_size(void)
{
return size_bytes;
}
+#endif
int dram_init(void)
{
+ int err;
+
+ /* try to initialize DRAM from cboot DTB first */
+ err = cboot_dram_init();
+ if (err == 0)
+ return 0;
+
+#if IS_ENABLED(CONFIG_TEGRA_MC)
/* We do not initialise DRAM here. We just query the size */
gd->ram_size = query_sdram_size();
+#endif
+
return 0;
}
+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
static int uart_configs[] = {
#if defined(CONFIG_TEGRA20)
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
}
}
}
+#endif
void board_init_uart_f(void)
{
+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
int uart_ids = 0; /* bit mask of which UART ids to enable */
#ifdef CONFIG_TEGRA_ENABLE_UARTA
uart_ids |= UARTE;
#endif
setup_uarts(uart_ids);
+#endif
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016, NVIDIA CORPORATION.
- */
-
-#include <common.h>
-#include <asm/arch/tegra.h>
-
-int board_early_init_f(void)
-{
- return 0;
-}
-
-__weak int tegra_board_init(void)
-{
- return 0;
-}
-
-int board_init(void)
-{
- return tegra_board_init();
-}
-
-__weak int tegra_soc_board_init_late(void)
-{
- return 0;
-}
-
-int board_late_init(void)
-{
- return tegra_soc_board_init_late();
-}
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/cboot.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/pmu.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/uart.h>
#include <asm/arch-tegra/warmboot.h>
#include <asm/arch-tegra/gpu.h>
#include <asm/arch-tegra/usb.h>
#include <asm/arch-tegra/xusb-padctl.h>
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
+#endif
+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/pmu.h>
+#endif
#include <asm/arch/tegra.h>
#ifdef CONFIG_TEGRA_CLOCK_SCALING
#include <asm/arch/emc.h>
__weak void gpio_early_init_uart(void) {}
__weak void pin_mux_display(void) {}
__weak void start_cpu_fan(void) {}
+__weak void cboot_late_init(void) {}
#if defined(CONFIG_TEGRA_NAND)
__weak void pin_mux_nand(void)
__maybe_unused int board_id;
/* Do clocks and UART first so that printf() works */
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
clock_init();
clock_verify();
+#endif
tegra_gpu_config();
int board_early_init_f(void)
{
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
if (!clock_early_init_done())
clock_early_init();
+#endif
#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
#define USBCMD_FS2 (1 << 15)
#endif
/* Do any special system timer/TSC setup */
-#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
+# if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (!tegra_cpu_is_non_secure())
-#endif
+# endif
arch_timer_init();
+#endif
pinmux_init();
board_init_uart_f();
}
#endif
start_cpu_fan();
+ cboot_late_init();
return 0;
}
*/
int dram_init_banksize(void)
{
+ int err;
+
+ /* try to compute DRAM bank size based on cboot DTB first */
+ err = cboot_dram_init_banksize();
+ if (err == 0)
+ return err;
+
+ /* fall back to default DRAM bank size computation */
+
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
*/
ulong board_get_usable_ram_top(ulong total_size)
{
+ ulong ram_top;
+
+ /* try to get top of usable RAM based on cboot DTB first */
+ ram_top = cboot_get_usable_ram_top(total_size);
+ if (ram_top > 0)
+ return ram_top;
+
+ /* fall back to default usable RAM computation */
+
return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}
#include <common.h>
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
+#if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL)
#include <asm/arch/gp_padctrl.h>
+#endif
#ifndef CONFIG_ARM64
void config_cache(void)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <linux/ctype.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/cboot.h>
+#include <asm/armv8/mmu.h>
+
+/*
+ * Size of a region that's large enough to hold the relocated U-Boot and all
+ * other allocations made around it (stack, heap, page tables, etc.)
+ * In practice, running "bdinfo" at the shell prompt, the stack reaches about
+ * 5MB from the address selected for ram_top as of the time of writing,
+ * so a 16MB region should be plenty.
+ */
+#define MIN_USABLE_RAM_SIZE SZ_16M
+/*
+ * The amount of space we expect to require for stack usage. Used to validate
+ * that all reservations fit into the region selected for the relocation target
+ */
+#define MIN_USABLE_STACK_SIZE SZ_1M
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct mm_region tegra_mem_map[];
+
+/*
+ * These variables are written to before relocation, and hence cannot be
+ * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary.
+ * The section attribute forces this into .data and avoids this issue. This
+ * also has the nice side-effect of the content being valid after relocation.
+ */
+
+/* The number of valid entries in ram_banks[] */
+static int ram_bank_count __attribute__((section(".data")));
+
+/*
+ * The usable top-of-RAM for U-Boot. This is both:
+ * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing.
+ * b) At the end of a region that has enough space to hold the relocated U-Boot
+ * and all other allocations made around it (stack, heap, page tables, etc.)
+ */
+static u64 ram_top __attribute__((section(".data")));
+/* The base address of the region of RAM that ends at ram_top */
+static u64 region_base __attribute__((section(".data")));
+
+/*
+ * Explicitly put this in the .data section because it is written before the
+ * .bss section is zeroed out but it needs to persist.
+ */
+unsigned long cboot_boot_x0 __attribute__((section(".data")));
+
+void cboot_save_boot_params(unsigned long x0, unsigned long x1,
+ unsigned long x2, unsigned long x3)
+{
+ cboot_boot_x0 = x0;
+}
+
+int cboot_dram_init(void)
+{
+ unsigned int na, ns;
+ const void *cboot_blob = (void *)cboot_boot_x0;
+ int node, len, i;
+ const u32 *prop;
+
+ if (!cboot_blob)
+ return -EINVAL;
+
+ na = fdtdec_get_uint(cboot_blob, 0, "#address-cells", 2);
+ ns = fdtdec_get_uint(cboot_blob, 0, "#size-cells", 2);
+
+ node = fdt_path_offset(cboot_blob, "/memory");
+ if (node < 0) {
+ pr_err("Can't find /memory node in cboot DTB");
+ hang();
+ }
+ prop = fdt_getprop(cboot_blob, node, "reg", &len);
+ if (!prop) {
+ pr_err("Can't find /memory/reg property in cboot DTB");
+ hang();
+ }
+
+ /* Calculate the true # of base/size pairs to read */
+ len /= 4; /* Convert bytes to number of cells */
+ len /= (na + ns); /* Convert cells to number of banks */
+ if (len > CONFIG_NR_DRAM_BANKS)
+ len = CONFIG_NR_DRAM_BANKS;
+
+ /* Parse the /memory node, and save useful entries */
+ gd->ram_size = 0;
+ ram_bank_count = 0;
+ for (i = 0; i < len; i++) {
+ u64 bank_start, bank_end, bank_size, usable_bank_size;
+
+ /* Extract raw memory region data from DTB */
+ bank_start = fdt_read_number(prop, na);
+ prop += na;
+ bank_size = fdt_read_number(prop, ns);
+ prop += ns;
+ gd->ram_size += bank_size;
+ bank_end = bank_start + bank_size;
+ debug("Bank %d: %llx..%llx (+%llx)\n", i,
+ bank_start, bank_end, bank_size);
+
+ /*
+ * Align the bank to MMU section size. This is not strictly
+ * necessary, since the translation table construction code
+ * handles page granularity without issue. However, aligning
+ * the MMU entries reduces the size and number of levels in the
+ * page table, so is worth it.
+ */
+ bank_start = ROUND(bank_start, SZ_2M);
+ bank_end = bank_end & ~(SZ_2M - 1);
+ bank_size = bank_end - bank_start;
+ debug(" aligned: %llx..%llx (+%llx)\n",
+ bank_start, bank_end, bank_size);
+ if (bank_end <= bank_start)
+ continue;
+
+ /* Record data used to create MMU translation tables */
+ ram_bank_count++;
+ /* Index below is deliberately 1-based to skip MMIO entry */
+ tegra_mem_map[ram_bank_count].virt = bank_start;
+ tegra_mem_map[ram_bank_count].phys = bank_start;
+ tegra_mem_map[ram_bank_count].size = bank_size;
+ tegra_mem_map[ram_bank_count].attrs =
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
+
+ /* Determine best bank to relocate U-Boot into */
+ if (bank_end > SZ_4G)
+ bank_end = SZ_4G;
+ debug(" end %llx (usable)\n", bank_end);
+ usable_bank_size = bank_end - bank_start;
+ debug(" size %llx (usable)\n", usable_bank_size);
+ if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) &&
+ (bank_end > ram_top)) {
+ ram_top = bank_end;
+ region_base = bank_start;
+ debug("ram top now %llx\n", ram_top);
+ }
+ }
+
+ /* Ensure memory map contains the desired sentinel entry */
+ tegra_mem_map[ram_bank_count + 1].virt = 0;
+ tegra_mem_map[ram_bank_count + 1].phys = 0;
+ tegra_mem_map[ram_bank_count + 1].size = 0;
+ tegra_mem_map[ram_bank_count + 1].attrs = 0;
+
+ /* Error out if a relocation target couldn't be found */
+ if (!ram_top) {
+ pr_err("Can't find a usable RAM top");
+ hang();
+ }
+
+ return 0;
+}
+
+int cboot_dram_init_banksize(void)
+{
+ int i;
+
+ if (ram_bank_count == 0)
+ return -EINVAL;
+
+ if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) {
+ pr_err("Reservations exceed chosen region size");
+ hang();
+ }
+
+ for (i = 0; i < ram_bank_count; i++) {
+ gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
+ gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
+ }
+
+#ifdef CONFIG_PCI
+ gd->pci_ram_top = ram_top;
+#endif
+
+ return 0;
+}
+
+ulong cboot_get_usable_ram_top(ulong total_size)
+{
+ return ram_top;
+}
+
+/*
+ * The following few functions run late during the boot process and dynamically
+ * calculate the load address of various binaries. To keep track of multiple
+ * allocations, some writable list of RAM banks must be used. tegra_mem_map[]
+ * is used for this purpose to avoid making yet another copy of the list of RAM
+ * banks. This is safe because tegra_mem_map[] is only used once during very
+ * early boot to create U-Boot's page tables, long before this code runs. If
+ * this assumption becomes invalid later, we can just fix the code to copy the
+ * list of RAM banks into some private data structure before running.
+ */
+
+static char *gen_varname(const char *var, const char *ext)
+{
+ size_t len_var = strlen(var);
+ size_t len_ext = strlen(ext);
+ size_t len = len_var + len_ext + 1;
+ char *varext = malloc(len);
+
+ if (!varext)
+ return 0;
+ strcpy(varext, var);
+ strcpy(varext + len_var, ext);
+ return varext;
+}
+
+static void mark_ram_allocated(int bank, u64 allocated_start, u64 allocated_end)
+{
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+ bool keep_front = allocated_start != bank_start;
+ bool keep_tail = allocated_end != bank_end;
+
+ if (keep_front && keep_tail) {
+ /*
+ * There are CONFIG_NR_DRAM_BANKS DRAM entries in the array,
+ * starting at index 1 (index 0 is MMIO). So, we are at DRAM
+ * entry "bank" not "bank - 1" as for a typical 0-base array.
+ * The number of remaining DRAM entries is therefore
+ * "CONFIG_NR_DRAM_BANKS - bank". We want to duplicate the
+ * current entry and shift up the remaining entries, dropping
+ * the last one. Thus, we must copy one fewer entry than the
+ * number remaining.
+ */
+ memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank],
+ CONFIG_NR_DRAM_BANKS - bank - 1);
+ tegra_mem_map[bank].size = allocated_start - bank_start;
+ bank++;
+ tegra_mem_map[bank].virt = allocated_end;
+ tegra_mem_map[bank].phys = allocated_end;
+ tegra_mem_map[bank].size = bank_end - allocated_end;
+ } else if (keep_front) {
+ tegra_mem_map[bank].size = allocated_start - bank_start;
+ } else if (keep_tail) {
+ tegra_mem_map[bank].virt = allocated_end;
+ tegra_mem_map[bank].phys = allocated_end;
+ tegra_mem_map[bank].size = bank_end - allocated_end;
+ } else {
+ /*
+ * We could move all subsequent banks down in the array but
+ * that's not necessary for subsequent allocations to work, so
+ * we skip doing so.
+ */
+ tegra_mem_map[bank].size = 0;
+ }
+}
+
+static void reserve_ram(u64 start, u64 size)
+{
+ int bank;
+ u64 end = start + size;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+
+ if (end <= bank_start || start > bank_end)
+ continue;
+ mark_ram_allocated(bank, start, end);
+ break;
+ }
+}
+
+static u64 alloc_ram(u64 size, u64 align, u64 offset)
+{
+ int bank;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+ u64 allocated = ROUND(bank_start, align) + offset;
+ u64 allocated_end = allocated + size;
+
+ if (allocated_end > bank_end)
+ continue;
+ mark_ram_allocated(bank, allocated, allocated_end);
+ return allocated;
+ }
+ return 0;
+}
+
+static void set_calculated_aliases(char *aliases, u64 address)
+{
+ char *tmp, *alias;
+ int err;
+
+ aliases = strdup(aliases);
+ if (!aliases) {
+ pr_err("strdup(aliases) failed");
+ return;
+ }
+
+ tmp = aliases;
+ while (true) {
+ alias = strsep(&tmp, " ");
+ if (!alias)
+ break;
+ debug("%s: alias: %s\n", __func__, alias);
+ err = env_set_hex(alias, address);
+ if (err)
+ pr_err("Could not set %s\n", alias);
+ }
+
+ free(aliases);
+}
+
+static void set_calculated_env_var(const char *var)
+{
+ char *var_size;
+ char *var_align;
+ char *var_offset;
+ char *var_aliases;
+ u64 size;
+ u64 align;
+ u64 offset;
+ char *aliases;
+ u64 address;
+ int err;
+
+ var_size = gen_varname(var, "_size");
+ if (!var_size)
+ return;
+ var_align = gen_varname(var, "_align");
+ if (!var_align)
+ goto out_free_var_size;
+ var_offset = gen_varname(var, "_offset");
+ if (!var_offset)
+ goto out_free_var_align;
+ var_aliases = gen_varname(var, "_aliases");
+ if (!var_aliases)
+ goto out_free_var_offset;
+
+ size = env_get_hex(var_size, 0);
+ if (!size) {
+ pr_err("%s not set or zero\n", var_size);
+ goto out_free_var_aliases;
+ }
+ align = env_get_hex(var_align, 1);
+ /* Handle extant variables, but with a value of 0 */
+ if (!align)
+ align = 1;
+ offset = env_get_hex(var_offset, 0);
+ aliases = env_get(var_aliases);
+
+ debug("%s: Calc var %s; size=%llx, align=%llx, offset=%llx\n",
+ __func__, var, size, align, offset);
+ if (aliases)
+ debug("%s: Aliases: %s\n", __func__, aliases);
+
+ address = alloc_ram(size, align, offset);
+ if (!address) {
+ pr_err("Could not allocate %s\n", var);
+ goto out_free_var_aliases;
+ }
+ debug("%s: Address %llx\n", __func__, address);
+
+ err = env_set_hex(var, address);
+ if (err)
+ pr_err("Could not set %s\n", var);
+ if (aliases)
+ set_calculated_aliases(aliases, address);
+
+out_free_var_aliases:
+ free(var_aliases);
+out_free_var_offset:
+ free(var_offset);
+out_free_var_align:
+ free(var_align);
+out_free_var_size:
+ free(var_size);
+}
+
+#ifdef DEBUG
+static void dump_ram_banks(void)
+{
+ int bank;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+
+ if (!bank_size)
+ continue;
+ printf("%d: %010llx..%010llx (+%010llx)\n", bank - 1,
+ bank_start, bank_end, bank_size);
+ }
+}
+#endif
+
+static void set_calculated_env_vars(void)
+{
+ char *vars, *tmp, *var;
+
+#ifdef DEBUG
+ printf("RAM banks before any calculated env. var.s:\n");
+ dump_ram_banks();
+#endif
+
+ reserve_ram(cboot_boot_x0, fdt_totalsize(cboot_boot_x0));
+
+#ifdef DEBUG
+ printf("RAM after reserving cboot DTB:\n");
+ dump_ram_banks();
+#endif
+
+ vars = env_get("calculated_vars");
+ if (!vars) {
+ debug("%s: No env var calculated_vars\n", __func__);
+ return;
+ }
+
+ vars = strdup(vars);
+ if (!vars) {
+ pr_err("strdup(calculated_vars) failed");
+ return;
+ }
+
+ tmp = vars;
+ while (true) {
+ var = strsep(&tmp, " ");
+ if (!var)
+ break;
+ debug("%s: var: %s\n", __func__, var);
+ set_calculated_env_var(var);
+#ifdef DEBUG
+ printf("RAM banks after allocating %s:\n", var);
+ dump_ram_banks();
+#endif
+ }
+
+ free(vars);
+}
+
+static int set_fdt_addr(void)
+{
+ int ret;
+
+ ret = env_set_hex("fdt_addr", cboot_boot_x0);
+ if (ret) {
+ printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * Attempt to use /chosen/nvidia,ether-mac in the cboot DTB to U-Boot's
+ * ethaddr environment variable if possible.
+ */
+static int cboot_get_ethaddr_legacy(const void *fdt, uint8_t mac[ETH_ALEN])
+{
+ const char *const properties[] = {
+ "nvidia,ethernet-mac",
+ "nvidia,ether-mac",
+ };
+ const char *prop;
+ unsigned int i;
+ int node, len;
+
+ node = fdt_path_offset(fdt, "/chosen");
+ if (node < 0) {
+ printf("Can't find /chosen node in cboot DTB\n");
+ return node;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(properties); i++) {
+ prop = fdt_getprop(fdt, node, properties[i], &len);
+ if (prop)
+ break;
+ }
+
+ if (!prop) {
+ printf("Can't find Ethernet MAC address in cboot DTB\n");
+ return -ENOENT;
+ }
+
+ eth_parse_enetaddr(prop, mac);
+
+ if (!is_valid_ethaddr(mac)) {
+ printf("Invalid MAC address: %s\n", prop);
+ return -EINVAL;
+ }
+
+ debug("Legacy MAC address: %pM\n", mac);
+
+ return 0;
+}
+
+int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN])
+{
+ int node, len, err = 0;
+ const uchar *prop;
+ const char *path;
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path) {
+ err = -ENOENT;
+ goto out;
+ }
+
+ debug("ethernet alias found: %s\n", path);
+
+ node = fdt_path_offset(fdt, path);
+ if (node < 0) {
+ err = -ENOENT;
+ goto out;
+ }
+
+ prop = fdt_getprop(fdt, node, "local-mac-address", &len);
+ if (!prop) {
+ err = -ENOENT;
+ goto out;
+ }
+
+ if (len != ETH_ALEN) {
+ err = -EINVAL;
+ goto out;
+ }
+
+ debug("MAC address: %pM\n", prop);
+ memcpy(mac, prop, ETH_ALEN);
+
+out:
+ if (err < 0)
+ err = cboot_get_ethaddr_legacy(fdt, mac);
+
+ return err;
+}
+
+static char *strip(const char *ptr)
+{
+ const char *end;
+
+ while (*ptr && isblank(*ptr))
+ ptr++;
+
+ /* empty string */
+ if (*ptr == '\0')
+ return strdup(ptr);
+
+ end = ptr;
+
+ while (end[1])
+ end++;
+
+ while (isblank(*end))
+ end--;
+
+ return strndup(ptr, end - ptr + 1);
+}
+
+static char *cboot_get_bootargs(const void *fdt)
+{
+ const char *args;
+ int offset, len;
+
+ offset = fdt_path_offset(fdt, "/chosen");
+ if (offset < 0)
+ return NULL;
+
+ args = fdt_getprop(fdt, offset, "bootargs", &len);
+ if (!args)
+ return NULL;
+
+ return strip(args);
+}
+
+int cboot_late_init(void)
+{
+ const void *fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN];
+ char *bootargs;
+ int err;
+
+ set_calculated_env_vars();
+ /*
+ * Ignore errors here; the value may not be used depending on
+ * extlinux.conf or boot script content.
+ */
+ set_fdt_addr();
+
+ /* Ignore errors here; not all cases care about Ethernet addresses */
+ err = cboot_get_ethaddr(fdt, mac);
+ if (!err) {
+ void *blob = (void *)gd->fdt_blob;
+
+ err = fdtdec_set_ethernet_mac_address(blob, mac, sizeof(mac));
+ if (err < 0)
+ printf("failed to set MAC address %pM: %d\n", mac, err);
+ }
+
+ bootargs = cboot_get_bootargs(fdt);
+ if (bootargs) {
+ env_set("cbootargs", bootargs);
+ free(bootargs);
+ }
+
+ return 0;
+}
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
*/
/* Tegra SoC common clock control functions */
int clock_external_output(int clk_id)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 val;
if (clk_id >= 1 && clk_id <= 3) {
- setbits_le32(&pmc->pmc_clk_out_cntrl,
- 1 << (2 + (clk_id - 1) * 8));
+ val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
+ pmc_clk_out_cntrl));
+ val |= 1 << (2 + (clk_id - 1) * 8);
+ tegra_pmc_writel(val,
+ offsetof(struct pmc_ctlr,
+ pmc_clk_out_cntrl));
+
} else {
printf("%s: Unknown output clock id %d\n", __func__, clk_id);
return -EINVAL;
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code (arch/arm/lib/reset.c) that is:
*
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
puts("Entering RCM...\n");
udelay(50000);
- pmc->pmc_scratch0 = 2;
+ tegra_pmc_writel(2, PMC_SCRATCH0);
disable_interrupts();
reset_cpu(0);
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
*/
#include <common.h>
static int is_cpu_powered(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
+ return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
+ pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
}
static void remove_cpu_io_clamps(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
debug("%s entry\n", __func__);
/* Remove the clamps on the CPU I/O signals */
- reg = readl(&pmc->pmc_remove_clamping);
+ reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
+ tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
/* Give I/O signals time to stabilize */
udelay(IO_STABILIZATION_DELAY);
void powerup_cpu(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
debug("%s entry\n", __func__);
if (!is_cpu_powered()) {
/* Toggle the CPU power state (OFF -> ON) */
- reg = readl(&pmc->pmc_pwrgate_toggle);
+ reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
+ pmc_pwrgate_toggle));
reg &= PARTID_CP;
reg |= START_CP;
- writel(reg, &pmc->pmc_pwrgate_toggle);
+ tegra_pmc_writel(reg,
+ offsetof(struct pmc_ctlr,
+ pmc_pwrgate_toggle));
/* Wait for the power to come up */
while (!is_cpu_powered()) {
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
-#include <asm/arch/pmu.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmu.h>
#include <asm/arch-tegra/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * SoC-specific setup info
- *
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-#ifdef CONFIG_ARM64
- .align 5
-ENTRY(reset_cpu)
- /* get address for global reset register */
- ldr x1, =PRM_RSTCTRL
- ldr w3, [x1]
- /* force reset */
- orr w3, w3, #0x10
- str w3, [x1]
- mov w0, w0
-1:
- b 1b
-ENDPROC(reset_cpu)
-#else
- .align 5
-ENTRY(reset_cpu)
- ldr r1, rstctl @ get addr for global reset
- @ reg
- ldr r3, [r1]
- orr r3, r3, #0x10
- str r3, [r1] @ force reset
- mov r0, r0
-_loop_forever:
- b _loop_forever
-rstctl:
- .word PRM_RSTCTRL
-ENDPROC(reset_cpu)
-#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <common.h>
+
+#include <linux/arm-smccc.h>
+
+#include <asm/io.h>
+#include <asm/arch-tegra/pmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
+static bool tegra_pmc_detect_tz_only(void)
+{
+ static bool initialized = false;
+ static bool is_tz_only = false;
+ u32 value, saved;
+
+ if (!initialized) {
+ saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
+ value = saved ^ 0xffffffff;
+
+ if (value == 0xffffffff)
+ value = 0xdeadbeef;
+
+ /* write pattern and read it back */
+ writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
+ value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
+
+ /* if we read all-zeroes, access is restricted to TZ only */
+ if (value == 0) {
+ debug("access to PMC is restricted to TZ\n");
+ is_tz_only = true;
+ } else {
+ /* restore original value */
+ writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
+ }
+
+ initialized = true;
+ }
+
+ return is_tz_only;
+}
+#endif
+
+uint32_t tegra_pmc_readl(unsigned long offset)
+{
+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
+ if (tegra_pmc_detect_tz_only()) {
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
+ 0, 0, 0, &res);
+ if (res.a0)
+ printf("%s(): SMC failed: %lu\n", __func__, res.a0);
+
+ return res.a1;
+ }
+#endif
+
+ return readl(NV_PA_PMC_BASE + offset);
+}
+
+void tegra_pmc_writel(u32 value, unsigned long offset)
+{
+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
+ if (tegra_pmc_detect_tz_only()) {
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
+ value, 0, 0, 0, 0, &res);
+ if (res.a0)
+ printf("%s(): SMC failed: %lu\n", __func__, res.a0);
+
+ return;
+ }
+#endif
+
+ writel(value, NV_PA_PMC_BASE + offset);
+}
+
+void reset_cpu(ulong addr)
+{
+ u32 value;
+
+ value = tegra_pmc_readl(PMC_CNTRL);
+ value |= PMC_CNTRL_MAIN_RST;
+ tegra_pmc_writel(value, PMC_CNTRL);
+}
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*/
#include <common.h>
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
#define PWRGATE_TOGGLE 0x30
#define PWRGATE_TOGGLE_START (1 << 8)
u32 value, mask = state ? (1 << id) : 0, old_mask;
unsigned long start, timeout = 25;
- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ value = tegra_pmc_readl(PWRGATE_STATUS);
old_mask = value & (1 << id);
if (mask == old_mask)
return 0;
- writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
+ tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
start = get_timer(0);
while (get_timer(start) < timeout) {
- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ value = tegra_pmc_readl(PWRGATE_STATUS);
if ((value & (1 << id)) == mask)
return 0;
}
else
value = 1 << id;
- writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
+ tegra_pmc_writel(value, REMOVE_CLAMPING);
return 0;
}
#
# SPDX-License-Identifier: GPL-2.0
-obj-y += ../board186.o
obj-y += cache.o
-obj-y += nvtboot_board.o
-obj-y += nvtboot_ll.o
-obj-y += nvtboot_mem.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.
- */
-
-#include <stdlib.h>
-#include <common.h>
-#include <fdt_support.h>
-#include <fdtdec.h>
-#include <asm/arch/tegra.h>
-#include <asm/armv8/mmu.h>
-
-extern unsigned long nvtboot_boot_x0;
-
-/*
- * The following few functions run late during the boot process and dynamically
- * calculate the load address of various binaries. To keep track of multiple
- * allocations, some writable list of RAM banks must be used. tegra_mem_map[]
- * is used for this purpose to avoid making yet another copy of the list of RAM
- * banks. This is safe because tegra_mem_map[] is only used once during very
- * early boot to create U-Boot's page tables, long before this code runs. If
- * this assumption becomes invalid later, we can just fix the code to copy the
- * list of RAM banks into some private data structure before running.
- */
-
-extern struct mm_region tegra_mem_map[];
-
-static char *gen_varname(const char *var, const char *ext)
-{
- size_t len_var = strlen(var);
- size_t len_ext = strlen(ext);
- size_t len = len_var + len_ext + 1;
- char *varext = malloc(len);
-
- if (!varext)
- return 0;
- strcpy(varext, var);
- strcpy(varext + len_var, ext);
- return varext;
-}
-
-static void mark_ram_allocated(int bank, u64 allocated_start, u64 allocated_end)
-{
- u64 bank_start = tegra_mem_map[bank].virt;
- u64 bank_size = tegra_mem_map[bank].size;
- u64 bank_end = bank_start + bank_size;
- bool keep_front = allocated_start != bank_start;
- bool keep_tail = allocated_end != bank_end;
-
- if (keep_front && keep_tail) {
- /*
- * There are CONFIG_NR_DRAM_BANKS DRAM entries in the array,
- * starting at index 1 (index 0 is MMIO). So, we are at DRAM
- * entry "bank" not "bank - 1" as for a typical 0-base array.
- * The number of remaining DRAM entries is therefore
- * "CONFIG_NR_DRAM_BANKS - bank". We want to duplicate the
- * current entry and shift up the remaining entries, dropping
- * the last one. Thus, we must copy one fewer entry than the
- * number remaining.
- */
- memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank],
- CONFIG_NR_DRAM_BANKS - bank - 1);
- tegra_mem_map[bank].size = allocated_start - bank_start;
- bank++;
- tegra_mem_map[bank].virt = allocated_end;
- tegra_mem_map[bank].phys = allocated_end;
- tegra_mem_map[bank].size = bank_end - allocated_end;
- } else if (keep_front) {
- tegra_mem_map[bank].size = allocated_start - bank_start;
- } else if (keep_tail) {
- tegra_mem_map[bank].virt = allocated_end;
- tegra_mem_map[bank].phys = allocated_end;
- tegra_mem_map[bank].size = bank_end - allocated_end;
- } else {
- /*
- * We could move all subsequent banks down in the array but
- * that's not necessary for subsequent allocations to work, so
- * we skip doing so.
- */
- tegra_mem_map[bank].size = 0;
- }
-}
-
-static void reserve_ram(u64 start, u64 size)
-{
- int bank;
- u64 end = start + size;
-
- for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
- u64 bank_start = tegra_mem_map[bank].virt;
- u64 bank_size = tegra_mem_map[bank].size;
- u64 bank_end = bank_start + bank_size;
-
- if (end <= bank_start || start > bank_end)
- continue;
- mark_ram_allocated(bank, start, end);
- break;
- }
-}
-
-static u64 alloc_ram(u64 size, u64 align, u64 offset)
-{
- int bank;
-
- for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
- u64 bank_start = tegra_mem_map[bank].virt;
- u64 bank_size = tegra_mem_map[bank].size;
- u64 bank_end = bank_start + bank_size;
- u64 allocated = ROUND(bank_start, align) + offset;
- u64 allocated_end = allocated + size;
-
- if (allocated_end > bank_end)
- continue;
- mark_ram_allocated(bank, allocated, allocated_end);
- return allocated;
- }
- return 0;
-}
-
-static void set_calculated_aliases(char *aliases, u64 address)
-{
- char *tmp, *alias;
- int err;
-
- aliases = strdup(aliases);
- if (!aliases) {
- pr_err("strdup(aliases) failed");
- return;
- }
-
- tmp = aliases;
- while (true) {
- alias = strsep(&tmp, " ");
- if (!alias)
- break;
- debug("%s: alias: %s\n", __func__, alias);
- err = env_set_hex(alias, address);
- if (err)
- pr_err("Could not set %s\n", alias);
- }
-
- free(aliases);
-}
-
-static void set_calculated_env_var(const char *var)
-{
- char *var_size;
- char *var_align;
- char *var_offset;
- char *var_aliases;
- u64 size;
- u64 align;
- u64 offset;
- char *aliases;
- u64 address;
- int err;
-
- var_size = gen_varname(var, "_size");
- if (!var_size)
- return;
- var_align = gen_varname(var, "_align");
- if (!var_align)
- goto out_free_var_size;
- var_offset = gen_varname(var, "_offset");
- if (!var_offset)
- goto out_free_var_align;
- var_aliases = gen_varname(var, "_aliases");
- if (!var_aliases)
- goto out_free_var_offset;
-
- size = env_get_hex(var_size, 0);
- if (!size) {
- pr_err("%s not set or zero\n", var_size);
- goto out_free_var_aliases;
- }
- align = env_get_hex(var_align, 1);
- /* Handle extant variables, but with a value of 0 */
- if (!align)
- align = 1;
- offset = env_get_hex(var_offset, 0);
- aliases = env_get(var_aliases);
-
- debug("%s: Calc var %s; size=%llx, align=%llx, offset=%llx\n",
- __func__, var, size, align, offset);
- if (aliases)
- debug("%s: Aliases: %s\n", __func__, aliases);
-
- address = alloc_ram(size, align, offset);
- if (!address) {
- pr_err("Could not allocate %s\n", var);
- goto out_free_var_aliases;
- }
- debug("%s: Address %llx\n", __func__, address);
-
- err = env_set_hex(var, address);
- if (err)
- pr_err("Could not set %s\n", var);
- if (aliases)
- set_calculated_aliases(aliases, address);
-
-out_free_var_aliases:
- free(var_aliases);
-out_free_var_offset:
- free(var_offset);
-out_free_var_align:
- free(var_align);
-out_free_var_size:
- free(var_size);
-}
-
-#ifdef DEBUG
-static void dump_ram_banks(void)
-{
- int bank;
-
- for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
- u64 bank_start = tegra_mem_map[bank].virt;
- u64 bank_size = tegra_mem_map[bank].size;
- u64 bank_end = bank_start + bank_size;
-
- if (!bank_size)
- continue;
- printf("%d: %010llx..%010llx (+%010llx)\n", bank - 1,
- bank_start, bank_end, bank_size);
- }
-}
-#endif
-
-static void set_calculated_env_vars(void)
-{
- char *vars, *tmp, *var;
-
-#ifdef DEBUG
- printf("RAM banks before any calculated env. var.s:\n");
- dump_ram_banks();
-#endif
-
- reserve_ram(nvtboot_boot_x0, fdt_totalsize(nvtboot_boot_x0));
-
-#ifdef DEBUG
- printf("RAM after reserving cboot DTB:\n");
- dump_ram_banks();
-#endif
-
- vars = env_get("calculated_vars");
- if (!vars) {
- debug("%s: No env var calculated_vars\n", __func__);
- return;
- }
-
- vars = strdup(vars);
- if (!vars) {
- pr_err("strdup(calculated_vars) failed");
- return;
- }
-
- tmp = vars;
- while (true) {
- var = strsep(&tmp, " ");
- if (!var)
- break;
- debug("%s: var: %s\n", __func__, var);
- set_calculated_env_var(var);
-#ifdef DEBUG
- printf("RAM banks affter allocating %s:\n", var);
- dump_ram_banks();
-#endif
- }
-
- free(vars);
-}
-
-static int set_fdt_addr(void)
-{
- int ret;
-
- ret = env_set_hex("fdt_addr", nvtboot_boot_x0);
- if (ret) {
- printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-/*
- * Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's
- * ethaddr environment variable if possible.
- */
-static int set_ethaddr_from_nvtboot(void)
-{
- const void *nvtboot_blob = (void *)nvtboot_boot_x0;
- int ret, node, len;
- const u32 *prop;
-
- /* Already a valid address in the environment? If so, keep it */
- if (env_get("ethaddr"))
- return 0;
-
- node = fdt_path_offset(nvtboot_blob, "/chosen");
- if (node < 0) {
- printf("Can't find /chosen node in nvtboot DTB\n");
- return node;
- }
- prop = fdt_getprop(nvtboot_blob, node, "nvidia,ether-mac", &len);
- if (!prop) {
- printf("Can't find nvidia,ether-mac property in nvtboot DTB\n");
- return -ENOENT;
- }
-
- ret = env_set("ethaddr", (void *)prop);
- if (ret) {
- printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-int tegra_soc_board_init_late(void)
-{
- set_calculated_env_vars();
- /*
- * Ignore errors here; the value may not be used depending on
- * extlinux.conf or boot script content.
- */
- set_fdt_addr();
- /* Ignore errors here; not all cases care about Ethernet addresses */
- set_ethaddr_from_nvtboot();
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Save nvtboot-related boot-time CPU state
- *
- * (C) Copyright 2015-2016 NVIDIA Corporation <www.nvidia.com>
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-.align 8
-.globl nvtboot_boot_x0
-nvtboot_boot_x0:
- .dword 0
-
-ENTRY(save_boot_params)
- adr x8, nvtboot_boot_x0
- str x0, [x8]
- b save_boot_params_ret
-ENDPROC(save_boot_params)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <fdtdec.h>
-#include <linux/sizes.h>
-#include <asm/arch/tegra.h>
-#include <asm/armv8/mmu.h>
-
-/*
- * Size of a region that's large enough to hold the relocated U-Boot and all
- * other allocations made around it (stack, heap, page tables, etc.)
- * In practice, running "bdinfo" at the shell prompt, the stack reaches about
- * 5MB from the address selected for ram_top as of the time of writing,
- * so a 16MB region should be plenty.
- */
-#define MIN_USABLE_RAM_SIZE SZ_16M
-/*
- * The amount of space we expect to require for stack usage. Used to validate
- * that all reservations fit into the region selected for the relocation target
- */
-#define MIN_USABLE_STACK_SIZE SZ_1M
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern unsigned long nvtboot_boot_x0;
-extern struct mm_region tegra_mem_map[];
-
-/*
- * These variables are written to before relocation, and hence cannot be
- * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary.
- * The section attribute forces this into .data and avoids this issue. This
- * also has the nice side-effect of the content being valid after relocation.
- */
-
-/* The number of valid entries in ram_banks[] */
-static int ram_bank_count __attribute__((section(".data")));
-
-/*
- * The usable top-of-RAM for U-Boot. This is both:
- * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing.
- * b) At the end of a region that has enough space to hold the relocated U-Boot
- * and all other allocations made around it (stack, heap, page tables, etc.)
- */
-static u64 ram_top __attribute__((section(".data")));
-/* The base address of the region of RAM that ends at ram_top */
-static u64 region_base __attribute__((section(".data")));
-
-int dram_init(void)
-{
- unsigned int na, ns;
- const void *nvtboot_blob = (void *)nvtboot_boot_x0;
- int node, len, i;
- const u32 *prop;
-
- na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
- ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
-
- node = fdt_path_offset(nvtboot_blob, "/memory");
- if (node < 0) {
- pr_err("Can't find /memory node in nvtboot DTB");
- hang();
- }
- prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
- if (!prop) {
- pr_err("Can't find /memory/reg property in nvtboot DTB");
- hang();
- }
-
- /* Calculate the true # of base/size pairs to read */
- len /= 4; /* Convert bytes to number of cells */
- len /= (na + ns); /* Convert cells to number of banks */
- if (len > CONFIG_NR_DRAM_BANKS)
- len = CONFIG_NR_DRAM_BANKS;
-
- /* Parse the /memory node, and save useful entries */
- gd->ram_size = 0;
- ram_bank_count = 0;
- for (i = 0; i < len; i++) {
- u64 bank_start, bank_end, bank_size, usable_bank_size;
-
- /* Extract raw memory region data from DTB */
- bank_start = fdt_read_number(prop, na);
- prop += na;
- bank_size = fdt_read_number(prop, ns);
- prop += ns;
- gd->ram_size += bank_size;
- bank_end = bank_start + bank_size;
- debug("Bank %d: %llx..%llx (+%llx)\n", i,
- bank_start, bank_end, bank_size);
-
- /*
- * Align the bank to MMU section size. This is not strictly
- * necessary, since the translation table construction code
- * handles page granularity without issue. However, aligning
- * the MMU entries reduces the size and number of levels in the
- * page table, so is worth it.
- */
- bank_start = ROUND(bank_start, SZ_2M);
- bank_end = bank_end & ~(SZ_2M - 1);
- bank_size = bank_end - bank_start;
- debug(" aligned: %llx..%llx (+%llx)\n",
- bank_start, bank_end, bank_size);
- if (bank_end <= bank_start)
- continue;
-
- /* Record data used to create MMU translation tables */
- ram_bank_count++;
- /* Index below is deliberately 1-based to skip MMIO entry */
- tegra_mem_map[ram_bank_count].virt = bank_start;
- tegra_mem_map[ram_bank_count].phys = bank_start;
- tegra_mem_map[ram_bank_count].size = bank_size;
- tegra_mem_map[ram_bank_count].attrs =
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
-
- /* Determine best bank to relocate U-Boot into */
- if (bank_end > SZ_4G)
- bank_end = SZ_4G;
- debug(" end %llx (usable)\n", bank_end);
- usable_bank_size = bank_end - bank_start;
- debug(" size %llx (usable)\n", usable_bank_size);
- if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) &&
- (bank_end > ram_top)) {
- ram_top = bank_end;
- region_base = bank_start;
- debug("ram top now %llx\n", ram_top);
- }
- }
-
- /* Ensure memory map contains the desired sentinel entry */
- tegra_mem_map[ram_bank_count + 1].virt = 0;
- tegra_mem_map[ram_bank_count + 1].phys = 0;
- tegra_mem_map[ram_bank_count + 1].size = 0;
- tegra_mem_map[ram_bank_count + 1].attrs = 0;
-
- /* Error out if a relocation target couldn't be found */
- if (!ram_top) {
- pr_err("Can't find a usable RAM top");
- hang();
- }
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- int i;
-
- if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) {
- pr_err("Reservations exceed chosen region size");
- hang();
- }
-
- for (i = 0; i < ram_bank_count; i++) {
- gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
- gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
- }
-
-#ifdef CONFIG_PCI
- gd->pci_ram_top = ram_top;
-#endif
-
- return 0;
-}
-
-ulong board_get_usable_ram_top(ulong total_size)
-{
- return ram_top;
-}
CLOCK_TYPE_PDCT,
CLOCK_TYPE_ACPT,
CLOCK_TYPE_ASPTE,
- CLOCK_TYPE_PMDACD2T,
+ CLOCK_TYPE_PDD2T,
CLOCK_TYPE_PCST,
CLOCK_TYPE_DP,
{ CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
MASK_BITS_31_29},
- { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
- CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
+ { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE),
+ CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
MASK_BITS_31_29},
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T),
+ TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T),
/* 0x10 */
TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
- { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
config TARGET_AX25_AE350
bool "Support ax25-ae350"
+config TARGET_MICROCHIP_ICICLE
+ bool "Support Microchip PolarFire-SoC Icicle Board"
+
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
+source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/fu540/Kconfig"
# platform-specific options below
return -1;
}
+ resetc.is_psoc = 1;
rc = dm_i2c_probe(i2cbus,
RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev);
if (rc) {
/* SPL */
#ifdef CONFIG_SPL_BUILD
+/* must set PB25 low to enable the CAN transceivers */
+static void board_can_stdby_dis(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0);
+}
+
+static void board_leds_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */
+}
+
+/* deassert reset lines for external periph in case of warm reboot */
+static void board_reset_additional_periph(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */
+}
+
+static void board_start_additional_periph(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */
+}
+
#ifdef CONFIG_SD_BOOT
void spl_mmc_init(void)
{
#ifdef CONFIG_SD_BOOT
spl_mmc_init();
#endif
+ board_reset_additional_periph();
+ board_can_stdby_dis();
+ board_leds_init();
}
void spl_display_print(void)
{
}
+void spl_board_prepare_for_boot(void)
+{
+ board_start_additional_periph();
+}
+
static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
{
ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
return -1;
}
- ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET) + 1, 7, addr);
+ ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
if (ret) {
printf("Error - unable to read MAC address from SPI flash.\n");
return -1;
return 0;
}
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
#ifdef CONFIG_MMC_DAVINCI
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
imply OF_BOARD_SETUP
imply SIFIVE_SERIAL
imply SMP
+ imply PCI
+ imply DM_PCI
+ imply PCIE_ECAM_GENERIC
+ imply CMD_PCI
+ imply E1000
+ imply NVME
endif
KM83XX BOARD
-M: Holger Brunck <holger.brunck@keymile.com>
+M: Holger Brunck <holger.brunck@ch.abb.com>
S: Maintained
F: board/keymile/km83xx/
F: include/configs/km8360.h
KM_ARM BOARD
-M: Valentin Longchamp <valentin.longchamp@keymile.com>
+M: Valentin Longchamp <valentin.longchamp@ch.abb.com>
S: Maintained
F: board/keymile/km_arm/
F: include/configs/km_kirkwood.h
KMP204X BOARD
-M: Valentin Longchamp <valentin.longchamp@keymile.com>
+M: Valentin Longchamp <valentin.longchamp@ch.abb.com>
S: Maintained
F: board/keymile/kmp204x/
F: include/configs/kmp204x.h
--- /dev/null
+if TARGET_MICROCHIP_ICICLE
+
+config SYS_BOARD
+ default "mpfs_icicle"
+
+config SYS_VENDOR
+ default "microchip"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "microchip_mpfs_icicle"
+
+config SYS_TEXT_BASE
+ default 0x80000000 if !RISCV_SMODE
+ default 0x80200000 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select GENERIC_RISCV
+ select BOARD_EARLY_INIT_F
+ imply SMP
+ imply SYS_NS16550
+
+endif
--- /dev/null
+Microchip MPFS icicle
+M: Padmarao Begari <padmarao.begari@microchip.com>
+M: Cyril Jean <cyril.jean@microchip.com>
+S: Maintained
+F: board/microchip/mpfs_icicle/
+F: include/configs/microchip_mpfs_icicle.h
+F: configs/microchip_mpfs_icicle_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Microchip Technology Inc.
+# Padmarao Begari <padmarao.begari@microchip.com>
+#
+
+obj-y += mpfs_icicle.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+
+int board_init(void)
+{
+ /* For now nothing to do here. */
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ unsigned int val;
+
+ /* Reset uart peripheral */
+ val = readl(MPFS_SYSREG_SOFT_RESET);
+ val = (val & ~(1u << 5u));
+ writel(val, MPFS_SYSREG_SOFT_RESET);
+
+ return 0;
+}
*/
#include <common.h>
+#include <environment.h>
+#include <fdtdec.h>
#include <i2c.h>
+#include <linux/libfdt.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/cboot.h>
#include "../p2571/max77620_init.h"
#include "pinmux-config-p2371-2180.h"
return 0;
}
#endif /* PCI */
+
+static void ft_mac_address_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ printf("ethernet alias points to absent node %s\n", path);
+ return;
+ }
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+ struct fdt_memory fb;
+ int err;
+
+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to get carveout for %s: %d\n", node,
+ err);
+
+ return err;
+ }
+
+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+ &fb);
+ if (err < 0) {
+ printf("failed to set carveout for %s: %d\n", node, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ static const char * const nodes[] = {
+ "/host1x@50000000/dc@54200000",
+ "/host1x@50000000/dc@54240000",
+ };
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to copy carveout for %s: %d\n",
+ nodes[i], err);
+ continue;
+ }
+ }
+}
+
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ ft_mac_address_setup(fdt);
+ ft_carveout_setup(fdt);
+
+ return 0;
+}
*/
#include <common.h>
+#include <environment.h>
+#include <fdtdec.h>
#include <i2c.h>
+#include <linux/libfdt.h>
+#include <asm/arch-tegra/cboot.h>
#include "../p2571/max77620_init.h"
-int tegra_board_init(void)
+void pin_mux_mmc(void)
{
struct udevice *dev;
uchar val;
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
if (ret) {
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
- return ret;
+ return;
}
/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
val = 0xF2;
ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1);
if (ret) {
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
- return ret;
+ return;
}
-
- return 0;
}
+#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
struct udevice *dev;
return 0;
}
+#endif
+
+static void ft_mac_address_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ printf("ethernet alias points to absent node %s\n", path);
+ return;
+ }
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+ struct fdt_memory fb;
+ int err;
+
+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to get carveout for %s: %d\n", node,
+ err);
+
+ return err;
+ }
+
+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+ &fb);
+ if (err < 0) {
+ printf("failed to set carveout for %s: %d\n", node, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ static const char * const nodes[] = {
+ "/host1x@13e00000/display-hub@15200000/display@15200000",
+ "/host1x@13e00000/display-hub@15200000/display@15210000",
+ "/host1x@13e00000/display-hub@15200000/display@15220000",
+ };
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+ printf("copying carveout for %s...\n", nodes[i]);
+
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to copy carveout for %s: %d\n",
+ nodes[i], err);
+
+ continue;
+ }
+ }
+}
+
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ ft_mac_address_setup(fdt);
+ ft_carveout_setup(fdt);
+
+ return 0;
+}
};
static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
}
ret = EFI_CALL(RT->set_variable(var_name16, &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, data));
guid = efi_global_variable_guid;
size = sizeof(u16);
ret = EFI_CALL(RT->set_variable(L"BootNext", &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, &bootnext));
guid = efi_global_variable_guid;
ret = EFI_CALL(RT->set_variable(L"BootOrder", &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, bootorder));
if (argc < 2)
return CMD_RET_USAGE;
led_label = argv[1];
- if (*led_label == 'l')
+ if (strncmp(led_label, "list", 4) == 0)
return list_leds();
cmd = argc > 2 ? get_led_cmd(argv[2]) : LEDST_COUNT;
led, 4, 1, do_led,
"manage LEDs",
"<led_label> on|off|toggle" BLINK "\tChange LED state\n"
- "led [<led_label>\tGet LED state\n"
+ "led [<led_label>]\tGet LED state\n"
"led list\t\tshow a list of LEDs"
);
setenv, CONFIG_SYS_MAXARGS, 0, do_env_set,
"set environment variables",
#if defined(CONFIG_CMD_NVEDIT_EFI)
- "-e name [value ...]\n"
+ "-e [-nv] name [value ...]\n"
" - set UEFI variable 'name' to 'value' ...'\n"
+ " 'nv' option makes the variable non-volatile\n"
" - delete UEFI variable 'name' if 'value' not specified\n"
#endif
"setenv [-f] name value ...\n"
u16 *var_name16 = NULL, *p;
size_t len;
efi_guid_t guid;
+ u32 attributes;
efi_status_t ret;
if (argc == 1)
return CMD_RET_FAILURE;
}
+ attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS;
+ if (!strcmp(argv[1], "-nv")) {
+ attributes |= EFI_VARIABLE_NON_VOLATILE;
+ argc--;
+ argv++;
+ if (argc == 1)
+ return CMD_RET_SUCCESS;
+ }
+
var_name = argv[1];
if (argc == 2) {
/* delete */
utf8_utf16_strncpy(&p, var_name, len + 1);
guid = efi_global_variable_guid;
- ret = EFI_CALL(efi_set_variable(var_name16, &guid,
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
+ ret = EFI_CALL(efi_set_variable(var_name16, &guid, attributes,
size, value));
if (ret == EFI_SUCCESS) {
ret = CMD_RET_SUCCESS;
supports MMC, NAND and YMODEM and other methods loading of U-Boot
and the Linux Kernel. If unsure, say Y.
+config SPL_SIZE_LIMIT
+ int "Maximum size of SPL image"
+ depends on SPL
+ default 0
+ help
+ Specifies the maximum length of the U-Boot SPL image.
+ If this value is zero, it is ignored.
+
+config SPL_SIZE_LIMIT_SUBTRACT_GD
+ bool "SPL image size check: provide space for global data"
+ depends on SPL_SIZE_LIMIT > 0
+ help
+ If enabled, aligned size of global data is reserved in
+ SPL_SIZE_LIMIT check to ensure such an image does not overflow SRAM
+ if SPL_SIZE_LIMIT describes the size of SRAM available for SPL when
+ pre-reloc global data is put into this SRAM, too.
+
+config SPL_SIZE_LIMIT_SUBTRACT_MALLOC
+ bool "SPL image size check: provide space for malloc() pool before relocation"
+ depends on SPL_SIZE_LIMIT > 0
+ help
+ If enabled, SPL_SYS_MALLOC_F_LEN is reserved in SPL_SIZE_LIMIT check
+ to ensure such an image does not overflow SRAM if SPL_SIZE_LIMIT
+ describes the size of SRAM available for SPL when pre-reloc malloc
+ pool is put into this SRAM, too.
+
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+ hex "SPL image size check: provide stack space before relocation"
+ depends on SPL_SIZE_LIMIT > 0
+ default 0
+ help
+ If set, this size is reserved in SPL_SIZE_LIMIT check to ensure such
+ an image does not overflow SRAM if SPL_SIZE_LIMIT describes the size
+ of SRAM available for SPL when the stack required before reolcation
+ uses this SRAM, too.
+
config HANDOFF
bool "Pass hand-off information from SPL to U-Boot proper"
depends on BLOBLIST
endif # TPL
+config SPL_AT91_MCK_BYPASS
+ bool "Use external clock signal as a source of main clock for AT91 platforms"
+ depends on ARCH_AT91
+ default n
+ help
+ Use external 8 to 24 Mhz clock signal as source of main clock instead
+ of an external crystal oscillator.
+ This option disables the internal driving on the XOUT pin.
+ The external source has to provide a stable clock on the XIN pin.
+ If this option is disabled, the SoC expects a crystal oscillator
+ that needs driving on both XIN and XOUT lines.
+
endif # SPL
endmenu
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SPI_LOAD=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_ARM=y
CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA210=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_ARCH_RV64I=y
+CONFIG_NR_CPUS=5
+CONFIG_TARGET_MICROCHIP_ICICLE=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_FIT=y
+CONFIG_OF_PRIOR_STAGE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA210=y
CONFIG_TARGET_P2371_0000=y
CONFIG_ARM=y
CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA210=y
CONFIG_TARGET_P2371_2180=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
CONFIG_ARM=y
CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA210=y
CONFIG_TARGET_P2571=y
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
-CONFIG_NR_DRAM_BANKS=8
+CONFIG_NR_DRAM_BANKS=1026
CONFIG_TEGRA186=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # "
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
-CONFIG_NR_DRAM_BANKS=8
+CONFIG_NR_DRAM_BANKS=1026
CONFIG_TEGRA186=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER_HII is not set
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=8
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
+CONFIG_SPL_SIZE_LIMIT=30720
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_TINKER_RK3288=y
CONFIG_NR_DRAM_BANKS=1
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Memory Info
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+/*
+ * Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * max number of command args
+ */
+#define CONFIG_SYS_MAXARGS 16
+
+/*
+ * Boot Argument Buffer Size
+ */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
+ */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+
+/* Init Stack Pointer */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000)
+
+#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* SDRAM */
+
+/*
+ * memtest works on DRAM
+ */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
+
+/* When we use RAM as ENV */
+#define CONFIG_ENV_SIZE 0x2000
+
+#endif /* __CONFIG_H */
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
/* Environment options */
-#define CONFIG_ENV_SIZE SZ_4K
+#define CONFIG_ENV_SIZE SZ_128K
#define BOOT_TARGET_DEVICES(func) \
func(QEMU, qemu, na) \
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
#ifndef CONFIG_SPL_BUILD
+#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
+#endif
#include <config_distro_bootcmd.h>
#else
#define BOOTENV
*/
int fdtdec_setup_memory_banksize(void);
+/**
+ * fdtdec_set_ethernet_mac_address() - set MAC address for default interface
+ *
+ * Looks up the default interface via the "ethernet" alias (in the /aliases
+ * node) and stores the given MAC in its "local-mac-address" property. This
+ * is useful on platforms that store the MAC address in a custom location.
+ * Board code can call this in the late init stage to make sure that the
+ * interface device tree node has the right MAC address configured for the
+ * Ethernet uclass to pick it up.
+ *
+ * Typically the FDT passed into this function will be U-Boot's control DTB.
+ * Given that a lot of code may be holding offsets to various nodes in that
+ * tree, this code will only set the "local-mac-address" property in-place,
+ * which means that it needs to exist and have space for the 6-byte address.
+ * This ensures that the operation is non-destructive and does not invalidate
+ * offsets that other drivers may be using.
+ *
+ * @param fdt FDT blob
+ * @param mac buffer containing the MAC address to set
+ * @param size size of MAC address
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size);
+
/**
* fdtdec_set_phandle() - sets the phandle of a given node
*
#ifndef __HAVE_ARCH_STRDUP
extern char * strdup(const char *);
#endif
+extern char * strndup(const char *, size_t);
#ifndef __HAVE_ARCH_STRSWAB
extern char * strswab(const char *);
#endif
#define _TIME_H
#include <linux/typecheck.h>
+#include <linux/types.h>
unsigned long get_timer(unsigned long base);
*/
void timer_test_add_offset(unsigned long offset);
+/**
+ * usec_to_tick() - convert microseconds to clock ticks
+ *
+ * @usec: duration in microseconds
+ * Return: duration in clock ticks
+ */
+uint64_t usec_to_tick(unsigned long usec);
+
/*
* These inlines deal with timer wrapping correctly. You are
* strongly encouraged to use them
#ifndef __UUID_H__
#define __UUID_H__
+#include <linux/bitops.h>
+
/* This is structure is in big-endian */
struct uuid {
unsigned int time_low;
unsigned char node[6];
} __packed;
-enum {
- UUID_STR_FORMAT_STD,
- UUID_STR_FORMAT_GUID
-};
+/* Bits of a bitmask specifying the output format for GUIDs */
+#define UUID_STR_FORMAT_STD 0
+#define UUID_STR_FORMAT_GUID BIT(0)
+#define UUID_STR_UPPER_CASE BIT(1)
#define UUID_STR_LEN 36
#define UUID_BIN_LEN sizeof(struct uuid)
ret = EFI_CALL(efi_set_variable(
L"BootNext",
(efi_guid_t *)&efi_global_variable_guid,
- 0, 0, &bootnext));
+ EFI_VARIABLE_NON_VOLATILE, 0,
+ &bootnext));
/* load BootNext */
if (ret == EFI_SUCCESS) {
++count;
}
}
+ *number_of_drivers = 0;
+ if (!count) {
+ *driver_handle_buffer = NULL;
+ return EFI_SUCCESS;
+ }
/*
* Create buffer. In case of duplicate driver assignments the buffer
* will be too large. But that does not harm.
*/
- *number_of_drivers = 0;
*driver_handle_buffer = calloc(count, sizeof(efi_handle_t));
if (!*driver_handle_buffer)
return EFI_OUT_OF_RESOURCES;
&driver_handle_buffer);
if (ret != EFI_SUCCESS)
return ret;
-
+ if (!number_of_drivers)
+ return EFI_SUCCESS;
ret = EFI_NOT_FOUND;
while (number_of_drivers) {
r = EFI_CALL(efi_disconnect_controller(
*/
static efi_status_t EFIAPI efi_stall(unsigned long microseconds)
{
+ u64 end_tick;
+
EFI_ENTRY("%ld", microseconds);
- udelay(microseconds);
+
+ end_tick = get_ticks() + usec_to_tick(microseconds);
+ while (get_ticks() < end_tick)
+ efi_timer_check();
+
return EFI_EXIT(EFI_SUCCESS);
}
* @image_obj: handle of the loaded image
* @loaded_image_protocol: loaded image protocol
*/
-static void efi_delete_image(struct efi_loaded_image_obj *image_obj,
- struct efi_loaded_image *loaded_image_protocol)
+static efi_status_t efi_delete_image
+ (struct efi_loaded_image_obj *image_obj,
+ struct efi_loaded_image *loaded_image_protocol)
{
+ struct efi_object *efiobj;
+ efi_status_t r, ret = EFI_SUCCESS;
+
+close_next:
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ struct efi_handler *protocol;
+
+ list_for_each_entry(protocol, &efiobj->protocols, link) {
+ struct efi_open_protocol_info_item *info;
+
+ list_for_each_entry(info, &protocol->open_infos, link) {
+ if (info->info.agent_handle !=
+ (efi_handle_t)image_obj)
+ continue;
+ r = EFI_CALL(efi_close_protocol
+ (efiobj, protocol->guid,
+ info->info.agent_handle,
+ info->info.controller_handle
+ ));
+ if (r != EFI_SUCCESS)
+ ret = r;
+ /*
+ * Closing protocols may results in further
+ * items being deleted. To play it safe loop
+ * over all elements again.
+ */
+ goto close_next;
+ }
+ }
+ }
+
efi_free_pages((uintptr_t)loaded_image_protocol->image_base,
efi_size_in_pages(loaded_image_protocol->image_size));
efi_delete_handle(&image_obj->header);
+
+ return ret;
}
/**
EFI_ENTRY("%p, %d", this, enable);
printf(ESC"[?25%c", enable ? 'h' : 'l');
+ efi_con_mode.cursor_visible = !!enable;
return EFI_EXIT(EFI_SUCCESS);
}
struct efi_mem_list *newlist;
bool carve_again;
uint64_t carved_pages = 0;
+ struct efi_event *evt;
EFI_PRINT("%s: 0x%llx 0x%llx %d %s\n", __func__,
start, pages, memory_type, overlap_only_ram ? "yes" : "no");
/* And make sure memory is listed in descending order */
efi_mem_sort();
+ /* Notify that the memory map was changed */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_memory_map_change)) {
+ efi_signal_event(evt, false);
+ break;
+ }
+ }
+
return start;
}
if ((s = prefix(str, "ro"))) {
attr |= READ_ONLY;
+ } else if ((s = prefix(str, "nv"))) {
+ attr |= EFI_VARIABLE_NON_VOLATILE;
} else if ((s = prefix(str, "boot"))) {
attr |= EFI_VARIABLE_BOOTSERVICE_ACCESS;
} else if ((s = prefix(str, "run"))) {
}
}
- val = malloc(2 * data_size + strlen("{ro,run,boot}(blob)") + 1);
+ val = malloc(2 * data_size + strlen("{ro,run,boot,nv}(blob)") + 1);
if (!val) {
ret = EFI_OUT_OF_RESOURCES;
goto out;
* store attributes
* TODO: several attributes are not supported
*/
- attributes &= (EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS);
+ attributes &= (EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS);
s += sprintf(s, "{");
while (attributes) {
u32 attr = 1 << (ffs(attributes) - 1);
- if (attr == EFI_VARIABLE_BOOTSERVICE_ACCESS)
+ if (attr == EFI_VARIABLE_NON_VOLATILE)
+ s += sprintf(s, "nv");
+ else if (attr == EFI_VARIABLE_BOOTSERVICE_ACCESS)
s += sprintf(s, "boot");
else if (attr == EFI_VARIABLE_RUNTIME_ACCESS)
s += sprintf(s, "run");
}
#endif
+int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size)
+{
+ const char *path;
+ int offset, err;
+
+ if (!is_valid_ethaddr(mac))
+ return -EINVAL;
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return 0;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ debug("ethernet alias points to absent node %s\n", path);
+ return -ENOENT;
+ }
+
+ err = fdt_setprop_inplace(fdt, offset, "local-mac-address", mac, size);
+ if (err < 0)
+ return err;
+
+ debug("MAC address: %pM\n", mac);
+
+ return 0;
+}
+
static int fdtdec_init_reserved_memory(void *blob)
{
int na, ns, node, err;
}
#endif
+char * strndup(const char *s, size_t n)
+{
+ size_t len;
+ char *new;
+
+ if (s == NULL)
+ return NULL;
+
+ len = strlen(s);
+
+ if (n < len)
+ len = n;
+
+ new = malloc(len + 1);
+ if (new == NULL)
+ return NULL;
+
+ strncpy(new, s, len);
+ new[len] = '\0';
+
+ return new;
+}
+
#ifndef __HAVE_ARCH_STRSPN
/**
* strspn - Calculate the length of the initial substring of @s which only
return tick_to_time(get_ticks() * 1000);
}
-static uint64_t usec_to_tick(unsigned long usec)
+uint64_t usec_to_tick(unsigned long usec)
{
uint64_t tick = usec;
tick *= get_tbclk();
/*
* uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
*
- * @param uuid_bin - pointer to binary data of UUID (big endian) [16B]
- * @param uuid_str - pointer to allocated array for output string [37B]
- * @str_format - UUID string format: 0 - UUID; 1 - GUID
+ * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
+ * @param uuid_str: pointer to allocated array for output string [37B]
+ * @str_format: bit 0: 0 - UUID; 1 - GUID
+ * bit 1: 0 - lower case; 2 - upper case
*/
void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format)
{
const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8,
9, 10, 11, 12, 13, 14, 15};
const u8 *char_order;
+ const char *format;
int i;
/*
* 4B-2B-2B-2B-6B
* be be be be be
*/
- if (str_format == UUID_STR_FORMAT_STD)
+ if (str_format & UUID_STR_FORMAT_GUID)
+ char_order = guid_char_order;
+ else
char_order = uuid_char_order;
+ if (str_format & UUID_STR_UPPER_CASE)
+ format = "%02X";
else
- char_order = guid_char_order;
+ format = "%02x";
for (i = 0; i < 16; i++) {
- sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]);
+ sprintf(uuid_str, format, uuid_bin[char_order[i]]);
uuid_str += 2;
switch (i) {
case 3:
#ifdef CONFIG_LIB_UUID
/*
- * This works (roughly) the same way as linux's, but we currently always
- * print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
- * mostly just because that is what uuid_bin_to_str() supports.
+ * This works (roughly) the same way as Linux's.
*
* %pUb: 01020304-0506-0708-090a-0b0c0d0e0f10
+ * %pUB: 01020304-0506-0708-090A-0B0C0D0E0F10
* %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10
+ * %pUL: 04030201-0605-0807-090A-0B0C0D0E0F10
*/
static char *uuid_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags, const char *fmt)
{
char uuid[UUID_STR_LEN + 1];
- int str_format = UUID_STR_FORMAT_STD;
+ int str_format;
switch (*(++fmt)) {
case 'L':
+ str_format = UUID_STR_FORMAT_GUID | UUID_STR_UPPER_CASE;
+ break;
case 'l':
str_format = UUID_STR_FORMAT_GUID;
break;
case 'B':
- case 'b':
- /* this is the default */
+ str_format = UUID_STR_FORMAT_STD | UUID_STR_UPPER_CASE;
break;
default:
+ str_format = UUID_STR_FORMAT_STD;
break;
}
#define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \
"and a lot more text to come"
+/* Test printing GUIDs */
+static void guid_ut_print(void)
+{
+#if CONFIG_IS_ENABLED(LIB_UUID)
+ unsigned char guid[16] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ };
+ char str[40];
+
+ sprintf(str, "%pUb", guid);
+ assert(!strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str));
+ sprintf(str, "%pUB", guid);
+ assert(!strcmp("01020304-0506-0708-090A-0B0C0D0E0F10", str));
+ sprintf(str, "%pUl", guid);
+ assert(!strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str));
+ sprintf(str, "%pUL", guid);
+ assert(!strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str));
+#endif
+}
+
/* Test efi_loader specific printing */
static void efi_ut_print(void)
{
/* Test efi_loader specific printing */
efi_ut_print();
+ /* Test printing GUIDs */
+ guid_ut_print();
+
printf("%s: Everything went swimmingly\n", __func__);
return 0;
}
hostprogs-y += fdtgrep
fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o
+ifneq ($(TOOLS_ONLY),y)
+hostprogs-y += spl_size_limit
+endif
+
hostprogs-$(CONFIG_MIPS) += mips-relocs
# We build some files with extra pedantic flags to try to minimize things
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019, Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
+ *
+ * This tool helps to return the size available for SPL image during build
+ */
+
+#include <generated/autoconf.h>
+#include <generated/generic-asm-offsets.h>
+
+int main(int argc, char *argv[])
+{
+ int spl_size_limit = 0;
+
+#ifdef CONFIG_SPL_SIZE_LIMIT
+ spl_size_limit = CONFIG_SPL_SIZE_LIMIT;
+#ifdef CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD
+ spl_size_limit -= GENERATED_GBL_DATA_SIZE;
+#endif
+#ifdef CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC
+ spl_size_limit -= CONFIG_SPL_SYS_MALLOC_F_LEN;
+#endif
+#ifdef CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK
+ spl_size_limit -= CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK;
+#endif
+#endif
+
+ printf("%d", spl_size_limit);
+ return 0;
+}
projects / project / bcm63xx / u-boot.git / commitdiff