Markus Klotzbuecher <mk@denx.de>
Prabhakar Kushwaha <prabhakar@freescale.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Ricardo Ribalda <ricardo.ribalda@uam.es>
+Ricardo Ribalda <ricardo.ribalda@gmail.com>
Sandeep Paulraj <s-paulraj@ti.com>
Shaohui Xie <Shaohui.Xie@freescale.com>
Stefan Roese <stroese>
select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
- select SPL_OF_CONTROL
+ select SPL_OF_CONTROL if SPL
select DM
select DM_ETH
- select SPL_DM
+ select SPL_DM if SPL
select DM_MMC
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
- select SPL_SEPARATE_BSS
+ select SPL_SEPARATE_BSS if SPL
config ARCH_ZYNQMP
bool "Support Xilinx ZynqMP Platform"
/* port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY_2_CFG 0x28183411
-#define AHCI_PORT_PHY_3_CFG 0x0e081004
-#define AHCI_PORT_PHY_4_CFG 0x00480811
-#define AHCI_PORT_PHY_5_CFG 0x192c96a4
-#define AHCI_PORT_TRANS_CFG 0x08000025
+#define AHCI_PORT_PHY_2_CFG 0x28183414
+#define AHCI_PORT_PHY_3_CFG 0x0e080e06
+#define AHCI_PORT_PHY_4_CFG 0x064a080b
+#define AHCI_PORT_PHY_5_CFG 0x2aa86470
+#define AHCI_PORT_TRANS_CFG 0x08000029
#define SATA_ECC_REG_ADDR 0x20220520
#define SATA_ECC_DISABLE 0x00020000
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
+ do_fixup_by_compat_u32(blob, "fixed-clock",
+ "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
SGMII1 } },
{0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
{0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
-#ifdef CONFIG_LS2080A
- {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
-#endif
-#ifdef CONFIG_LS2085A
{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
-#endif
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include <fsl_validate.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
init_early_memctl_regs(); /* tighten IFC timing */
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
/* Make SEC reads and writes snoopable */
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP);
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
config SYS_CONFIG_NAME
default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
-config SECURE_IOU
- bool "Configure ZynqMP secure IOU"
- default n
-
config ZYNQMP_USB
bool "Configure ZynqMP USB"
return 48000;
case ZYNQMP_CSU_VERSION_EP108:
return 25000000;
+ case ZYNQMP_CSU_VERSION_QEMU:
+ return 133000000;
}
- return 133000000;
+ return 100000000;
+}
+
+unsigned long zynqmp_get_system_timer_freq(void)
+{
+ u32 ver = zynqmp_get_silicon_version();
+
+ switch (ver) {
+ case ZYNQMP_CSU_VERSION_VELOCE:
+ return 10000;
+ case ZYNQMP_CSU_VERSION_EP108:
+ return 4000000;
+ case ZYNQMP_CSU_VERSION_QEMU:
+ return 50000000;
+ }
+
+ return 100000000;
}
#ifdef CONFIG_CLOCKS
DECLARE_GLOBAL_DATA_PTR;
+static unsigned int zynqmp_get_silicon_version_secure(void)
+{
+ u32 ver;
+
+ ver = readl(&csu_base->version);
+ ver &= ZYNQMP_SILICON_VER_MASK;
+ ver >>= ZYNQMP_SILICON_VER_SHIFT;
+
+ return ver;
+}
+
unsigned int zynqmp_get_silicon_version(void)
{
+ if (current_el() == 3)
+ return zynqmp_get_silicon_version_secure();
+
gd->cpu_clk = get_tbclk();
switch (gd->cpu_clk) {
return ZYNQMP_CSU_VERSION_VELOCE;
case 50000000:
return ZYNQMP_CSU_VERSION_QEMU;
+ case 4000000:
+ return ZYNQMP_CSU_VERSION_EP108;
}
- return ZYNQMP_CSU_VERSION_EP108;
+ return ZYNQMP_CSU_VERSION_SILICON;
}
#ifndef CONFIG_SYS_DCACHE_OFF
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
-dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+ fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
--- /dev/null
+/*
+ * Device Tree file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
--- /dev/null
+/*
+ * Device Tree file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &lpuart0;
+ };
+};
+++ /dev/null
-/*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
- *
- * Copyright (C) 2015, Freescale Semiconductor
- *
- * Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
-
-/ {
- model = "LS1043A QDS Board";
-};
-
-&i2c0 {
- status = "okay";
- pca9547@77 {
- compatible = "philips,pca9547";
- reg = <0x77>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0>;
-
- rtc@68 {
- compatible = "dallas,ds3232";
- reg = <0x68>;
- /* IRQ10_B */
- interrupts = <0 150 0x4>;
- };
- };
-
- i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x2>;
-
- ina220@40 {
- compatible = "ti,ina220";
- reg = <0x40>;
- shunt-resistor = <1000>;
- };
-
- ina220@41 {
- compatible = "ti,ina220";
- reg = <0x41>;
- shunt-resistor = <1000>;
- };
- };
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x3>;
-
- eeprom@56 {
- compatible = "at24,24c512";
- reg = <0x56>;
- };
-
- eeprom@57 {
- compatible = "at24,24c512";
- reg = <0x57>;
- };
-
- adt7461a@4c {
- compatible = "adt7461a";
- reg = <0x4c>;
- };
- };
- };
-};
-
-&ifc {
- #address-cells = <2>;
- #size-cells = <1>;
- /* NOR, NAND Flashes and FPGA on board */
- ranges = <0x0 0x0 0x0 0x60000000 0x08000000
- 0x2 0x0 0x0 0x7e800000 0x00010000
- 0x3 0x0 0x0 0x7fb00000 0x00000100>;
- status = "okay";
-
- nor@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash";
- reg = <0x0 0x0 0x8000000>;
- bank-width = <2>;
- device-width = <1>;
- };
-
- nand@2,0 {
- compatible = "fsl,ifc-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x1 0x0 0x10000>;
- };
-
- fpga: board-control@3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- reg = <0x3 0x0 0x0000100>;
- bank-width = <1>;
- device-width = <1>;
- ranges = <0 3 0 0x100>;
- };
-};
-
-&duart0 {
- status = "okay";
-};
-
-&duart1 {
- status = "okay";
-};
--- /dev/null
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+ model = "LS1043A QDS Board";
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547@77 {
+ compatible = "philips,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ /* IRQ10_B */
+ interrupts = <0 150 0x4>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220@41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ eeprom@56 {
+ compatible = "at24,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom@57 {
+ compatible = "at24,24c512";
+ reg = <0x57>;
+ };
+
+ adt7461a@4c {
+ compatible = "adt7461a";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7e800000 0x00010000
+ 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ status = "okay";
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ fpga: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ reg = <0x3 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 3 0 0x100>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&lpuart0 {
+ status = "okay";
+};
interrupts = <0 55 0x4>;
clocks = <&clockgen 4 0>;
};
+
+ lpuart0: serial@2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <0 48 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <0 49 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <0 50 0x4>;
+ clock-names = "ipg";
+ clocks = <&sysclk>;
+ status = "disabled";
+ };
+
+ lpuart3: serial@2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <0 51 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+ qspi: quadspi@1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1550000 0x10000>,
+ <0x40000000 0x4000000>;
+ num-cs = <2>;
+ big-endian;
+ status = "disabled";
+ };
};
};
interrupt-parent = <&intc>;
interrupts = <0 24 4>;
reg = <0xe0100000 0x1000>;
- } ;
+ };
sdhci1: sdhci@e0101000 {
compatible = "arasan,sdhci-8.9a";
interrupt-parent = <&intc>;
interrupts = <0 47 4>;
reg = <0xe0101000 0x1000>;
- } ;
+ };
slcr: slcr@f8000000 {
#address-cells = <1>;
scutimer: timer@f8f00600 {
interrupt-parent = <&intc>;
- interrupts = < 1 13 0x301 >;
+ interrupts = <1 13 0x301>;
compatible = "arm,cortex-a9-twd-timer";
- reg = < 0xf8f00600 0x20 >;
+ reg = <0xf8f00600 0x20>;
clocks = <&clkc 4>;
- } ;
+ };
usb0: usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
};
chosen {
- bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
- linux,stdout-path = &uart1;
- stdout-path = &uart1;
+ bootargs = "root=/dev/ram rw earlyprintk";
+ stdout-path = "serial0:115200n8";
};
memory {
};
chosen {
- bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
- linux,stdout-path = &uart1;
- stdout-path = &uart1;
+ bootargs = "root=/dev/ram rw earlyprintk";
+ stdout-path = "serial0:115200n8";
};
memory {
};
};
-&spi0 {
- status = "okay";
- num-cs = <4>;
- is-decoded-cs = <0>;
-};
-
&can0 {
status = "okay";
};
};
};
+&spi0 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+};
+
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
};
chosen {
- bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
- linux,stdout-path = &uart1;
- stdout-path = &uart1;
+ bootargs = "root=/dev/ram rw earlyprintk";
+ stdout-path = "serial0:115200n8";
};
memory {
};
};
-&spi1 {
- status = "okay";
- num-cs = <4>;
- is-decoded-cs = <0>;
-};
-
&can1 {
status = "okay";
};
};
};
+&spi1 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+};
+
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
};
chosen {
- bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
- linux,stdout-path = &uart0;
- stdout-path = &uart0;
+ bootargs = "root=/dev/ram rw earlyprintk";
+ stdout-path = "serial0:115200n8";
};
memory {
};
};
-&spi0 {
- status = "okay";
- num-cs = <4>;
- is-decoded-cs = <0>;
- eeprom: at25@0 {
- at25,byte-len = <8192>;
- at25,addr-mode = <2>;
- at25,page-size = <32>;
-
- compatible = "atmel,at25";
- reg = <2>;
- spi-max-frequency = <1000000>;
- };
-};
-
&can1 {
status = "okay";
};
};
};
+&spi0 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+ eeprom: at25@0 {
+ at25,byte-len = <8192>;
+ at25,addr-mode = <2>;
+ at25,page-size = <32>;
+
+ compatible = "atmel,at25";
+ reg = <2>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- phy0: phy@0{
+ phy0: phy@0 {
reg = <0>;
max-speed = <100>;
};
};
uart0: serial@ff000000 {
- compatible = "cdns,uart-r1p8";
+ compatible = "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
};
uart1: serial@ff010000 {
- compatible = "cdns,uart-r1p8";
+ compatible = "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 52 1>;
+ interrupts = <0 113 1>;
reg = <0x0 0xfd4d0000 0x1000>;
timeout-sec = <10>;
};
#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_ERRATUM_A009635
+#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009929
#else
#error SoC not defined
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+ CPU_TYPE_ENTRY(LS2040, LS2040, 4),
};
#ifndef CONFIG_SYS_DCACHE_OFF
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+#define RCW_SB_EN_REG_INDEX 7
+#define RCW_SB_EN_MASK 0x00200000
+
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
u32 res_0c; /* 0x00c */
u32 pllcr3;
u32 pllcr4;
- u8 res_18[0x20-0x18];
+ u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
+ u8 res_1c[0x20-0x1c];
} bank[2];
u8 res_40[0x90-0x40];
u32 srdstcalcr; /* 0x90 TX Calibration Control */
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
u8 res_a4[0xb0-0xa4];
u32 srdsgr0; /* 0xb0 General Register 0 */
- u8 res_b4[0xe0-0xb4];
- u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
- u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
- u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
- u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
- u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
- u8 res_f4[0x100-0xf4];
+ u8 res_b4[0x100-0xb4];
struct {
- u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+ u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */
u8 res_104[0x120-0x104];
- } srdslnpssr[4];
- u8 res_180[0x300-0x180];
- u32 srdspexeqcr;
- u32 srdspexeqpcr[11];
- u8 res_330[0x400-0x330];
- u32 srdspexapcr;
- u8 res_404[0x440-0x404];
- u32 srdspexbpcr;
- u8 res_444[0x800-0x444];
+ } lnpssr[4]; /* Lane A, B, C, D */
+ u8 res_180[0x200-0x180];
+ u32 srdspccr0; /* 0x200 Protocol Configuration 0 */
+ u32 srdspccr1; /* 0x204 Protocol Configuration 1 */
+ u32 srdspccr2; /* 0x208 Protocol Configuration 2 */
+ u32 srdspccr3; /* 0x20c Protocol Configuration 3 */
+ u32 srdspccr4; /* 0x210 Protocol Configuration 4 */
+ u32 srdspccr5; /* 0x214 Protocol Configuration 5 */
+ u32 srdspccr6; /* 0x218 Protocol Configuration 6 */
+ u32 srdspccr7; /* 0x21c Protocol Configuration 7 */
+ u32 srdspccr8; /* 0x220 Protocol Configuration 8 */
+ u32 srdspccr9; /* 0x224 Protocol Configuration 9 */
+ u32 srdspccra; /* 0x228 Protocol Configuration A */
+ u32 srdspccrb; /* 0x22c Protocol Configuration B */
+ u8 res_230[0x800-0x230];
struct {
u32 gcr0; /* 0x800 General Control Register 0 */
u32 gcr1; /* 0x804 General Control Register 1 */
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
u8 res_824[0x83c-0x824];
u32 tcsr3;
- } lane[4]; /* Lane A, B, C, D, E, F, G, H */
- u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
+ } lane[4]; /* Lane A, B, C, D */
+ u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */
+ struct {
+ u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
+ u8 res_1004[0x1040-0x1004];
+ } pcie[3];
+ u8 res_10c0[0x1800-0x10c0];
+ struct {
+ u8 res_1800[0x1804-0x1800];
+ u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */
+ u8 res_1808[0x180c-0x1808];
+ u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */
+ } sgmii[4]; /* Lane A, B, C, D */
+ u8 res_1840[0x1880-0x1840];
+ struct {
+ u8 res_1880[0x1884-0x1880];
+ u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */
+ u8 res_1888[0x188c-0x1888];
+ u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */
+ } qsgmii[2]; /* Lane A, B */
+ u8 res_18a0[0x1980-0x18a0];
+ struct {
+ u8 res_1980[0x1984-0x1980];
+ u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
+ u8 res_1988[0x198c-0x1988];
+ u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
+ } xfi[2]; /* Lane A, B */
+ u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
};
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define SVR_LS2045 0x870120
#define SVR_LS2080 0x870110
#define SVR_LS2085 0x870100
+#define SVR_LS2040 0x870130
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
+#define CONFIG_SYS_FSL_ERRATUM_A009663
#else
#error SoC not defined
#endif
u32 brrl; /* Boot release */
u8 res_0e8[0x100-0xe8];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX 7
+#define RCW_SB_EN_MASK 0x00200000
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
#define _ASM_ARCH_CLK_H_
unsigned long get_uart_clk(int dev_id);
+unsigned long zynqmp_get_system_timer_freq(void);
#endif /* _ASM_ARCH_CLK_H_ */
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
-#if defined(CONFIG_SECURE_IOU)
-#define ZYNQMP_IOU_SCNTR 0xFF260000
-#else
+#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
#define ZYNQMP_IOU_SCNTR 0xFF250000
-#endif
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
+struct iou_scntr_secure {
+ u32 counter_control_register;
+ u32 reserved0[7];
+ u32 base_frequency_id_register;
+};
+
+#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
+
/* Bootmode setting values */
#define BOOT_MODES_MASK 0x0000000F
-#define SD_MODE 0x00000003
+#define QSPI_MODE_24BIT 0x00000001
+#define QSPI_MODE_32BIT 0x00000002
+#define SD_MODE 0x00000003 /* sd 0 */
+#define SD_MODE1 0x00000005 /* sd 1 */
+#define NAND_MODE 0x00000004
#define EMMC_MODE 0x00000006
#define JTAG_MODE 0x00000000
#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
/* Board version value */
+#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
#define ZYNQMP_CSU_VERSION_SILICON 0x0
#define ZYNQMP_CSU_VERSION_EP108 0x1
#define ZYNQMP_CSU_VERSION_VELOCE 0x2
#define ZYNQMP_CSU_VERSION_QEMU 0x3
+#define ZYNQMP_SILICON_VER_MASK 0xF000
+#define ZYNQMP_SILICON_VER_SHIFT 12
+
+struct csu_regs {
+ u32 reserved0[17];
+ u32 version;
+};
+
+#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
#define __FSL_SECURE_BOOT_H
#ifdef CONFIG_SECURE_BOOT
+
+#ifndef CONFIG_FIT_SIGNATURE
+#define CONFIG_CHAIN_OF_TRUST
+#endif
+
+#endif
+
+#ifdef CONFIG_CHAIN_OF_TRUST
#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_CMD_BLOB
#define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_PROG_HW_ACCEL
#define CONFIG_RSA
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
-#ifndef CONFIG_FIT_SIGNATURE
+#ifdef CONFIG_LS1043A
+/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
#define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xcfffffff;" \
/* The address needs to be modified according to NOR memory map */
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000
-#include <config_fsl_secboot.h>
-#endif
-#endif
-
+#include <config_fsl_chain_trust.h>
+#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif
*/
/* cppcheck-suppress nullPointer */
memset((void *)0, 0, 1 * 1024 * 1024);
-
- gd->ram_size /= 2;
} else {
puts("ECC disabled ");
}
select SUPPORT_SPL
select OF_CONTROL
select DM
+ select DM_SERIAL
endchoice
extra-y = start.o
obj-y = irq.o
-obj-y += cpu.o interrupts.o cache.o exception.o timer.o
+obj-y += interrupts.o cache.o exception.o timer.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+++ /dev/null
-/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* EMPTY FILE */
cmp r6, r5, r4 /* check if we have reach the end */
bnei r6, 2b
3: /* jumping to board_init */
+#ifdef CONFIG_DEBUG_UART
+ bralid r15, debug_uart_init
+ nop
+#endif
#ifndef CONFIG_SPL_BUILD
or r5, r0, r0 /* flags - empty */
addi r31, r0, _gd
#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS)
puts("Work-around for Erratum XFI on B4860QDS enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
+ puts("Work-around for Erratum A009663 enabled\n");
+#endif
return 0;
}
#include <hwconfig.h>
#include <linux/compiler.h>
#include "mp.h"
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include <fsl_validate.h>
+#endif
#ifdef CONFIG_FSL_CAAM
#include <fsl_sec.h>
#endif
qe_reset();
#endif
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
+
+ return 0;
+}
+#endif
config TARGET_YUCCA
bool "Support yucca"
-config TARGET_FX12MM
- bool "Support fx12mm"
-
-config TARGET_V5FX30TEVAL
- bool "Support v5fx30teval"
-
config TARGET_CPCI2DP
bool "Support CPCI2DP"
config TARGET_XPEDITE1000
bool "Support xpedite1000"
-config TARGET_ML507
- bool "Support ml507"
-
config TARGET_XILINX_PPC405_GENERIC
bool "Support xilinx-ppc405-generic"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
config TARGET_XILINX_PPC440_GENERIC
bool "Support xilinx-ppc440-generic"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
endchoice
source "board/amcc/walnut/Kconfig"
source "board/amcc/yosemite/Kconfig"
source "board/amcc/yucca/Kconfig"
-source "board/avnet/fx12mm/Kconfig"
-source "board/avnet/v5fx30teval/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
source "board/esd/plu405/Kconfig"
source "board/mpl/pip405/Kconfig"
source "board/t3corp/Kconfig"
source "board/xes/xpedite1000/Kconfig"
-source "board/xilinx/ml507/Kconfig"
source "board/xilinx/ppc405-generic/Kconfig"
source "board/xilinx/ppc440-generic/Kconfig"
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
*
* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
- * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* Work supported by Qtechnology (htpp://qtec.com)
*
* SPDX-License-Identifier: GPL-2.0+
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
*
* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
- * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* Work supported by Qtechnology (htpp://qtec.com)
*
* SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
* SPDX-License-Identifier: GPL-2.0+
#
dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb
+dtb-$(CONFIG_TARGET_XILINX_PPC440_GENERIC) += xilinx-ppc440-generic.dtb
+dtb-$(CONFIG_TARGET_XILINX_PPC405_GENERIC) += xilinx-ppc405-generic.dtb
targets += $(dtb-y)
--- /dev/null
+/dts-v1/;
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ };
+
+ uart0: serial@84000000 {
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ interrupts = <0 0>;
+ reg = <0x84000000 0x10000>;
+ };
+} ;
--- /dev/null
+/dts-v1/;
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ };
+
+ uart0: serial@8b000000 {
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ interrupts = <0 0>;
+ reg = <0x8b000000 0x10000>;
+ };
+} ;
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ERRATUM_A008378
+#define CONFIG_SYS_FSL_ERRATUM_A009663
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ERRATUM_A008378
+#define CONFIG_SYS_FSL_ERRATUM_A009663
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_ESBC_VALIDATE
-#define CONFIG_FSL_SEC_MON
-#define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_DM
-#define CONFIG_RSA
-#define CONFIG_RSA_FREESCALE_EXP
-#ifndef CONFIG_FSL_CAAM
-#define CONFIG_FSL_CAAM
-#endif
+
+#ifndef CONFIG_FIT_SIGNATURE
+#define CONFIG_CHAIN_OF_TRUST
#endif
-#ifdef CONFIG_SECURE_BOOT
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
#elif defined(CONFIG_BSC9132QDS)
*/
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
+#endif /* #ifdef CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_CMD_BLOB
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+
+#ifndef CONFIG_DM
+#define CONFIG_DM
+#endif
+
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+
+/* fsl_setenv_chain_of_trust() must be called from
+ * board_late_init()
+ */
+#ifndef CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
+#endif
-#ifndef CONFIG_FIT_SIGNATURE
/* If Boot Script is not on NOR and is required to be copied on RAM */
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
#endif
-#endif
-
-#include <config_fsl_secboot.h>
-#endif
+#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
-#endif
+#include <config_fsl_chain_trust.h>
+#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif
u32 brrl; /* Boot release */
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX 7
+#define RCW_SB_EN_MASK 0x00200000
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
#endif
+#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
/* The 8544 RM says this is bit 26, but it's really bit 24 */
#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
u8 res1[8];
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
*
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
* SPDX-License-Identifier: GPL-2.0+
+++ /dev/null
-if TARGET_FX12MM
-
-config SYS_BOARD
- default "fx12mm"
-
-config SYS_VENDOR
- default "avnet"
-
-config SYS_CONFIG_NAME
- default "fx12mm"
-
-endif
+++ /dev/null
-FX12MM BOARD
-M: Georg Schardt <schardt@team-ctech.de>
-S: Maintained
-F: board/avnet/fx12mm/
-F: include/configs/fx12mm.h
-F: configs/fx12mm_defconfig
-F: configs/fx12mm_flash_defconfig
+++ /dev/null
-#
-# (C) Copyright 2008
-# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
-# This work has been supported by: Qtechnology http://qtec.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += fx12mm.o
-
-include $(srctree)/board/xilinx/ppc405-generic/Makefile
+++ /dev/null
-/*
- * (C) Copyright 2008
- *
- * Author: Xilinx Inc.
- *
- * Modified by:
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- if (l < 0) {
- printf("Avnet Virtex4 FX12 with no serial #");
- } else {
- printf("Avnet Virtex4 FX12 Minimodul # ");
- for (i = 0; i < l; ++i) {
- if (buf[i] == ' ')
- break;
- putc(buf[i]);
- }
- }
- putc('\n');
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- *
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * CAUTION: This file is based on the xparameters.h automatically
- * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
- */
-
-#ifndef __XPARAMETER_H__
-#define __XPARAMETER_H__
-
-/* RS232 */
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
-#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
-
-
-/* INT_C */
-#define XPAR_XPS_INTC_0_DEVICE_ID 0
-#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
-
-/* CPU core clock */
-#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-
-/* RAM */
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
-
-/* FLASH */
-#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
-
-#endif
+++ /dev/null
-if TARGET_V5FX30TEVAL
-
-config SYS_BOARD
- default "v5fx30teval"
-
-config SYS_VENDOR
- default "avnet"
-
-config SYS_CONFIG_NAME
- default "v5fx30teval"
-
-endif
+++ /dev/null
-V5FX30TEVAL BOARD
-M: Ricardo Ribalda <ricardo.ribalda@uam.es>
-S: Maintained
-F: board/avnet/v5fx30teval/
-F: include/configs/v5fx30teval.h
-F: configs/v5fx30teval_defconfig
-F: configs/v5fx30teval_flash_defconfig
+++ /dev/null
-#
-# (C) Copyright 2008
-# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
-# This work has been supported by: Qtechnology http://qtec.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += v5fx30teval.o
-
-include $(srctree)/board/xilinx/ppc440-generic/Makefile
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com/
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-
-int checkboard(void)
-{
- puts("Avnet Virtex 5 FX30 Evaluation Board\n");
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com/
- * based on xparameters.h by Xilinx
- *
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef XPARAMETER_H
-#define XPARAMETER_H
-
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
-#define XPAR_INTC_0_BASEADDR 0x81800000
-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
-#define XPAR_UARTLITE_0_BAUDRATE 9600
-
-#endif
ifdef CONFIG_SECURE_BOOT
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
endif
+obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
endif
static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+ if (fsl_check_boot_mode_secure() == 0) {
+ printf("Boot Mode is Non-Secure. Not entering spin loop.\n");
+ return 0;
+ }
+
printf("Core is entering spin loop.\n");
loop:
goto loop;
static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+ char *hash_str = NULL;
+ uintptr_t haddr;
+ int ret;
+
if (argc < 2)
return cmd_usage(cmdtp);
+ else if (argc > 2)
+ /* Second arg - Optional - Hash Str*/
+ hash_str = argv[2];
+
+ /* First argument - header address -32/64bit */
+ haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16);
- return fsl_secboot_validate(cmdtp, flag, argc, argv);
+ /* With esbc_validate command, Image address must be
+ * part of header. So, the function is called
+ * by passing this argument as 0.
+ */
+ ret = fsl_secboot_validate(haddr, hash_str, 0);
+ if (ret)
+ return 1;
+
+ printf("esbc_validate command successful\n");
+ return 0;
}
/***************************************************/
U_BOOT_CMD(
esbc_halt, 1, 0, do_esbc_halt,
- "Put the core in spin loop ",
+ "Put the core in spin loop (Secure Boot Only)",
""
);
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_validate.h>
+#include <fsl_sfp.h>
+
+#ifdef CONFIG_LS102XA
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#if defined(CONFIG_MPC85xx)
+#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#else
+#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a) in_le32(a)
+#else
+#define gur_in32(a) in_be32(a)
+#endif
+
+/* Check the Boot Mode. If Secure, return 1 else return 0 */
+int fsl_check_boot_mode_secure(void)
+{
+ uint32_t val;
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+
+ val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
+ if (val == ITS_MASK)
+ return 1;
+
+#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
+ /* For PBL based platforms check the SB_EN bit in RCWSR */
+ val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
+ if (val == RCW_SB_EN_MASK)
+ return 1;
+#endif
+
+#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
+ /* For Non-PBL Platforms, check the Device Status register 2*/
+ val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
+ if (val != MPC85xx_PORDEVSR2_SBC_MASK)
+ return 1;
+
+#endif
+ return 0;
+}
+
+int fsl_setenv_chain_of_trust(void)
+{
+ /* Check Boot Mode
+ * If Boot Mode is Non-Secure, no changes are required
+ */
+ if (fsl_check_boot_mode_secure() == 0)
+ return 0;
+
+ /* If Boot mode is Secure, set the environment variables
+ * bootdelay = 0 (To disable Boot Prompt)
+ * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+ */
+ setenv("bootdelay", "0");
+ setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+ return 0;
+}
#define SHA256_NIBBLES (256/4)
#define NUM_HEX_CHARS (sizeof(ulong) * 2)
+#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
+ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
+ ((key_len) == 2 * KEY_SIZE_BYTES))
+
/* This array contains DER value for SHA-256 */
static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00,
return 0;
}
-/* It validates srk_table key lengths.*/
-static u32 validate_srk_tbl(struct srk_table *tbl, u32 num_entries)
+/* It read validates srk_table key lengths.*/
+static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img)
{
int i = 0;
- for (i = 0; i < num_entries; i++) {
- if (!((tbl[i].key_len == 2 * KEY_SIZE_BYTES/4) ||
- (tbl[i].key_len == 2 * KEY_SIZE_BYTES/2) ||
- (tbl[i].key_len == 2 * KEY_SIZE_BYTES)))
+ u32 ret, key_num, key_revoc_flag, size;
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+
+ if ((hdr->len_kr.num_srk == 0) ||
+ (hdr->len_kr.num_srk > MAX_KEY_ENTRIES))
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY;
+
+ key_num = hdr->len_kr.srk_sel;
+ if (key_num == 0 || key_num > hdr->len_kr.num_srk)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM;
+
+ /* Get revoc key from sfp */
+ key_revoc_flag = get_key_revoc();
+ ret = is_key_revoked(key_num, key_revoc_flag);
+ if (ret)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED;
+
+ size = hdr->len_kr.num_srk * sizeof(struct srk_table);
+
+ memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size);
+
+ for (i = 0; i < hdr->len_kr.num_srk; i++) {
+ if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len))
return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN;
}
+
+ img->key_len = img->srk_tbl[key_num - 1].key_len;
+
+ memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey),
+ img->key_len);
+
+ return 0;
+}
+#endif
+
+static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
+{
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+
+ /* check key length */
+ if (!CHECK_KEY_LEN(hdr->key_len))
+ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN;
+
+ memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len);
+
+ img->key_len = hdr->key_len;
+
+ return 0;
+}
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
+{
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ u32 ie_key_len, ie_revoc_flag, ie_num;
+ struct ie_key_info *ie_info;
+
+ if (get_ie_info_addr(&img->ie_addr))
+ return ERROR_IE_TABLE_NOT_FOUND;
+ ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
+ if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
+
+ ie_num = hdr->ie_key_sel;
+ if (ie_num == 0 || ie_num > ie_info->num_keys)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM;
+
+ ie_revoc_flag = ie_info->key_revok;
+ if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag)
+ return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED;
+
+ ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len;
+
+ if (!CHECK_KEY_LEN(ie_key_len))
+ return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN;
+
+ memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey),
+ ie_key_len);
+
+ img->key_len = ie_key_len;
return 0;
}
#endif
+
/* This function return length of public key.*/
static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
{
printf("ERROR :: %x :: %s\n", error, e->name);
}
+ /* If Boot Mode is secure, transition the SNVS state and issue
+ * reset based on type of failure and ITS setting.
+ * If Boot mode is non-secure, return from this function.
+ */
+ if (fsl_check_boot_mode_secure() == 0)
+ return;
+
switch (error) {
case ERROR_ESBC_CLIENT_HEADER_BARKER:
case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
return ret;
/* Update hash for actual Image */
-#ifdef CONFIG_ESBC_ADDR_64BIT
- ret = algo->hash_update(algo, ctx,
- (u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1);
-#else
ret = algo->hash_update(algo, ctx,
- (u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1);
-#endif
+ (u8 *)img->img_addr, img->img_size, 1);
if (ret)
return ret;
struct fsl_secboot_img_hdr *hdr = &img->hdr;
void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
u8 *k, *s;
+ u32 ret = 0;
+
#ifdef CONFIG_KEY_REVOCATION
- u32 ret;
- u32 key_num, key_revoc_flag, size;
-#endif
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
- struct ie_key_info *ie_info;
- u32 ie_num, ie_revoc_flag, ie_key_len;
#endif
int key_found = 0;
if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
-#ifdef CONFIG_ESBC_ADDR_64BIT
- sprintf(buf, "%llx", hdr->pimg64);
-#else
- sprintf(buf, "%x", hdr->pimg);
-#endif
+ /* If Image Address is not passed as argument to function,
+ * then Address and Size must be read from the Header.
+ */
+ if (img->img_addr == 0) {
+ #ifdef CONFIG_ESBC_ADDR_64BIT
+ img->img_addr = hdr->pimg64;
+ #else
+ img->img_addr = hdr->pimg;
+ #endif
+ }
+
+ sprintf(buf, "%lx", img->img_addr);
setenv("img_addr", buf);
if (!hdr->img_size)
return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
+ img->img_size = hdr->img_size;
+
/* Key checking*/
#ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
- if ((hdr->len_kr.num_srk == 0) ||
- (hdr->len_kr.num_srk > MAX_KEY_ENTRIES))
- return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY;
-
- key_num = hdr->len_kr.srk_sel;
- if (key_num == 0 || key_num > hdr->len_kr.num_srk)
- return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM;
-
- /* Get revoc key from sfp */
- key_revoc_flag = get_key_revoc();
- ret = is_key_revoked(key_num, key_revoc_flag);
- if (ret)
- return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED;
-
- size = hdr->len_kr.num_srk * sizeof(struct srk_table);
-
- memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size);
-
- ret = validate_srk_tbl(img->srk_tbl, hdr->len_kr.num_srk);
-
+ ret = read_validate_srk_tbl(img);
if (ret != 0)
return ret;
-
- img->key_len = img->srk_tbl[key_num - 1].key_len;
-
- memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey),
- img->key_len);
-
key_found = 1;
}
#endif
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
if (!key_found && check_ie(img)) {
- if (get_ie_info_addr(&img->ie_addr))
- return ERROR_IE_TABLE_NOT_FOUND;
- ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
- if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
- return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
-
- ie_num = hdr->ie_key_sel;
- if (ie_num == 0 || ie_num > ie_info->num_keys)
- return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM;
-
- ie_revoc_flag = ie_info->key_revok;
- if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag)
- return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED;
-
- ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len;
-
- if (!((ie_key_len == 2 * KEY_SIZE_BYTES / 4) ||
- (ie_key_len == 2 * KEY_SIZE_BYTES / 2) ||
- (ie_key_len == 2 * KEY_SIZE_BYTES)))
- return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN;
-
- memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey),
- ie_key_len);
-
- img->key_len = ie_key_len;
+ ret = read_validate_ie_tbl(img);
+ if (ret != 0)
+ return ret;
key_found = 1;
}
#endif
if (key_found == 0) {
- /* check key length */
- if (!((hdr->key_len == 2 * KEY_SIZE_BYTES / 4) ||
- (hdr->key_len == 2 * KEY_SIZE_BYTES / 2) ||
- (hdr->key_len == 2 * KEY_SIZE_BYTES)))
- return ERROR_ESBC_CLIENT_HEADER_KEY_LEN;
-
- memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len);
-
- img->key_len = hdr->key_len;
-
+ ret = read_validate_single_key(img);
+ if (ret != 0)
+ return ret;
key_found = 1;
}
return *p != '\0' && *endptr == '\0';
}
+/* Function to calculate the ESBC Image Hash
+ * and hash from Digital signature.
+ * The Two hash's are compared to yield the
+ * result of signature validation.
+ */
+static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
+{
+ int ret;
+ uint32_t key_len;
+ struct key_prop prop;
+#if !defined(USE_HOSTCC)
+ struct udevice *mod_exp_dev;
+#endif
+ ret = calc_esbchdr_esbc_hash(img);
+ if (ret)
+ return ret;
+
+ /* Construct encoded hash EM' wrt PKCSv1.5 */
+ construct_img_encoded_hash_second(img);
+
+ /* Fill prop structure for public key */
+ memset(&prop, 0, sizeof(struct key_prop));
+ key_len = get_key_len(img) / 2;
+ prop.modulus = img->img_key;
+ prop.public_exponent = img->img_key + key_len;
+ prop.num_bits = key_len * 8;
+ prop.exp_len = key_len;
+
+ ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
+ if (ret) {
+ printf("RSA: Can't find Modular Exp implementation\n");
+ return -EINVAL;
+ }
+
+ ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
+ &prop, img->img_encoded_hash);
+ if (ret)
+ return ret;
+
+ /*
+ * compare the encoded messages EM' and EM wrt RSA PKCSv1.5
+ * memcmp returns zero on success
+ * memcmp returns non-zero on failure
+ */
+ ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash,
+ img->hdr.sign_len);
-int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+ if (ret)
+ return ERROR_ESBC_CLIENT_HASH_COMPARE_EM;
+
+ return 0;
+}
+
+int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
+ uintptr_t img_addr)
{
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
char hash_str[NUM_HEX_CHARS + 1];
- ulong addr = simple_strtoul(argv[1], NULL, 16);
struct fsl_secboot_img_priv *img;
struct fsl_secboot_img_hdr *hdr;
void *esbc;
int ret, i, hash_cmd = 0;
u32 srk_hash[8];
- uint32_t key_len;
- struct key_prop prop;
-#if !defined(USE_HOSTCC)
- struct udevice *mod_exp_dev;
-#endif
- if (argc == 3) {
- char *cp = argv[2];
+ if (arg_hash_str != NULL) {
+ const char *cp = arg_hash_str;
int i = 0;
if (*cp == '0' && *(cp + 1) == 'x')
*/
if (strlen(cp) != SHA256_NIBBLES) {
printf("%s is not a 256 bits hex string as expected\n",
- argv[2]);
+ arg_hash_str);
return -1;
}
hash_str[NUM_HEX_CHARS] = '\0';
if (!str2longbe(hash_str, &hash[i])) {
printf("%s is not a 256 bits hex string ",
- argv[2]);
+ arg_hash_str);
return -1;
}
}
memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+ /* Update the information in Private Struct */
hdr = &img->hdr;
- img->ehdrloc = addr;
- esbc = (u8 *)(uintptr_t)img->ehdrloc;
+ img->ehdrloc = haddr;
+ img->img_addr = img_addr;
+ esbc = (u8 *)img->ehdrloc;
memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
goto exit;
}
- ret = calc_esbchdr_esbc_hash(img);
+ ret = calculate_cmp_img_sig(img);
if (ret) {
- fsl_secblk_handle_error(ret);
- goto exit;
- }
-
- /* Construct encoded hash EM' wrt PKCSv1.5 */
- construct_img_encoded_hash_second(img);
-
- /* Fill prop structure for public key */
- memset(&prop, 0, sizeof(struct key_prop));
- key_len = get_key_len(img) / 2;
- prop.modulus = img->img_key;
- prop.public_exponent = img->img_key + key_len;
- prop.num_bits = key_len * 8;
- prop.exp_len = key_len;
-
- ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
- if (ret) {
- printf("RSA: Can't find Modular Exp implementation\n");
- return -EINVAL;
- }
-
- ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
- &prop, img->img_encoded_hash);
- if (ret) {
- fsl_secblk_handle_error(ret);
- goto exit;
- }
-
- /*
- * compare the encoded messages EM' and EM wrt RSA PKCSv1.5
- * memcmp returns zero on success
- * memcmp returns non-zero on failure
- */
- ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash,
- img->hdr.sign_len);
-
- if (ret) {
- fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_EM);
+ fsl_secboot_handle_error(ret);
goto exit;
}
- printf("esbc_validate command successful\n");
-
exit:
- return 0;
+ return ret;
}
QIXIS_WRITE(rcfg_ctl, 0x21);
#else
printf("Not implemented\n");
+#endif
+ } else if (strcmp(argv[1], "sd") == 0) {
+#ifdef QIXIS_LBMAP_SD
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_SD);
+ set_rcw_src(QIXIS_RCW_SRC_SD);
+ QIXIS_WRITE(rcfg_ctl, 0x20);
+ QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+ printf("Not implemented\n");
+#endif
+ } else if (strcmp(argv[1], "sd_qspi") == 0) {
+#ifdef QIXIS_LBMAP_SD_QSPI
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_SD_QSPI);
+ set_rcw_src(QIXIS_RCW_SRC_SD);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+#else
+ printf("Not implemented\n");
+#endif
+ } else if (strcmp(argv[1], "qspi") == 0) {
+#ifdef QIXIS_LBMAP_QSPI
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_QSPI);
+ set_rcw_src(QIXIS_RCW_SRC_QSPI);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+#else
+ printf("Not implemented\n");
#endif
} else if (strcmp(argv[1], "watchdog") == 0) {
static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
"- hard reset to default bank\n"
"qixis_reset altbank - reset to alternate bank\n"
"qixis_reset nand - reset to nand\n"
+ "qixis_reset sd - reset to sd\n"
+ "qixis_reset sd_qspi - reset to sd with qspi support\n"
+ "qixis_reset qspi - reset to qspi\n"
"qixis watchdog <watchdog_period> - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
"qixis_reset dump - display the QIXIS registers\n"
#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
+#include <fsl_validate.h>
#include "../common/sleep.h"
#include "../common/qixis.h"
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#endif
+#include <fsl_validate.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
F: configs/ls1043aqds_nor_ddr3_defconfig
F: configs/ls1043aqds_nand_defconfig
F: configs/ls1043aqds_sdcard_ifc_defconfig
+F: configs/ls1043aqds_sdcard_qspi_defconfig
+F: configs/ls1043aqds_qspi_defconfig
b) NOR boot
c) NAND boot
d) SD boot
+e) QSPI boot
* The address needs to add the offset of its bank.
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->secure_ram = gd->bd->bi_dram[1].start +
+ gd->secure_ram -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+ }
}
#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK 0x6
+#define CFG_UART_MUX_SHIFT 1
+#define CFG_LPUART_EN 0x1
int checkboard(void)
{
char buf[64];
-#ifndef CONFIG_SD_BOOT
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
u8 sw;
#endif
#ifdef CONFIG_SD_BOOT
puts("SD\n");
+#elif defined(CONFIG_QSPI_BOOT)
+ puts("QSPI\n");
#else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
int board_early_init_f(void)
{
+#ifdef CONFIG_LPUART
+ u8 uart;
+#endif
fsl_lsch2_early_init_f();
+#ifdef CONFIG_LPUART
+ /* We use lpuart0 as system console */
+ uart = QIXIS_READ(brdcfg[14]);
+ uart &= ~CFG_UART_MUX_MASK;
+ uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+ QIXIS_WRITE(brdcfg[14], uart);
+#endif
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ /* fixup DT for the two DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable QSPI; disable IFC
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
+00000000 00000000 00000000 00038800
+20124000 00001100 00000096 00000001
#include <common.h>
#include <config.h>
#include <fdtdec.h>
-#include <netdev.h>
#include <asm/processor.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
static int reset_pin = -1;
#endif
-#if CONFIG_IS_ENABLED(OF_CONTROL)
ulong ram_base;
void dram_init_banksize(void)
return 0;
};
-#else
-int dram_init(void)
-{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
-#endif
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return 0;
}
-int gpio_init (void)
+static int gpio_init(void)
{
#ifdef CONFIG_XILINX_GPIO
reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
return 0;
}
-void board_init(void)
+int board_late_init(void)
{
gpio_init();
-}
-int board_eth_init(bd_t *bis)
-{
- int ret = 0;
-
-#ifdef CONFIG_XILINX_AXIEMAC
- ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
- XILINX_AXIDMA_BASEADDR);
-#endif
-
-#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR)
- u32 txpp = 0;
- u32 rxpp = 0;
-# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- txpp = 1;
-# endif
-# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- rxpp = 1;
-# endif
- ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
- txpp, rxpp);
-#endif
-
- return ret;
+ return 0;
}
#define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 0
-/* Uart pheriphery is RS232_Uart */
-#define XILINX_UARTLITE_BASEADDR 0x40600000
-#define XILINX_UARTLITE_BAUDRATE 115200
-
-/* IIC pheriphery is IIC_EEPROM */
-#define XILINX_IIC_0_BASEADDR 0x40800000
-#define XILINX_IIC_0_FREQ 100000
-#define XILINX_IIC_0_BIT 0
-
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
#define XILINX_FLASH_START 0x2c000000
#define XILINX_FLASH_SIZE 0x00800000
-/* Main Memory is DDR_SDRAM_64Mx32 */
-#define XILINX_RAM_START 0x28000000
-#define XILINX_RAM_SIZE 0x04000000
-
-/* Sysace Controller is SysACE_CompactFlash */
-#define XILINX_SYSACE_BASEADDR 0x41800000
-#define XILINX_SYSACE_HIGHADDR 0x4180ffff
-#define XILINX_SYSACE_MEM_WIDTH 16
-
-/* Ethernet controller is Ethernet_MAC */
-#define XILINX_EMACLITE_BASEADDR 0x40C00000
-
/* Watchdog IP is wxi_timebase_wdt_0 */
#define XILINX_WATCHDOG_BASEADDR 0x50000000
#define XILINX_WATCHDOG_IRQ 1
+++ /dev/null
-if TARGET_ML507
-
-config SYS_BOARD
- default "ml507"
-
-config SYS_VENDOR
- default "xilinx"
-
-config SYS_CONFIG_NAME
- default "ml507"
-
-endif
+++ /dev/null
-ML507 BOARD
-M: Ricardo Ribalda <ricardo.ribalda@uam.es>
-S: Maintained
-F: board/xilinx/ml507/
-F: include/configs/ml507.h
-F: configs/ml507_defconfig
-F: configs/ml507_flash_defconfig
+++ /dev/null
-#
-# (C) Copyright 2008
-# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
-# This work has been supported by: Qtechnology http://qtec.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ml507.o
-
-include $(srctree)/board/xilinx/ppc440-generic/Makefile
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com/
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-
-int checkboard(void)
-{
- puts("Xilinx ML507 Board\n");
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com/
- * based on xparameters-ml507.h by Xilinx
- *
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef XPARAMETER_H
-#define XPARAMETER_H
-
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
-#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
-#define XPAR_INTC_0_BASEADDR 0x81800000
-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
-#define XPAR_UARTLITE_0_BAUDRATE 9600
-
-#endif
PPC405-GENERIC BOARD
-M: Ricardo Ribalda <ricardo.ribalda@uam.es>
+M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
S: Maintained
F: board/xilinx/ppc405-generic/
F: include/configs/xilinx-ppc405-generic.h
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
# Work supported by Qtechnology http://www.qtec.com
#
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
+obj-y += xilinx_ppc405_generic.o
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/processor.h>
-ulong __get_PCI_freq(void)
+ulong get_PCI_freq(void)
{
return 0;
}
-ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq")));
-
-int __board_pre_init(void)
-{
- return 0;
-}
-int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
-
-int __checkboard(void)
+int checkboard(void)
{
puts("Xilinx PPC405 Generic Board\n");
return 0;
}
-int checkboard(void) __attribute__((weak, alias("__checkboard")));
-phys_size_t __initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
}
-phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
-void __get_sys_info(sys_info_t *sysInfo)
+void get_sys_info(sys_info_t *sys_info)
{
- sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
- sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
- sysInfo->freqPCI = 0;
+ sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+ sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+ sys_info->freqPCI = 0;
return;
}
-void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
+
+int get_serial_clock(void){
+ return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_SPI_0_BASEADDR 0x83400000
-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
-#define XPAR_UARTLITE_0_BAUDRATE 9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif
PPC440-GENERIC BOARD
-M: Ricardo Ribalda <ricardo.ribalda@uam.es>
+M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
S: Maintained
F: board/xilinx/ppc440-generic/
F: include/configs/xilinx-ppc440-generic.h
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
# Work supported by Qtechnology http://www.qtec.com
#
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
-extra-y += ../../xilinx/ppc440-generic/init.o
+obj-y += xilinx_ppc440_generic.o
+extra-y += init.o
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+
#include <config.h>
#include <common.h>
+#include <netdev.h>
#include <asm/processor.h>
-int __board_pre_init(void)
-{
- return 0;
-}
-int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
-
-int __checkboard(void)
+int checkboard(void)
{
puts("Xilinx PPC440 Generic Board\n");
return 0;
}
-int checkboard(void) __attribute__((weak, alias("__checkboard")));
-phys_size_t __initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
}
-phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
-void __get_sys_info(sys_info_t *sysInfo)
+void get_sys_info(sys_info_t *sys_info)
{
- sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
- sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
- sysInfo->freqPCI = 0;
+ sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+ sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+ sys_info->freqPCI = 0;
return;
}
-void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
+
+int get_serial_clock(void){
+ return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+ puts("Init xilinx temac\n");
+#ifdef XPAR_LLTEMAC_0_BASEADDR
+ ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
+ XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
+ XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
+
+#endif
+
+#ifdef XPAR_LLTEMAC_1_BASEADDR
+ ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
+ XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
+ XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
+#endif
+
+ return ret;
+}
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
-#define XPAR_INTC_0_BASEADDR 0x81800000
-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
+#define XPAR_INTC_0_BASEADDR 0x87000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
-#define XPAR_UARTLITE_0_BAUDRATE 9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
+#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
+#define XPAR_LLTEMAC_0_BASEADDR 0x83000000
+#define XPAR_LLTEMAC_1_BASEADDR 0x83000040
#endif
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
-#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
- puts("Board:\tXilinx Zynq\n");
+ puts("Board: Xilinx Zynq\n");
return 0;
}
#endif
-int board_eth_init(bd_t *bis)
-{
- u32 ret = 0;
-
-#ifdef CONFIG_XILINX_AXIEMAC
- ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
- XILINX_AXIDMA_BASEADDR);
-#endif
-#ifdef CONFIG_XILINX_EMACLITE
- u32 txpp = 0;
- u32 rxpp = 0;
-# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- txpp = 1;
-# endif
-# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- rxpp = 1;
-# endif
- ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
- txpp, rxpp);
-#endif
- return ret;
-}
-
int dram_init(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
#include <netdev.h>
#include <ahci.h>
#include <scsi.h>
+#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
{
u32 val;
- val = readl(&crlapb_base->timestamp_ref_ctrl);
- val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
- writel(val, &crlapb_base->timestamp_ref_ctrl);
-
+ if (current_el() == 3) {
+ val = readl(&crlapb_base->timestamp_ref_ctrl);
+ val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+ writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+ /* Program freq register in System counter */
+ writel(zynqmp_get_system_timer_freq(),
+ &iou_scntr_secure->base_frequency_id_register);
+ /* And enable system counter */
+ writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+ &iou_scntr_secure->counter_control_register);
+ }
/* Program freq register in System counter and enable system counter */
writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
return 0;
}
-int timer_init(void)
-{
- return 0;
-}
-
void reset_cpu(ulong addr)
{
}
reg = readl(&crlapb_base->boot_mode);
bootmode = reg & BOOT_MODES_MASK;
+ puts("Bootmode: ");
switch (bootmode) {
- case SD_MODE:
+ case JTAG_MODE:
+ puts("JTAG_MODE\n");
+ setenv("modeboot", "jtagboot");
+ break;
+ case QSPI_MODE_24BIT:
+ case QSPI_MODE_32BIT:
+ setenv("modeboot", "qspiboot");
+ puts("QSPI_MODE\n");
+ break;
case EMMC_MODE:
+ puts("EMMC_MODE\n");
+ setenv("modeboot", "sdboot");
+ break;
+ case SD_MODE:
+ puts("SD_MODE\n");
setenv("modeboot", "sdboot");
break;
+ case SD_MODE1:
+ puts("SD_MODE1\n");
+#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
+ setenv("sdbootdev", "1");
+#endif
+ setenv("modeboot", "sdboot");
+ break;
+ case NAND_MODE:
+ puts("NAND_MODE\n");
+ setenv("modeboot", "nandboot");
+ break;
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
int checkboard(void)
{
- puts("Board:\tXilinx ZynqMP\n");
+ puts("Board: Xilinx ZynqMP\n");
return 0;
}
print_num("sram start ", (ulong)bd->bi_sramstart);
print_num("sram size ", (ulong)bd->bi_sramsize);
#endif
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
print_eths();
#endif
printf("baudrate = %u bps\n", gd->baudrate);
debug("* fpga: cmdline image address = 0x%08lx\n",
(ulong)fpga_data);
}
- debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
+ debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
case 3: /* fpga <op> <dev | data addr> */
dev = (int)simple_strtoul(argv[2], NULL, 16);
} else
#endif
{
- fpga_data = (void *)dev;
+ fpga_data = (void *)(uintptr_t)dev;
debug("* fpga: cmdline image addr = 0x%08lx\n",
(ulong)fpga_data);
}
- debug("%s: fpga_data = 0x%x\n",
- __func__, (uint)fpga_data);
+ debug("%s: fpga_data = 0x%lx\n",
+ __func__, (ulong)fpga_data);
dev = FPGA_INVALID_DEVICE; /* reset device num */
}
#include <spi_flash.h>
#include <search.h>
#include <errno.h>
+#include <dm/device-internal.h>
#ifndef CONFIG_ENV_SPI_BUS
# define CONFIG_ENV_SPI_BUS 0
char *saved_buffer = NULL, flag = OBSOLETE_FLAG;
u32 saved_size, saved_offset, sector = 1;
int ret;
+#ifdef CONFIG_DM_SPI_FLASH
+ struct udevice *new;
+
+ ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ,
+ CONFIG_ENV_SPI_MODE, &new);
+ if (ret) {
+ set_default_env("!spi_flash_probe_bus_cs() failed");
+ return 1;
+ }
+
+ env_flash = dev_get_uclass_priv(new);
+#else
if (!env_flash) {
env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
return 1;
}
}
+#endif
ret = env_export(&env_new);
if (ret)
char *saved_buffer = NULL;
int ret = 1;
env_t env_new;
+#ifdef CONFIG_DM_SPI_FLASH
+ struct udevice *new;
+
+ ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ,
+ CONFIG_ENV_SPI_MODE, &new);
+ if (ret) {
+ set_default_env("!spi_flash_probe_bus_cs() failed");
+ return 1;
+ }
+
+ env_flash = dev_get_uclass_priv(new);
+#else
if (!env_flash) {
env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
return 1;
}
}
+#endif
/* Is the sector larger than the env (i.e. embedded) */
if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) {
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_FX12MM=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o"
-CONFIG_SYS_PROMPT="FX12MM:/# "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_FX12MM=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_FSL_LPUART=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_SYS_NS16550=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_SYS_NS16550=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
CONFIG_MICROBLAZE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_SYS_TEXT_BASE=0x29000000
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot-mONStR> "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM_ETH=y
+CONFIG_XILINX_AXIEMAC=y
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_XILINX_UARTLITE=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_ML507=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o"
-CONFIG_SYS_PROMPT="ml507:/# "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_ML507=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_V5FX30TEVAL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o"
-CONFIG_SYS_PROMPT="v5fx30t:/# "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_V5FX30TEVAL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_MALLOC_SIMPLE=y
+CONFIG_XILINX_UARTLITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_EMBED=y
+CONFIG_OF_CONTROL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_XILINX_PPC405_GENERIC=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
CONFIG_SYS_PROMPT="board:/# "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+CONFIG_SYS_MALLOC_SIMPLE=y
+CONFIG_XILINX_UARTLITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_EMBED=y
+CONFIG_OF_CONTROL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NETCONSOLE=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_XILINX_PPC440_GENERIC=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_TARGET_ZYNQ_PICOZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_ZYNQ_GEM=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ZYNQ_QSPI=y
--- /dev/null
+Binding for Xilinx Uartlite Controller
+
+Required properties:
+- compatible : should be "xlnx,xps-uartlite-1.00.a", or "xlnx,opb-uartlite-1.00.b"
+- reg: Should contain UART controller registers location and length.
+- interrupts: Should contain UART controller interrupts.
+
+Example:
+ serial@40600000 {
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ interrupts = <1 0>;
+ reg = <0x40600000 0x10000>;
+ };
serial_pxa.c
serial_s3c24x0.c
serial_sa1100.c
- serial_xuartlite.c
usbtty.c
You should complete this by the end of January 2016.
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
u32 *vref_seq = vref_seq1;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+ ulong ddr_freq;
+ u32 tmp;
+#endif
#ifdef CONFIG_FSL_DDR_BIST
u32 mtcr, err_detect, err_sbe;
u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
+ ddr_out32(&ddr->sdram_interval,
+ regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
+#else
ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+#endif
ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
#ifndef CONFIG_SYS_FSL_DDR_EMU
ddr_out32(&ddr->debug[25], 0x9000);
}
#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+ tmp = ddr_in32(&ddr->debug[28]);
+ if (ddr_freq <= 1333)
+ ddr_out32(&ddr->debug[28], tmp | 0x0080006a);
+ else if (ddr_freq <= 1600)
+ ddr_out32(&ddr->debug[28], tmp | 0x0070006f);
+ else if (ddr_freq <= 1867)
+ ddr_out32(&ddr->debug[28], tmp | 0x00700076);
+ else if (ddr_freq <= 2133)
+ ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
+#endif
+
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
* deasserted. Clocks start when any chip select is enabled and clock
if (timeout <= 0)
printf("Waiting for D_INIT timeout. Memory may not work.\n");
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
+ ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+#endif
+
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
/* exit self-refresh */
info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
info.board_need_mem_reset = NULL;
+ remove_unused_controllers(&info);
/* Compute it once normally. */
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
buffer[i] = *dataptr++;
if (xdesc->name) {
- i = strncmp(buffer, xdesc->name, strlen(xdesc->name));
- if (i) {
+ i = (ulong)strstr(buffer, xdesc->name);
+ if (!i) {
printf("%s: Wrong bitstream ID for this device\n",
__func__);
printf("%s: Bitstream ID %s, current device ID %d/%s\n",
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
- defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \
- defined(CONFIG_PPC_T4160)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
-#endif
+
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}
* Rounding up to next power of 2
* => timeout + 13 = log2(mmc->clock/4) + 1
* => timeout + 13 = fls(mmc->clock/4)
+ *
+ * However, the MMC spec "It is strongly recommended for hosts to
+ * implement more than 500ms timeout value even if the card
+ * indicates the 250ms maximum busy length." Even the previous
+ * value of 300ms is known to be insufficient for some cards.
+ * So, we use
+ * => timeout + 13 = fls(mmc->clock/2)
*/
- timeout = fls(mmc->clock/4);
+ timeout = fls(mmc->clock/2);
timeout -= 13;
if (timeout > 14)
if (caps & SDHCI_CAN_DO_8BIT)
host->cfg.host_caps |= MMC_MODE_8BIT;
}
+
+ if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
+ host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
+
if (host->host_caps)
host->cfg.host_caps |= host->host_caps;
#include <malloc.h>
#include <sdhci.h>
+#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
+# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
+#endif
+
static int arasan_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_BROKEN_R1B;
+
+#ifdef CONFIG_ZYNQ_HISPD_BROKEN
+ host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+#endif
+
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
- add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0);
+ add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
+ CONFIG_ZYNQ_SDHCI_MIN_FREQ);
upriv->mmc = host->mmc;
This MAC is present in Intel Platform Controller Hub EG20T. It
supports 10/100/1000 Mbps operation.
+config XILINX_AXIEMAC
+ depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ select PHYLIB
+ select MII
+ bool "Xilinx AXI Ethernet"
+ help
+ This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
+
+config XILINX_EMACLITE
+ depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ select PHYLIB
+ select MII
+ bool "Xilinx Ethernetlite"
+ help
+ This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
+
config ZYNQ_GEM
depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
void *qbman_swp_mc_start(struct qbman_swp *p)
{
void *ret;
+ int *return_val;
#ifdef QBMAN_CHECKING
BUG_ON(p->mc.check != swp_mc_can_start);
#endif
ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR);
#ifdef QBMAN_CHECKING
- if (!ret)
+ return_val = (int *)ret;
+ if (!(*return_val))
p->mc.check = swp_mc_can_submit;
#endif
return ret;
#include <fsl-mc/fsl_mc_cmd.h>
#include <fsl-mc/fsl_dpni.h>
+int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg,
+ uint8_t *ext_cfg_buf)
+{
+ uint64_t *ext_params = (uint64_t *)ext_cfg_buf;
+
+ DPNI_PREP_EXTENDED_CFG(ext_params, cfg);
+
+ return 0;
+}
+
+int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg,
+ const uint8_t *ext_cfg_buf)
+{
+ uint64_t *ext_params = (uint64_t *)ext_cfg_buf;
+
+ DPNI_EXT_EXTENDED_CFG(ext_params, cfg);
+
+ return 0;
+}
+
int dpni_open(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
int dpni_id,
cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR,
cmd_flags,
token);
+ DPNI_CMD_GET_ATTR(cmd, attr);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
return 0;
}
+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpni_error_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
return 0;
}
+
+int dpni_set_tx_conf(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint16_t flow_id,
+ const struct dpni_tx_conf_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_tx_conf(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint16_t flow_id,
+ struct dpni_tx_conf_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF,
+ cmd_flags,
+ token);
+ DPNI_CMD_GET_TX_CONF(cmd, flow_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ DPNI_RSP_GET_TX_CONF(cmd, attr);
+
+ return 0;
+}
return 0;
}
+static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle)
+{
+ struct dprc_attributes attr;
+ int error;
+
+ memset(&attr, 0, sizeof(struct dprc_attributes));
+ error = dprc_get_attributes(mc_io, MC_CMD_NO_FLAGS, handle, &attr);
+ if (error == 0) {
+ if ((attr.version.major != DPRC_VER_MAJOR) ||
+ (attr.version.minor != DPRC_VER_MINOR)) {
+ printf("DPRC version mismatch found %u.%u,",
+ attr.version.major,
+ attr.version.minor);
+ printf("supported version is %u.%u\n",
+ DPRC_VER_MAJOR, DPRC_VER_MINOR);
+ }
+ }
+ return error;
+}
+
static int dpio_init(void)
{
struct qbman_swp_desc p_des;
goto err_get_attr;
}
+ if ((attr.version.major != DPIO_VER_MAJOR) ||
+ (attr.version.minor != DPIO_VER_MINOR)) {
+ printf("DPIO version mismatch found %u.%u,",
+ attr.version.major, attr.version.minor);
+ printf("supported version is %u.%u\n",
+ DPIO_VER_MAJOR, DPIO_VER_MINOR);
+ }
+
dflt_dpio->dpio_id = attr.id;
#ifdef DEBUG
printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
#endif
-
err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
if (err < 0) {
printf("dpio_enable() failed %d\n", err);
goto err_root_open;
}
+ err = dprc_version_check(root_mc_io, root_dprc_handle);
+ if (err < 0) {
+ printf("dprc_version_check() failed: %d\n", err);
+ goto err_root_open;
+ }
+
cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
DPRC_CFG_OPT_ALLOC_ALLOWED;
cfg.icid = DPRC_GET_ICID_FROM_POOL;
- cfg.portal_id = 250;
+ cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL;
err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
root_dprc_handle,
&cfg,
goto err_get_attr;
}
+ if ((dpbp_attr.version.major != DPBP_VER_MAJOR) ||
+ (dpbp_attr.version.minor != DPBP_VER_MINOR)) {
+ printf("DPBP version mismatch found %u.%u,",
+ dpbp_attr.version.major, dpbp_attr.version.minor);
+ printf("supported version is %u.%u\n",
+ DPBP_VER_MAJOR, DPBP_VER_MINOR);
+ }
+
dflt_dpbp->dpbp_attr.id = dpbp_attr.id;
#ifdef DEBUG
printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
{
int err;
struct dpni_attr dpni_attr;
+ uint8_t ext_cfg_buf[256] = {0};
+ struct dpni_extended_cfg dpni_extended_cfg;
struct dpni_cfg dpni_cfg;
dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
goto err_malloc;
}
+ memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg));
+ err = dpni_prepare_extended_cfg(&dpni_extended_cfg, &ext_cfg_buf[0]);
+ if (err < 0) {
+ err = -ENODEV;
+ printf("dpni_prepare_extended_cfg() failed: %d\n", err);
+ goto err_prepare_extended_cfg;
+ }
+
memset(&dpni_cfg, 0, sizeof(dpni_cfg));
dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER |
DPNI_OPT_MULTICAST_FILTER;
+ dpni_cfg.adv.ext_cfg_iova = (uint64_t)&ext_cfg_buf[0];
err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg,
&dflt_dpni->dpni_handle);
goto err_get_attr;
}
+ if ((dpni_attr.version.major != DPNI_VER_MAJOR) ||
+ (dpni_attr.version.minor != DPNI_VER_MINOR)) {
+ printf("DPNI version mismatch found %u.%u,",
+ dpni_attr.version.major, dpni_attr.version.minor);
+ printf("supported version is %u.%u\n",
+ DPNI_VER_MAJOR, DPNI_VER_MINOR);
+ }
+
dflt_dpni->dpni_id = dpni_attr.id;
#ifdef DEBUG
printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
return 0;
err_close:
- free(dflt_dpni);
err_get_attr:
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_create:
+err_prepare_extended_cfg:
+ free(dflt_dpni);
err_malloc:
return err;
}
}
printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value);
}
+
+static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev)
+{
+ struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
+ int err = 0;
+ u64 value;
+
+ err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle,
+ DPMAC_CNT_ING_BYTE,
+ &value);
+ if (err < 0) {
+ printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n");
+ return;
+ }
+ printf("DPMAC_CNT_ING_BYTE=%lld\n", value);
+
+ err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle,
+ DPMAC_CNT_ING_FRAME_DISCARD,
+ &value);
+ if (err < 0) {
+ printf("dpmac_get_counter: DPMAC_CNT_ING_FRAME_DISCARD failed\n");
+ return;
+ }
+ printf("DPMAC_CNT_ING_FRAME_DISCARD=%lld\n", value);
+
+ err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle,
+ DPMAC_CNT_ING_ALIGN_ERR,
+ &value);
+ if (err < 0) {
+ printf("dpmac_get_counter: DPMAC_CNT_ING_ALIGN_ERR failed\n");
+ return;
+ }
+ printf("DPMAC_CNT_ING_ALIGN_ERR =%lld\n", value);
+
+ err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle,
+ DPMAC_CNT_ING_BYTE,
+ &value);
+ if (err < 0) {
+ printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n");
+ return;
+ }
+ printf("DPMAC_CNT_ING_BYTE=%lld\n", value);
+
+ err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle,
+ DPMAC_CNT_ING_ERR_FRAME,
+ &value);
+ if (err < 0) {
+ printf("dpmac_get_counter: DPMAC_CNT_ING_ERR_FRAME failed\n");
+ return;
+ }
+ printf("DPMAC_CNT_ING_ERR_FRAME=%lld\n", value);
+
+ err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle,
+ DPMAC_CNT_EGR_BYTE ,
+ &value);
+ if (err < 0) {
+ printf("dpmac_get_counter: DPMAC_CNT_EGR_BYTE failed\n");
+ return;
+ }
+ printf("DPMAC_CNT_EGR_BYTE =%lld\n", value);
+
+ err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle,
+ DPMAC_CNT_EGR_ERR_FRAME ,
+ &value);
+ if (err < 0) {
+ printf("dpmac_get_counter: DPMAC_CNT_EGR_ERR_FRAME failed\n");
+ return;
+ }
+ printf("DPMAC_CNT_EGR_ERR_FRAME =%lld\n", value);
+}
#endif
static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
#ifdef DEBUG
ldpaa_eth_get_dpni_counter();
+ ldpaa_eth_get_dpmac_counter(net_dev);
#endif
err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
}
+static int ldpaa_dpmac_version_check(struct fsl_mc_io *mc_io,
+ struct ldpaa_eth_priv *priv)
+{
+ struct dpmac_attr attr;
+ int error;
+
+ memset(&attr, 0, sizeof(struct dpmac_attr));
+ error = dpmac_get_attributes(mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle,
+ &attr);
+ if (error == 0) {
+ if ((attr.version.major != DPMAC_VER_MAJOR) ||
+ (attr.version.minor != DPMAC_VER_MINOR)) {
+ printf("DPMAC version mismatch found %u.%u,",
+ attr.version.major, attr.version.minor);
+ printf("supported version is %u.%u\n",
+ DPMAC_VER_MAJOR, DPMAC_VER_MINOR);
+ }
+ }
+
+ return error;
+}
+
static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv)
{
int err = 0;
&priv->dpmac_handle);
if (err)
printf("dpmac_create() failed\n");
+
+ err = ldpaa_dpmac_version_check(dflt_mc_io, priv);
+ if (err < 0)
+ printf("ldpaa_dpmac_version_check() failed: %d\n", err);
+
return err;
}
{
struct dpni_pools_cfg pools_params;
struct dpni_tx_flow_cfg dflt_tx_flow;
+ struct dpni_tx_conf_cfg tx_conf_cfg;
int err = 0;
pools_params.num_dpbp = 1;
priv->tx_flow_id = DPNI_NEW_FLOW_ID;
memset(&dflt_tx_flow, 0, sizeof(dflt_tx_flow));
- dflt_tx_flow.options = DPNI_TX_FLOW_OPT_ONLY_TX_ERROR;
- dflt_tx_flow.conf_err_cfg.use_default_queue = 0;
- dflt_tx_flow.conf_err_cfg.errors_only = 1;
+ dflt_tx_flow.use_common_tx_conf_queue = 0;
err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, &priv->tx_flow_id,
&dflt_tx_flow);
return err;
}
+ memset(&tx_conf_cfg, 0, sizeof(struct dpni_tx_conf_cfg));
+ tx_conf_cfg.errors_only = true;
+ /*Set tx-conf and error configuration*/
+ err = dpni_set_tx_conf(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ priv->tx_flow_id, &tx_conf_cfg);
+ if (err) {
+ printf("dpni_set_tx_conf() failed\n");
+ return err;
+ }
+
return 0;
}
};
/* Arbitrary values for now, but we'll need to tune */
-#define LDPAA_ETH_NUM_BUFS (2 * 7)
+#define LDPAA_ETH_NUM_BUFS (7 * 7)
#define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2)
#define LDPAA_ETH_RX_BUFFER_SIZE 2048
/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
+#define DP83867_MDI_CROSSOVER 5
+#define DP83867_MDI_CROSSOVER_AUTO 2
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
+ (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
return ret;
#include <config.h>
#include <common.h>
+#include <dm.h>
#include <net.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
-#if !defined(CONFIG_PHYLIB)
-# error AXI_ETHERNET requires PHYLIB
-#endif
+DECLARE_GLOBAL_DATA_PTR;
/* Link setup */
#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
struct axidma_reg *dmatx;
struct axidma_reg *dmarx;
int phyaddr;
-
+ struct axi_regs *iobase;
+ phy_interface_t interface;
struct phy_device *phydev;
struct mii_dev *bus;
};
*/
#define PHY_DETECT_MASK 0x1808
-static inline int mdio_wait(struct eth_device *dev)
+static inline int mdio_wait(struct axi_regs *regs)
{
- struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 timeout = 200;
/* Wait till MDIO interface is ready to accept a new transaction. */
return 0;
}
-static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
- u16 *val)
+static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
+ u16 *val)
{
- struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+ struct axi_regs *regs = priv->iobase;
u32 mdioctrlreg = 0;
- if (mdio_wait(dev))
+ if (mdio_wait(regs))
return 1;
mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
out_be32(®s->mdio_mcr, mdioctrlreg);
- if (mdio_wait(dev))
+ if (mdio_wait(regs))
return 1;
/* Read data */
return 0;
}
-static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
- u32 data)
+static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
+ u32 data)
{
- struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+ struct axi_regs *regs = priv->iobase;
u32 mdioctrlreg = 0;
- if (mdio_wait(dev))
+ if (mdio_wait(regs))
return 1;
mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
out_be32(®s->mdio_mcr, mdioctrlreg);
- if (mdio_wait(dev))
+ if (mdio_wait(regs))
return 1;
return 0;
}
-/* Setting axi emac and phy to proper setting */
-static int setup_phy(struct eth_device *dev)
+static int axiemac_phy_init(struct udevice *dev)
{
u16 phyreg;
- u32 i, speed, emmc_reg, ret;
- struct axidma_priv *priv = dev->priv;
- struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+ u32 i, ret;
+ struct axidma_priv *priv = dev_get_priv(dev);
+ struct axi_regs *regs = priv->iobase;
struct phy_device *phydev;
u32 supported = SUPPORTED_10baseT_Half |
SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
+ /* Set default MDIO divisor */
+ out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
+
if (priv->phyaddr == -1) {
/* Detect the PHY address */
for (i = 31; i >= 0; i--) {
- ret = phyread(dev, i, PHY_DETECT_REG, &phyreg);
+ ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
if (!ret && (phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
priv->phyaddr = i;
debug("axiemac: Found valid phy address, %x\n",
- phyreg);
+ i);
break;
}
}
phydev->advertising = phydev->supported;
priv->phydev = phydev;
phy_config(phydev);
+
+ return 0;
+}
+
+/* Setting axi emac and phy to proper setting */
+static int setup_phy(struct udevice *dev)
+{
+ u32 speed, emmc_reg;
+ struct axidma_priv *priv = dev_get_priv(dev);
+ struct axi_regs *regs = priv->iobase;
+ struct phy_device *phydev = priv->phydev;
+
if (phy_startup(phydev)) {
printf("axiemac: could not initialize PHY %s\n",
phydev->dev->name);
}
/* STOP DMA transfers */
-static void axiemac_halt(struct eth_device *dev)
+static void axiemac_stop(struct udevice *dev)
{
- struct axidma_priv *priv = dev->priv;
+ struct axidma_priv *priv = dev_get_priv(dev);
u32 temp;
/* Stop the hardware */
debug("axiemac: Halted\n");
}
-static int axi_ethernet_init(struct eth_device *dev)
+static int axi_ethernet_init(struct axidma_priv *priv)
{
- struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+ struct axi_regs *regs = priv->iobase;
u32 timeout = 200;
/*
return 0;
}
-static int axiemac_setup_mac(struct eth_device *dev)
+static int axiemac_write_hwaddr(struct udevice *dev)
{
- struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct axidma_priv *priv = dev_get_priv(dev);
+ struct axi_regs *regs = priv->iobase;
/* Set the MAC address */
- int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
- (dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
+ int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
+ (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
out_be32(®s->uaw0, val);
- val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ;
+ val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
out_be32(®s->uaw1, val);
return 0;
}
/* Reset DMA engine */
-static void axi_dma_init(struct eth_device *dev)
+static void axi_dma_init(struct axidma_priv *priv)
{
- struct axidma_priv *priv = dev->priv;
u32 timeout = 500;
/* Reset the engine so the hardware starts from a known state */
while (timeout--) {
/* Check transmit/receive channel */
/* Reset is done when the reset bit is low */
- if (!(in_be32(&priv->dmatx->control) |
+ if (!((in_be32(&priv->dmatx->control) |
in_be32(&priv->dmarx->control))
- & XAXIDMA_CR_RESET_MASK) {
+ & XAXIDMA_CR_RESET_MASK)) {
break;
}
}
printf("%s: Timeout\n", __func__);
}
-static int axiemac_init(struct eth_device *dev, bd_t * bis)
+static int axiemac_start(struct udevice *dev)
{
- struct axidma_priv *priv = dev->priv;
- struct axi_regs *regs = (struct axi_regs *)dev->iobase;
+ struct axidma_priv *priv = dev_get_priv(dev);
+ struct axi_regs *regs = priv->iobase;
u32 temp;
debug("axiemac: Init started\n");
* reset, and since AXIDMA reset line is connected to AxiEthernet, this
* would ensure a reset of AxiEthernet.
*/
- axi_dma_init(dev);
+ axi_dma_init(priv);
/* Initialize AxiEthernet hardware. */
- if (axi_ethernet_init(dev))
+ if (axi_ethernet_init(priv))
return -1;
/* Disable all RX interrupts before RxBD space setup */
/* PHY setup */
if (!setup_phy(dev)) {
- axiemac_halt(dev);
+ axiemac_stop(dev);
return -1;
}
return 0;
}
-static int axiemac_send(struct eth_device *dev, void *ptr, int len)
+static int axiemac_send(struct udevice *dev, void *ptr, int len)
{
- struct axidma_priv *priv = dev->priv;
+ struct axidma_priv *priv = dev_get_priv(dev);
u32 timeout;
if (len > PKTSIZE_ALIGN)
/* Wait for transmission to complete */
debug("axiemac: Waiting for tx to be done\n");
timeout = 200;
- while (timeout && (!in_be32(&priv->dmatx->status) &
- (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
+ while (timeout && (!(in_be32(&priv->dmatx->status) &
+ (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
timeout--;
udelay(1);
}
return 0;
}
-static int isrxready(struct eth_device *dev)
+static int isrxready(struct axidma_priv *priv)
{
u32 status;
- struct axidma_priv *priv = dev->priv;
/* Read pending interrupts */
status = in_be32(&priv->dmarx->status);
return 0;
}
-static int axiemac_recv(struct eth_device *dev)
+static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
{
u32 length;
- struct axidma_priv *priv = dev->priv;
+ struct axidma_priv *priv = dev_get_priv(dev);
u32 temp;
/* Wait for an incoming packet */
- if (!isrxready(dev))
- return 0;
+ if (!isrxready(priv))
+ return -1;
debug("axiemac: RX data ready\n");
#ifdef DEBUG
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
#endif
- /* Pass the received frame up for processing */
- if (length)
- net_process_received_packet(rxframe, length);
+
+ *packetp = rxframe;
+ return length;
+}
+
+static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct axidma_priv *priv = dev_get_priv(dev);
#ifdef DEBUG
/* It is useful to clear buffer to be sure that it is consistent */
debug("axiemac: RX completed, framelength = %d\n", length);
- return length;
+ return 0;
}
-static int axiemac_miiphy_read(const char *devname, uchar addr,
- uchar reg, ushort *val)
+static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
+ int devad, int reg)
{
- struct eth_device *dev = eth_get_dev();
- u32 ret;
+ int ret;
+ u16 value;
- ret = phyread(dev, addr, reg, val);
- debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
- return ret;
+ ret = phyread(bus->priv, addr, reg, &value);
+ debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
+ value, ret);
+ return value;
}
-static int axiemac_miiphy_write(const char *devname, uchar addr,
- uchar reg, ushort val)
+static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 value)
{
- struct eth_device *dev = eth_get_dev();
-
- debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
- return phywrite(dev, addr, reg, val);
+ debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
+ return phywrite(bus->priv, addr, reg, value);
}
-static int axiemac_bus_reset(struct mii_dev *bus)
+static int axi_emac_probe(struct udevice *dev)
{
- debug("axiemac: Bus reset\n");
+ struct axidma_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->bus = mdio_alloc();
+ priv->bus->read = axiemac_miiphy_read;
+ priv->bus->write = axiemac_miiphy_write;
+ priv->bus->priv = priv;
+ strcpy(priv->bus->name, "axi_emac");
+
+ ret = mdio_register(priv->bus);
+ if (ret)
+ return ret;
+
+ axiemac_phy_init(dev);
+
return 0;
}
-int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
- unsigned long dma_addr)
+static int axi_emac_remove(struct udevice *dev)
{
- struct eth_device *dev;
- struct axidma_priv *priv;
+ struct axidma_priv *priv = dev_get_priv(dev);
- dev = calloc(1, sizeof(struct eth_device));
- if (dev == NULL)
- return -1;
+ free(priv->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
- dev->priv = calloc(1, sizeof(struct axidma_priv));
- if (dev->priv == NULL) {
- free(dev);
- return -1;
- }
- priv = dev->priv;
+ return 0;
+}
- sprintf(dev->name, "aximac.%lx", base_addr);
+static const struct eth_ops axi_emac_ops = {
+ .start = axiemac_start,
+ .send = axiemac_send,
+ .recv = axiemac_recv,
+ .free_pkt = axiemac_free_pkt,
+ .stop = axiemac_stop,
+ .write_hwaddr = axiemac_write_hwaddr,
+};
- dev->iobase = base_addr;
- priv->dmatx = (struct axidma_reg *)dma_addr;
+static int axi_emac_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct axidma_priv *priv = dev_get_priv(dev);
+ int offset = 0;
+ const char *phy_mode;
+
+ pdata->iobase = (phys_addr_t)dev_get_addr(dev);
+ priv->iobase = (struct axi_regs *)pdata->iobase;
+
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ "axistream-connected");
+ if (offset <= 0) {
+ printf("%s: axistream is not found\n", __func__);
+ return -EINVAL;
+ }
+ priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
+ offset, "reg", 0);
+ if (!priv->dmatx) {
+ printf("%s: axi_dma register space not found\n", __func__);
+ return -EINVAL;
+ }
/* RX channel offset is 0x30 */
- priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
- dev->init = axiemac_init;
- dev->halt = axiemac_halt;
- dev->send = axiemac_send;
- dev->recv = axiemac_recv;
- dev->write_hwaddr = axiemac_setup_mac;
-
-#ifdef CONFIG_PHY_ADDR
- priv->phyaddr = CONFIG_PHY_ADDR;
-#else
+ priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
+
priv->phyaddr = -1;
-#endif
- eth_register(dev);
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ "phy-handle");
+ if (offset > 0)
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+
+ phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+ priv->interface = pdata->phy_interface;
+
+ printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
+ priv->phyaddr, phy_string_for_interface(priv->interface));
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
- miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
- priv->bus = miiphy_get_dev_by_name(dev->name);
- priv->bus->reset = axiemac_bus_reset;
-#endif
- return 1;
+ return 0;
}
+
+static const struct udevice_id axi_emac_ids[] = {
+ { .compatible = "xlnx,axi-ethernet-1.00.a" },
+ { }
+};
+
+U_BOOT_DRIVER(axi_emac) = {
+ .name = "axi_emac",
+ .id = UCLASS_ETH,
+ .of_match = axi_emac_ids,
+ .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
+ .probe = axi_emac_probe,
+ .remove = axi_emac_remove,
+ .ops = &axi_emac_ops,
+ .priv_auto_alloc_size = sizeof(struct axidma_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
#include <common.h>
#include <net.h>
#include <config.h>
+#include <dm.h>
+#include <console.h>
#include <malloc.h>
#include <asm/io.h>
+#include <phy.h>
+#include <miiphy.h>
#include <fdtdec.h>
+#include <asm-generic/errno.h>
+#include <linux/kernel.h>
-#undef DEBUG
+DECLARE_GLOBAL_DATA_PTR;
#define ENET_ADDR_LENGTH 6
-
-/* EmacLite constants */
-#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
-#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
-#define XEL_TSR_OFFSET 0x07FC /* Tx status */
-#define XEL_RSR_OFFSET 0x17FC /* Rx status */
-#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
+#define ETH_FCS_LEN 4 /* Octets in the FCS */
/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
-/* Buffer is active, SW bit only */
-#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK 0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
+/* MDIO Address Register Bit Masks */
+#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
+#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
+#define XEL_MDIOADDR_PHYADR_SHIFT 5
+#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
+
+/* MDIO Write Data Register Bit Masks */
+#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
+
+/* MDIO Read Data Register Bit Masks */
+#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
+
+/* MDIO Control Register Bit Masks */
+#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
+#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
+
+struct emaclite_regs {
+ u32 tx_ping; /* 0x0 - TX Ping buffer */
+ u32 reserved1[504];
+ u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
+ u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
+ u32 mdiord;/* 0x7ec - MDIO Read Data Register */
+ u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
+ u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
+ u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
+ u32 tx_ping_tsr; /* 0x7fc - Tx status */
+ u32 tx_pong; /* 0x800 - TX Pong buffer */
+ u32 reserved2[508];
+ u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
+ u32 reserved3; /* 0xff8 */
+ u32 tx_pong_tsr; /* 0xffc - Tx status */
+ u32 rx_ping; /* 0x1000 - Receive Buffer */
+ u32 reserved4[510];
+ u32 rx_ping_rsr; /* 0x17fc - Rx status */
+ u32 rx_pong; /* 0x1800 - Receive Buffer */
+ u32 reserved5[510];
+ u32 rx_pong_rsr; /* 0x1ffc - Rx status */
+};
+
struct xemaclite {
- u32 nexttxbuffertouse; /* Next TX buffer to write to */
- u32 nextrxbuffertouse; /* Next RX buffer to read from */
+ bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
u32 txpp; /* TX ping pong buffer */
u32 rxpp; /* RX ping pong buffer */
+ int phyaddr;
+ struct emaclite_regs *regs;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
};
-static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
+static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
*to8ptr++ = *from8ptr++;
}
-static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
+static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
{
u32 i;
u32 alignbuffer;
*to32ptr++ = alignbuffer;
}
-static void emaclite_halt(struct eth_device *dev)
+static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
+ bool set, unsigned int timeout)
+{
+ u32 val;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ val = readl(reg);
+
+ if (!set)
+ val = ~val;
+
+ if ((val & mask) == mask)
+ return 0;
+
+ if (get_timer(start) > timeout)
+ break;
+
+ if (ctrlc()) {
+ puts("Abort\n");
+ return -EINTR;
+ }
+
+ udelay(1);
+ }
+
+ debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
+ func, reg, mask, set);
+
+ return -ETIMEDOUT;
+}
+
+static int mdio_wait(struct emaclite_regs *regs)
{
- debug("eth_halt\n");
+ return wait_for_bit(__func__, ®s->mdioctrl,
+ XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
}
-static int emaclite_init(struct eth_device *dev, bd_t *bis)
+static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
+ u16 *data)
{
- struct xemaclite *emaclite = dev->priv;
+ struct emaclite_regs *regs = emaclite->regs;
+
+ if (mdio_wait(regs))
+ return 1;
+
+ u32 ctrl_reg = in_be32(®s->mdioctrl);
+ out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK |
+ ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
+ out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+
+ if (mdio_wait(regs))
+ return 1;
+
+ /* Read data */
+ *data = in_be32(®s->mdiord);
+ return 0;
+}
+
+static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
+ u16 data)
+{
+ struct emaclite_regs *regs = emaclite->regs;
+
+ if (mdio_wait(regs))
+ return 1;
+
+ /*
+ * Write the PHY address, register number and clear the OP bit in the
+ * MDIO Address register and then write the value into the MDIO Write
+ * Data register. Finally, set the Status bit in the MDIO Control
+ * register to start a MDIO write transaction.
+ */
+ u32 ctrl_reg = in_be32(®s->mdioctrl);
+ out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
+ ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
+ out_be32(®s->mdiowr, data);
+ out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+
+ if (mdio_wait(regs))
+ return 1;
+
+ return 0;
+}
+
+static void emaclite_stop(struct udevice *dev)
+{
+ debug("eth_stop\n");
+}
+
+/* Use MII register 1 (MII status register) to detect PHY */
+#define PHY_DETECT_REG 1
+
+/* Mask used to verify certain PHY features (or register contents)
+ * in the register above:
+ * 0x1000: 10Mbps full duplex support
+ * 0x0800: 10Mbps half duplex support
+ * 0x0008: Auto-negotiation support
+ */
+#define PHY_DETECT_MASK 0x1808
+
+static int setup_phy(struct udevice *dev)
+{
+ int i;
+ u16 phyreg;
+ struct xemaclite *emaclite = dev_get_priv(dev);
+ struct phy_device *phydev;
+
+ u32 supported = SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full;
+
+ if (emaclite->phyaddr != -1) {
+ phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
+ if ((phyreg != 0xFFFF) &&
+ ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+ /* Found a valid PHY address */
+ debug("Default phy address %d is valid\n",
+ emaclite->phyaddr);
+ } else {
+ debug("PHY address is not setup correctly %d\n",
+ emaclite->phyaddr);
+ emaclite->phyaddr = -1;
+ }
+ }
+
+ if (emaclite->phyaddr == -1) {
+ /* detect the PHY address */
+ for (i = 31; i >= 0; i--) {
+ phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
+ if ((phyreg != 0xFFFF) &&
+ ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+ /* Found a valid PHY address */
+ emaclite->phyaddr = i;
+ debug("emaclite: Found valid phy address, %d\n",
+ i);
+ break;
+ }
+ }
+ }
+
+ /* interface - look at tsec */
+ phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
+ PHY_INTERFACE_MODE_MII);
+ /*
+ * Phy can support 1000baseT but device NOT that's why phydev->supported
+ * must be setup for 1000baseT. phydev->advertising setups what speeds
+ * will be used for autonegotiation where 1000baseT must be disabled.
+ */
+ phydev->supported = supported | SUPPORTED_1000baseT_Half |
+ SUPPORTED_1000baseT_Full;
+ phydev->advertising = supported;
+ emaclite->phydev = phydev;
+ phy_config(phydev);
+ phy_startup(phydev);
+
+ if (!phydev->link) {
+ printf("%s: No link.\n", phydev->dev->name);
+ return 0;
+ }
+
+ /* Do not setup anything */
+ return 1;
+}
+
+static int emaclite_start(struct udevice *dev)
+{
+ struct xemaclite *emaclite = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct emaclite_regs *regs = emaclite->regs;
+
debug("EmacLite Initialization Started\n");
/*
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
- out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
+ out_be32(®s->tx_ping_tsr, 0);
/* Copy MAC address */
- xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
+ xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
+ ENET_ADDR_LENGTH);
/* Set the length */
- out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+ out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH);
/* Update the MAC address in the EMAC Lite */
- out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
+ out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
/* Wait for EMAC Lite to finish with the MAC address update */
- while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
+ while ((in_be32 (®s->tx_ping_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
if (emaclite->txpp) {
/* The same operation with PONG TX */
- out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
- xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
- XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
- out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
- out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
- XEL_TSR_PROG_MAC_ADDR);
- while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
- XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
+ out_be32(®s->tx_pong_tsr, 0);
+ xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
+ ENET_ADDR_LENGTH);
+ out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH);
+ out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
+ while ((in_be32(®s->tx_pong_tsr) &
+ XEL_TSR_PROG_MAC_ADDR) != 0)
;
}
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
- out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
+ out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
if (emaclite->rxpp)
- out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
- XEL_RSR_RECV_IE_MASK);
+ out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
+
+ out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
+ if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
+ if (!setup_phy(dev))
+ return -1;
debug("EmacLite Initialization complete\n");
return 0;
}
-static int xemaclite_txbufferavailable(struct eth_device *dev)
+static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
{
- u32 reg;
- u32 txpingbusy;
- u32 txpongbusy;
- struct xemaclite *emaclite = dev->priv;
+ u32 tmp;
+ struct emaclite_regs *regs = emaclite->regs;
/*
* Read the other buffer register
* and determine if the other buffer is available
*/
- reg = in_be32 (dev->iobase +
- emaclite->nexttxbuffertouse + 0);
- txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
- XEL_TSR_XMIT_BUSY_MASK);
-
- reg = in_be32 (dev->iobase +
- (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
- txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
- XEL_TSR_XMIT_BUSY_MASK);
+ tmp = ~in_be32(®s->tx_ping_tsr);
+ if (emaclite->txpp)
+ tmp |= ~in_be32(®s->tx_pong_tsr);
- return !(txpingbusy && txpongbusy);
+ return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
}
-static int emaclite_send(struct eth_device *dev, void *ptr, int len)
+static int emaclite_send(struct udevice *dev, void *ptr, int len)
{
u32 reg;
- u32 baseaddress;
- struct xemaclite *emaclite = dev->priv;
+ struct xemaclite *emaclite = dev_get_priv(dev);
+ struct emaclite_regs *regs = emaclite->regs;
u32 maxtry = 1000;
if (len > PKTSIZE)
len = PKTSIZE;
- while (!xemaclite_txbufferavailable(dev) && maxtry) {
+ while (xemaclite_txbufferavailable(emaclite) && maxtry) {
udelay(10);
maxtry--;
}
if (!maxtry) {
printf("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
- out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
+ out_be32(®s->tx_ping_tsr, 0);
if (emaclite->txpp) {
- out_be32 (dev->iobase + XEL_TSR_OFFSET +
- XEL_BUFFER_OFFSET, 0);
+ out_be32(®s->tx_pong_tsr, 0);
}
return -1;
}
- /* Determine the expected TX buffer address */
- baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
-
/* Determine if the expected buffer address is empty */
- reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
- if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
- && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
- & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
-
- if (emaclite->txpp)
- emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
-
- debug("Send packet from 0x%x\n", baseaddress);
+ reg = in_be32(®s->tx_ping_tsr);
+ if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
+ debug("Send packet from tx_ping buffer\n");
/* Write the frame to the buffer */
- xemaclite_alignedwrite(ptr, baseaddress, len);
- out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
- (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
- reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
+ xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
+ out_be32(®s->tx_ping_tplr, len &
+ (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
+ reg = in_be32(®s->tx_ping_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
- if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
- reg |= XEL_TSR_XMIT_ACTIVE_MASK;
- out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
+ out_be32(®s->tx_ping_tsr, reg);
return 0;
}
if (emaclite->txpp) {
- /* Switch to second buffer */
- baseaddress ^= XEL_BUFFER_OFFSET;
/* Determine if the expected buffer address is empty */
- reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
- if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
- && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
- & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
- debug("Send packet from 0x%x\n", baseaddress);
+ reg = in_be32(®s->tx_pong_tsr);
+ if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
+ debug("Send packet from tx_pong buffer\n");
/* Write the frame to the buffer */
- xemaclite_alignedwrite(ptr, baseaddress, len);
- out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
- (XEL_TPLR_LENGTH_MASK_HI |
- XEL_TPLR_LENGTH_MASK_LO)));
- reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
+ xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
+ out_be32(®s->tx_pong_tplr, len &
+ (XEL_TPLR_LENGTH_MASK_HI |
+ XEL_TPLR_LENGTH_MASK_LO));
+ reg = in_be32(®s->tx_pong_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
- if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
- reg |= XEL_TSR_XMIT_ACTIVE_MASK;
- out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
+ out_be32(®s->tx_pong_tsr, reg);
return 0;
}
}
return -1;
}
-static int emaclite_recv(struct eth_device *dev)
+static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
{
- u32 length;
- u32 reg;
- u32 baseaddress;
+ u32 length, first_read, reg, attempt = 0;
+ void *addr, *ack;
struct xemaclite *emaclite = dev->priv;
+ struct emaclite_regs *regs = emaclite->regs;
+ struct ethernet_hdr *eth;
+ struct ip_udp_hdr *ip;
+
+try_again:
+ if (!emaclite->use_rx_pong_buffer_next) {
+ reg = in_be32(®s->rx_ping_rsr);
+ debug("Testing data at rx_ping\n");
+ if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
+ debug("Data found in rx_ping buffer\n");
+ addr = ®s->rx_ping;
+ ack = ®s->rx_ping_rsr;
+ } else {
+ debug("Data not found in rx_ping buffer\n");
+ /* Pong buffer is not available - return immediately */
+ if (!emaclite->rxpp)
+ return -1;
- baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
- reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
- debug("Testing data at address 0x%x\n", baseaddress);
- if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
- if (emaclite->rxpp)
- emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
+ /* Try pong buffer if this is first attempt */
+ if (attempt++)
+ return -1;
+ emaclite->use_rx_pong_buffer_next =
+ !emaclite->use_rx_pong_buffer_next;
+ goto try_again;
+ }
} else {
-
- if (!emaclite->rxpp) {
- debug("No data was available - address 0x%x\n",
- baseaddress);
- return 0;
+ reg = in_be32(®s->rx_pong_rsr);
+ debug("Testing data at rx_pong\n");
+ if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
+ debug("Data found in rx_pong buffer\n");
+ addr = ®s->rx_pong;
+ ack = ®s->rx_pong_rsr;
} else {
- baseaddress ^= XEL_BUFFER_OFFSET;
- reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
- if ((reg & XEL_RSR_RECV_DONE_MASK) !=
- XEL_RSR_RECV_DONE_MASK) {
- debug("No data was available - address 0x%x\n",
- baseaddress);
- return 0;
- }
+ debug("Data not found in rx_pong buffer\n");
+ /* Try ping buffer if this is first attempt */
+ if (attempt++)
+ return -1;
+ emaclite->use_rx_pong_buffer_next =
+ !emaclite->use_rx_pong_buffer_next;
+ goto try_again;
}
}
- /* Get the length of the frame that arrived */
- switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
- 0xFFFF0000 ) >> 16) {
- case 0x806:
- length = 42 + 20; /* FIXME size of ARP */
- debug("ARP Packet\n");
- break;
- case 0x800:
- length = 14 + 14 +
- (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
- 0x10))) & 0xFFFF0000) >> 16);
- /* FIXME size of IP packet */
- debug ("IP Packet\n");
- break;
- default:
- debug("Other Packet\n");
- length = PKTSIZE;
- break;
+
+ /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
+ first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
+ xemaclite_alignedread(addr, etherrxbuff, first_read);
+
+ /* Detect real packet size */
+ eth = (struct ethernet_hdr *)etherrxbuff;
+ switch (ntohs(eth->et_protlen)) {
+ case PROT_ARP:
+ length = first_read;
+ debug("ARP Packet %x\n", length);
+ break;
+ case PROT_IP:
+ ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
+ length = ntohs(ip->ip_len);
+ length += ETHER_HDR_SIZE + ETH_FCS_LEN;
+ debug("IP Packet %x\n", length);
+ break;
+ default:
+ debug("Other Packet\n");
+ length = PKTSIZE;
+ break;
}
- xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
- etherrxbuff, length);
+ /* Read the rest of the packet which is longer then first read */
+ if (length != first_read)
+ xemaclite_alignedread(addr + first_read,
+ etherrxbuff + first_read,
+ length - first_read);
/* Acknowledge the frame */
- reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
+ reg = in_be32(ack);
reg &= ~XEL_RSR_RECV_DONE_MASK;
- out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
+ out_be32(ack, reg);
- debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
- net_process_received_packet((uchar *)etherrxbuff, length);
+ debug("Packet receive from 0x%p, length %dB\n", addr, length);
+ *packetp = etherrxbuff;
return length;
-
}
-int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
- int txpp, int rxpp)
+static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
+ int devad, int reg)
{
- struct eth_device *dev;
- struct xemaclite *emaclite;
+ u32 ret;
+ u16 val = 0;
- dev = calloc(1, sizeof(*dev));
- if (dev == NULL)
- return -1;
+ ret = phyread(bus->priv, addr, reg, &val);
+ debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
+ return val;
+}
- emaclite = calloc(1, sizeof(struct xemaclite));
- if (emaclite == NULL) {
- free(dev);
- return -1;
- }
+static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 value)
+{
+ debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
+ return phywrite(bus->priv, addr, reg, value);
+}
+
+static int emaclite_probe(struct udevice *dev)
+{
+ struct xemaclite *emaclite = dev_get_priv(dev);
+ int ret;
- dev->priv = emaclite;
+ emaclite->bus = mdio_alloc();
+ emaclite->bus->read = emaclite_miiphy_read;
+ emaclite->bus->write = emaclite_miiphy_write;
+ emaclite->bus->priv = emaclite;
+ strcpy(emaclite->bus->name, "emaclite");
- emaclite->txpp = txpp;
- emaclite->rxpp = rxpp;
+ ret = mdio_register(emaclite->bus);
+ if (ret)
+ return ret;
- sprintf(dev->name, "Xelite.%lx", base_addr);
+ return 0;
+}
- dev->iobase = base_addr;
- dev->init = emaclite_init;
- dev->halt = emaclite_halt;
- dev->send = emaclite_send;
- dev->recv = emaclite_recv;
+static int emaclite_remove(struct udevice *dev)
+{
+ struct xemaclite *emaclite = dev_get_priv(dev);
- eth_register(dev);
+ free(emaclite->phydev);
+ mdio_unregister(emaclite->bus);
+ mdio_free(emaclite->bus);
- return 1;
+ return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-int xilinx_emaclite_of_init(const void *blob)
+static const struct eth_ops emaclite_ops = {
+ .start = emaclite_start,
+ .send = emaclite_send,
+ .recv = emaclite_recv,
+ .stop = emaclite_stop,
+};
+
+static int emaclite_ofdata_to_platdata(struct udevice *dev)
{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
- u32 ret = 0;
- u32 reg;
- do {
- offset = fdt_node_offset_by_compatible(blob, offset,
- "xlnx,xps-ethernetlite-1.00.a");
- if (offset != -1) {
- reg = fdtdec_get_addr(blob, offset, "reg");
- if (reg != FDT_ADDR_T_NONE) {
- u32 rxpp = fdtdec_get_int(blob, offset,
- "xlnx,rx-ping-pong", 0);
- u32 txpp = fdtdec_get_int(blob, offset,
- "xlnx,tx-ping-pong", 0);
- ret |= xilinx_emaclite_initialize(NULL, reg,
- txpp, rxpp);
- } else {
- debug("EMACLITE: Can't get base address\n");
- return -1;
- }
- }
- } while (offset != -1);
+ pdata->iobase = (phys_addr_t)dev_get_addr(dev);
+ emaclite->regs = (struct emaclite_regs *)pdata->iobase;
+
+ emaclite->phyaddr = -1;
+
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ "phy-handle");
+ if (offset > 0)
+ emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
+ "reg", -1);
+
+ emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "xlnx,tx-ping-pong", 0);
+ emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "xlnx,rx-ping-pong", 0);
- return ret;
+ printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
+ emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
+
+ return 0;
}
-#endif
+
+static const struct udevice_id emaclite_ids[] = {
+ { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
+ { }
+};
+
+U_BOOT_DRIVER(emaclite) = {
+ .name = "emaclite",
+ .id = UCLASS_ETH,
+ .of_match = emaclite_ids,
+ .ofdata_to_platdata = emaclite_ofdata_to_platdata,
+ .probe = emaclite_probe,
+ .remove = emaclite_remove,
+ .ops = &emaclite_ops,
+ .priv_auto_alloc_size = sizeof(struct xemaclite),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
if (devinf->devname) {
strncpy(dev->name, devinf->devname, sizeof(dev->name));
} else {
- snprintf(dev->name, sizeof(dev->name), "lltemac.%lx", devinf->base_addr);
+ snprintf(dev->name, sizeof(dev->name), "ll_tem.%lx",
+ devinf->base_addr);
devinf->devname = dev->name;
}
#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
+#ifdef CONFIG_ARM64
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */
+#else
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
+#endif
#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_UARTLITE
+ bool "Xilinx Uartlite"
+ help
+ Select this to enable a debug UART using the serial_uartlite driver.
+ You will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
config DEBUG_UART_ZYNQ
bool "Xilinx Zynq"
help
If you have a UniPhier based board and want to use the on-chip
serial ports, say Y to this option. If unsure, say N.
+config XILINX_UARTLITE
+ bool "Xilinx Uarlite support"
+ depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx)
+ help
+ If you have a Xilinx based board and want to use the uartlite
+ serial ports, say Y to this option. If unsure, say N.
+
endmenu
/*
- * (C) Copyright 2008-2011 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2008 - 2015 Michal Simek <monstr@monstr.eu>
* Clean driver and add xilinx constant from header file
*
* (C) Copyright 2004 Atmark Techno, Inc.
#include <config.h>
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <serial.h>
-#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
-#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
-#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */
+#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */
+#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */
+#define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */
#define ULITE_CONTROL_RST_TX 0x01
#define ULITE_CONTROL_RST_RX 0x02
unsigned int control;
};
-static struct uartlite *userial_ports[4] = {
-#ifdef XILINX_UARTLITE_BASEADDR
- [0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR1
- [1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR2
- [2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR3
- [3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
-#endif
+struct uartlite_platdata {
+ struct uartlite *regs;
};
-static void uartlite_serial_putc(const char c, const int port)
+static int uartlite_serial_putc(struct udevice *dev, const char ch)
{
- struct uartlite *regs = userial_ports[port];
+ struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite *regs = plat->regs;
- if (c == '\n')
- uartlite_serial_putc('\r', port);
+ if (in_be32(®s->status) & SR_TX_FIFO_FULL)
+ return -EAGAIN;
- while (in_be32(®s->status) & SR_TX_FIFO_FULL)
- ;
- out_be32(®s->tx_fifo, c & 0xff);
-}
+ out_be32(®s->tx_fifo, ch & 0xff);
-static void uartlite_serial_puts(const char *s, const int port)
-{
- while (*s)
- uartlite_serial_putc(*s++, port);
+ return 0;
}
-static int uartlite_serial_getc(const int port)
+static int uartlite_serial_getc(struct udevice *dev)
{
- struct uartlite *regs = userial_ports[port];
+ struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite *regs = plat->regs;
+
+ if (!(in_be32(®s->status) & SR_RX_FIFO_VALID_DATA))
+ return -EAGAIN;
- while (!(in_be32(®s->status) & SR_RX_FIFO_VALID_DATA))
- ;
return in_be32(®s->rx_fifo) & 0xff;
}
-static int uartlite_serial_tstc(const int port)
+static int uartlite_serial_pending(struct udevice *dev, bool input)
{
- struct uartlite *regs = userial_ports[port];
+ struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite *regs = plat->regs;
+
+ if (input)
+ return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA;
- return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA;
+ return !(in_be32(®s->status) & SR_TX_FIFO_EMPTY);
}
-static int uartlite_serial_init(const int port)
+static int uartlite_serial_probe(struct udevice *dev)
{
- struct uartlite *regs = userial_ports[port];
+ struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite *regs = plat->regs;
- if (regs) {
- out_be32(®s->control, 0);
- out_be32(®s->control,
- ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
- in_be32(®s->control);
- return 0;
- }
+ out_be32(®s->control, 0);
+ out_be32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+ in_be32(®s->control);
- return -1;
+ return 0;
}
-/* Multi serial device functions */
-#define DECLARE_ESERIAL_FUNCTIONS(port) \
- static int userial##port##_init(void) \
- { return uartlite_serial_init(port); } \
- static void userial##port##_setbrg(void) {} \
- static int userial##port##_getc(void) \
- { return uartlite_serial_getc(port); } \
- static int userial##port##_tstc(void) \
- { return uartlite_serial_tstc(port); } \
- static void userial##port##_putc(const char c) \
- { uartlite_serial_putc(c, port); } \
- static void userial##port##_puts(const char *s) \
- { uartlite_serial_puts(s, port); }
-
-/* Serial device descriptor */
-#define INIT_ESERIAL_STRUCTURE(port, __name) { \
- .name = __name, \
- .start = userial##port##_init, \
- .stop = NULL, \
- .setbrg = userial##port##_setbrg, \
- .getc = userial##port##_getc, \
- .tstc = userial##port##_tstc, \
- .putc = userial##port##_putc, \
- .puts = userial##port##_puts, \
+static int uartlite_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct uartlite_platdata *plat = dev_get_platdata(dev);
+
+ plat->regs = (struct uartlite *)dev_get_addr(dev);
+
+ return 0;
}
-DECLARE_ESERIAL_FUNCTIONS(0);
-struct serial_device uartlite_serial0_device =
- INIT_ESERIAL_STRUCTURE(0, "ttyUL0");
-DECLARE_ESERIAL_FUNCTIONS(1);
-struct serial_device uartlite_serial1_device =
- INIT_ESERIAL_STRUCTURE(1, "ttyUL1");
-DECLARE_ESERIAL_FUNCTIONS(2);
-struct serial_device uartlite_serial2_device =
- INIT_ESERIAL_STRUCTURE(2, "ttyUL2");
-DECLARE_ESERIAL_FUNCTIONS(3);
-struct serial_device uartlite_serial3_device =
- INIT_ESERIAL_STRUCTURE(3, "ttyUL3");
-
-__weak struct serial_device *default_serial_console(void)
+static const struct dm_serial_ops uartlite_serial_ops = {
+ .putc = uartlite_serial_putc,
+ .pending = uartlite_serial_pending,
+ .getc = uartlite_serial_getc,
+};
+
+static const struct udevice_id uartlite_serial_ids[] = {
+ { .compatible = "xlnx,opb-uartlite-1.00.b", },
+ { .compatible = "xlnx,xps-uartlite-1.00.a" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_uartlite) = {
+ .name = "serial_uartlite",
+ .id = UCLASS_SERIAL,
+ .of_match = uartlite_serial_ids,
+ .ofdata_to_platdata = uartlite_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct uartlite_platdata),
+ .probe = uartlite_serial_probe,
+ .ops = &uartlite_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_UARTLITE
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
{
- if (userial_ports[0])
- return &uartlite_serial0_device;
- if (userial_ports[1])
- return &uartlite_serial1_device;
- if (userial_ports[2])
- return &uartlite_serial2_device;
- if (userial_ports[3])
- return &uartlite_serial3_device;
-
- return NULL;
+ struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+
+ out_be32(®s->control, 0);
+ out_be32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+ in_be32(®s->control);
}
-void uartlite_serial_initialize(void)
+static inline void _debug_uart_putc(int ch)
{
-#ifdef XILINX_UARTLITE_BASEADDR
- serial_register(&uartlite_serial0_device);
-#endif /* XILINX_UARTLITE_BASEADDR */
-#ifdef XILINX_UARTLITE_BASEADDR1
- serial_register(&uartlite_serial1_device);
-#endif /* XILINX_UARTLITE_BASEADDR1 */
-#ifdef XILINX_UARTLITE_BASEADDR2
- serial_register(&uartlite_serial2_device);
-#endif /* XILINX_UARTLITE_BASEADDR2 */
-#ifdef XILINX_UARTLITE_BASEADDR3
- serial_register(&uartlite_serial3_device);
-#endif /* XILINX_UARTLITE_BASEADDR3 */
+ struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+
+ while (in_be32(®s->status) & SR_TX_FIFO_FULL)
+ ;
+
+ out_be32(®s->tx_fifo, ch & 0xff);
}
+
+DEBUG_UART_FUNCS
+#endif
static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
{
struct zynq_uart_priv *priv = dev_get_priv(dev);
- fdt_addr_t addr;
- addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- priv->regs = (struct uart_zynq *)addr;
+ priv->regs = (struct uart_zynq *)dev_get_addr(dev);
return 0;
}
static const struct udevice_id zynq_serial_ids[] = {
{ .compatible = "xlnx,xuartps" },
{ .compatible = "cdns,uart-r1p8" },
+ { .compatible = "cdns,uart-r1p12" },
{ }
};
static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
{
struct fsl_qspi_regs *regs = priv->regs;
- u32 mcr_reg, rbsr_reg, data;
- int i, size;
+ u32 mcr_reg, rbsr_reg, data, size;
+ int i;
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
;
i = 0;
- size = len;
- while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
+ while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
rbsr_reg = qspi_read32(priv->flags, ®s->rbsr);
if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[i]);
data = qspi_endian_xchg(data);
- memcpy(rxbuf, &data, 4);
+ size = (len < 4) ? len : 4;
+ memcpy(rxbuf, &data, size);
+ len -= size;
rxbuf++;
- size -= 4;
i++;
}
}
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
}
-static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf)
+static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
{
struct fsl_qspi_regs *regs = priv->regs;
u32 mcr_reg, reg, data;
if (reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[0]);
data = qspi_endian_xchg(data);
- memcpy(rxbuf, &data, 4);
+ memcpy(rxbuf, &data, len);
qspi_write32(priv->flags, ®s->mcr,
qspi_read32(priv->flags, ®s->mcr) |
QSPI_MCR_CLR_RXF_MASK);
} else if (priv->cur_seqid == QSPI_CMD_RDID)
qspi_op_rdid(priv, din, bytes);
else if (priv->cur_seqid == QSPI_CMD_RDSR)
- qspi_op_rdsr(priv, din);
+ qspi_op_rdsr(priv, din, bytes);
#ifdef CONFIG_SPI_FLASH_BAR
else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
(priv->cur_seqid == QSPI_CMD_RDEAR)) {
dm_spi_bus->max_hz = plat->speed_hz;
- priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
+ priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
priv->flags = plat->flags;
priv->speed_hz = plat->speed_hz;
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_FSL_CHAIN_TRUST_H
+#define __CONFIG_FSL_CHAIN_TRUST_H
+
+/* For secure boot, since ENVIRONMENT in flash/external memories is
+ * not verified, undef CONFIG_ENV_xxx and set default env
+ * (CONFIG_ENV_IS_NOWHERE)
+ */
+#ifdef CONFIG_SECURE_BOOT
+
+#undef CONFIG_ENV_IS_IN_EEPROM
+#undef CONFIG_ENV_IS_IN_NAND
+#undef CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_SPI_FLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#endif
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+
+#ifndef CONFIG_EXTRA_ENV
+#define CONFIG_EXTRA_ENV ""
+#endif
+
+/*
+ * Control should not reach back to uboot after validation of images
+ * for secure boot flow and therefore bootscript should have
+ * the bootm command. If control reaches back to uboot anyhow
+ * after validating images, core should just spin.
+ */
+
+/*
+ * Define the key hash for boot script here if public/private key pair used to
+ * sign bootscript are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_BOOTSCRIPT_KEY_HASH \
+ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ */
+
+#ifdef CONFIG_BOOTSCRIPT_KEY_HASH
+#define CONFIG_SECBOOT \
+ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
+ "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \
+ "ramdisk_size=600000\';" \
+ CONFIG_EXTRA_ENV \
+ "esbc_validate $bs_hdraddr " \
+ __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \
+ "source $img_addr;" \
+ "esbc_halt\0"
+#else
+#define CONFIG_SECBOOT \
+ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
+ "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \
+ "ramdisk_size=600000\';" \
+ CONFIG_EXTRA_ENV \
+ "esbc_validate $bs_hdraddr;" \
+ "source $img_addr;" \
+ "esbc_halt\0"
+#endif
+
+/* For secure boot flow, default environment used will be used */
+#if defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BS_COPY_ENV \
+ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
+ "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \
+ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \
+ "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \
+ "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \
+ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
+
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_BS_COPY_CMD \
+ "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \
+ "nand read $bs_ram $bs_flash $bs_size ;"
+#endif /* CONFIG_RAMBOOT_NAND */
+#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
+
+#endif
+
+#ifndef CONFIG_BS_COPY_ENV
+#define CONFIG_BS_COPY_ENV
+#endif
+
+#ifndef CONFIG_BS_COPY_CMD
+#define CONFIG_BS_COPY_CMD
+#endif
+
+#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \
+ CONFIG_BS_COPY_CMD \
+ CONFIG_SECBOOT
+
+#endif
+#endif
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_FSL_SECBOOT_H
-#define __CONFIG_FSL_SECBOOT_H
-
-#ifdef CONFIG_SECURE_BOOT
-
-#ifndef CONFIG_CMD_ESBC_VALIDATE
-#define CONFIG_CMD_ESBC_VALIDATE
-#endif
-
-#ifndef CONFIG_EXTRA_ENV
-#define CONFIG_EXTRA_ENV ""
-#endif
-
-/*
- * Control should not reach back to uboot after validation of images
- * for secure boot flow and therefore bootscript should have
- * the bootm command. If control reaches back to uboot anyhow
- * after validating images, core should just spin.
- */
-
-/*
- * Define the key hash for boot script here if public/private key pair used to
- * sign bootscript are different from the SRK hash put in the fuse
- * Example of defining KEY_HASH is
- * #define CONFIG_BOOTSCRIPT_KEY_HASH \
- * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
- */
-
-#ifdef CONFIG_BOOTSCRIPT_KEY_HASH
-#define CONFIG_SECBOOT \
- "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
- "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \
- "ramdisk_size=600000\';" \
- CONFIG_EXTRA_ENV \
- "esbc_validate $bs_hdraddr " \
- __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \
- "source $img_addr;" \
- "esbc_halt\0"
-#else
-#define CONFIG_SECBOOT \
- "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
- "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \
- "ramdisk_size=600000\';" \
- CONFIG_EXTRA_ENV \
- "esbc_validate $bs_hdraddr;" \
- "source $img_addr;" \
- "esbc_halt\0"
-#endif
-
-/* For secure boot flow, default environment used will be used */
-#if defined(CONFIG_SYS_RAMBOOT)
-#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
-#define CONFIG_BS_COPY_ENV \
- "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
- "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \
- "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \
- "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \
- "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \
- "setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
-
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_BS_COPY_CMD \
- "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \
- "nand read $bs_ram $bs_flash $bs_size ;"
-#endif /* CONFIG_RAMBOOT_NAND */
-#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
-
-#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
-#elif defined(CONFIG_RAMBOOT_NAND)
-#undef CONFIG_ENV_IS_IN_NAND
-#elif defined(CONFIG_RAMBOOT_SDCARD)
-#undef CONFIG_ENV_IS_IN_MMC
-#endif
-#else /*CONFIG_SYS_RAMBOOT*/
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#define CONFIG_ENV_IS_NOWHERE
-
-#ifndef CONFIG_BS_COPY_ENV
-#define CONFIG_BS_COPY_ENV
-#endif
-
-#ifndef CONFIG_BS_COPY_CMD
-#define CONFIG_BS_COPY_CMD
-#endif
-
-#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \
- CONFIG_BS_COPY_CMD \
- CONFIG_SECBOOT
-/*
- * We don't want boot delay for secure boot flow
- * before autoboot starts
- */
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY 0
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD
-
-/*
- * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for
- * secure boot flow as defining this would enable a user to
- * reach uboot prompt by pressing some key before start of
- * autoboot
- */
-#undef CONFIG_ZERO_BOOTDELAY_CHECK
-
-#endif
-#endif
#include <asm/fsl_secure_boot.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
#endif /* __CONFIG_H */
#include <asm/fsl_secure_boot.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
#endif /* __CONFIG_H */
#include <asm/fsl_secure_boot.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
#endif /* __CONFIG_H */
#include <asm/fsl_secure_boot.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
#endif /* __CONFIG_H */
#define CONFIG_BOARD_EARLY_INIT_F
#endif
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
+
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-#ifdef CONFIG_SECURE_BOOT
-#include <asm/fsl_secure_boot.h>
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
#endif
+#include <asm/fsl_secure_boot.h>
+
#endif /* __T1024QDS_H */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
+
/* support deep sleep */
#ifdef CONFIG_PPC_T1024
#define CONFIG_DEEP_SLEEP
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-#ifdef CONFIG_SECURE_BOOT
-#include <asm/fsl_secure_boot.h>
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
#endif
+#include <asm/fsl_secure_boot.h>
+
#endif /* __T1024RDB_H */
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
-#define CONFIG_CMD_BLOB
-#endif
#endif /* __CONFIG_H */
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
-#define CONFIG_CMD_BLOB
-#endif
#endif /* __CONFIG_H */
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
-#define CONFIG_CMD_BLOB
-#undef CONFIG_CMD_USB
-#endif
#endif /* __T208xQDS_H */
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
-#define CONFIG_CMD_BLOB
-#undef CONFIG_CMD_USB
-#endif
#endif /* __T2080RDB_H */
#include <asm/fsl_secure_boot.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
#endif /* __CONFIG_H */
#include <asm/fsl_secure_boot.h>
-#ifdef CONFIG_SECURE_BOOT
-/* Secure Boot target was not getting build for T4240 because of
- * increased binary size. So the size is being reduced by removing USB
- * which is anyways not used in Secure Environment.
- */
-#undef CONFIG_CMD_USB
-#define CONFIG_CMD_BLOB
-#endif
-
#endif /* __CONFIG_H */
#include <asm/fsl_secure_boot.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008
- *
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com
- *
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec,
- * see http://www.em.avnet.com
- */
-
-#ifndef __CONFIG_FX12_H
-#define __CONFIG_FX12_H
-
-#include "../board/avnet/fx12mm/xparameters.h"
-
-/* cmd config */
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-
-/* sdram */
-#define CONFIG_SYS_SDRAM_SIZE_MB 64
-
-/* environment */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_SYS_ENV_OFFSET 0xA0000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
-#define CONFIG_ENV_OVERWRITE 1
-
-/*Misc*/
-#define CONFIG_PREBOOT "echo U-Boot is up and running;"
-
-/*Flash*/
-#define CONFIG_SYS_FLASH_SIZE (4*1024*1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-#define MTDIDS_DEFAULT "nor0=fx12mm-flash"
-#define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)"
-
-#include "configs/xilinx-ppc405.h"
-
-#endif /* __CONFIG_H */
#define CONFIG_MISC_INIT_R
/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
+#endif
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
#include <asm/fsl_secure_boot.h>
-#endif
#endif
#define CONFIG_MISC_INIT_R
/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
+#endif
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
#include <asm/fsl_secure_boot.h>
-#endif
#endif
#endif
/* IFC */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
/*
* CONFIG_SYS_FLASH_BASE has the final address (core view)
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#endif
+#endif
/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_DOS_PARTITION
#endif
+/* DSPI */
+#define CONFIG_FSL_DSPI
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+#define CONFIG_SPI_FLASH_EON /* cs2 */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+#endif
+#endif
+
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
+
/* FMan ucode */
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
+#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
#endif /* __LS1043A_COMMON_H */
#include "ls1043a_common.h"
#define CONFIG_DISPLAY_CPUINFO
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#else
#define CONFIG_DISPLAY_BOARDINFO
+#endif
#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE 0x82000000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x40010000
#else
#define CONFIG_SYS_TEXT_BASE 0x60100000
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#endif
#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
+#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
#endif
+#endif
+
+/* LPUART */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#endif
/* SATA */
#define CONFIG_LIBATA
/*
* IFC Definitions
*/
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#endif
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
#endif
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
/*
* QIXIS Definitions
*/
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x44
+#define QIXIS_LBMAP_NAND 0x09
+#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_SD_QSPI 0xff
+#define QIXIS_LBMAP_QSPI 0xff
+#define QIXIS_RCW_SRC_NAND 0x106
+#define QIXIS_RCW_SRC_SD 0x040
+#define QIXIS_RCW_SRC_QSPI 0x045
+#define QIXIS_RST_CTL_RESET 0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
+/* QSPI device */
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+#endif
+
/*
* Miscellaneous configurable options
*/
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_CMD_MII
#define CONFIG_CMDLINE_TAG
+#include <asm/fsl_secure_boot.h>
+
#endif /* __LS1043AQDS_H__ */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-/* DSPI */
-#define CONFIG_FSL_DSPI
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
-#define CONFIG_DM_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SF_DEFAULT_BUS 1
-#define CONFIG_SF_DEFAULT_CS 0
-#endif
-
/*
* Environment
*/
#define CONFIG_CMD_EXT2
#endif
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#define CONFIG_CMD_BLOB
-/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
-#define CONFIG_ESBC_ADDR_64BIT
-#endif
-
#include <asm/fsl_secure_boot.h>
#endif /* __LS1043ARDB_H__ */
*/
#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
#endif
#endif
/* uart */
-#ifdef XILINX_UARTLITE_BASEADDR
-# define CONFIG_XILINX_UARTLITE
-# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
-# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
-# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
-#elif XILINX_UART16550_BASEADDR
-# define CONFIG_SYS_NS16550_SERIAL
-# if defined(__MICROBLAZEEL__)
-# define CONFIG_SYS_NS16550_REG_SIZE -4
-# else
-# define CONFIG_SYS_NS16550_REG_SIZE 4
-# endif
-# define CONFIG_CONS_INDEX 1
-# define CONFIG_SYS_NS16550_COM1 \
- ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
-# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE 115200
-
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-# define CONSOLE_ARG "console=console=ttyS0,115200\0"
-#else
-# error Undefined uart
-#endif
/* setting reset address */
/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
-/* ethernet */
-#undef CONFIG_SYS_ENET
-#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
-# define CONFIG_XILINX_EMACLITE 1
-# define CONFIG_SYS_ENET
-#endif
-#if defined(XILINX_AXIEMAC_BASEADDR)
-# define CONFIG_XILINX_AXIEMAC 1
-# define CONFIG_SYS_ENET
-#endif
-
-#undef ET_DEBUG
-
/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
#endif
+#define CONFIG_BOARD_LATE_INIT
/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
# endif
#endif
-#if !defined(CONFIG_OF_CONTROL) || \
- (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
-/* ddr sdram - main memory */
-# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
-# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
-#endif
-
#define CONFIG_SYS_MALLOC_LEN 0xC0000
/* Stack location before relocation */
#endif /* !SPIFLASH */
#endif /* !FLASH */
-/* system ace */
-#ifdef XILINX_SYSACE_BASEADDR
-# define CONFIG_SYSTEMACE
-/* #define DEBUG_SYSTEMACE */
-# define SYSTEMACE_CONFIG_FPGA
-# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
-# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
-# define CONFIG_DOS_PARTITION
-#endif
-
#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_CMD_CACHE
#endif
-#ifdef CONFIG_SYS_ENET
-# define CONFIG_CMD_PING
-# define CONFIG_CMD_DHCP
-# define CONFIG_CMD_TFTPPUT
-#endif
-
-#if defined(CONFIG_SYSTEMACE)
-# define CONFIG_CMD_EXT2
-# define CONFIG_CMD_FAT
-#endif
-
#if defined(FLASH)
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
#define CONFIG_SYS_MAXARGS 15
#define CONFIG_SYS_LONGHELP
/* default load address */
-#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
+#define CONFIG_SYS_LOAD_ADDR 0
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_NETCONSOLE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
/* Enable flat device tree support */
#define CONFIG_LMB 1
-#define CONFIG_FIT 1
#define CONFIG_OF_LIBFDT 1
#if defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_CMD_MII 1
# define CONFIG_PHY_GIGE 1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
-# define CONFIG_PHYLIB 1
# define CONFIG_PHY_ATHEROS 1
# define CONFIG_PHY_BROADCOM 1
# define CONFIG_PHY_DAVICOM 1
# define CONFIG_PHY_LXT 1
# define CONFIG_PHY_MARVELL 1
# define CONFIG_PHY_MICREL 1
+# define CONFIG_PHY_MICREL_KSZ9021
# define CONFIG_PHY_NATSEMI 1
# define CONFIG_PHY_REALTEK 1
# define CONFIG_PHY_VITESSE 1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
-# undef CONFIG_PHYLIB
#endif
/* SPL part */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com/
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*CPU*/
-#define CONFIG_440 1
-#define CONFIG_XILINX_ML507 1
-#include "../board/xilinx/ml507/xparameters.h"
-
-/*Mem Map*/
-#define CONFIG_SYS_SDRAM_SIZE_MB 256
-
-/*Env*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OFFSET 0x340000
-#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
-
-/*Misc*/
-#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
-
-/*Flash*/
-#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 259
-#define MTDIDS_DEFAULT "nor0=ml507-flash"
-#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
-
-/*Generic Configs*/
-#include <configs/xilinx-ppc440.h>
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com/
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*CPU*/
-#define CONFIG_440 1
-#define CONFIG_XILINX_ML507 1
-#include "../board/avnet/v5fx30teval/xparameters.h"
-
-/*Mem Map*/
-#define CONFIG_SYS_SDRAM_SIZE_MB 64
-
-/*Env*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OFFSET 0x1A0000
-#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
-
-/*Misc*/
-#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
-
-/*Flash*/
-#define CONFIG_SYS_FLASH_SIZE (16*1024*1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 131
-#define MTDIDS_DEFAULT "nor0=v5fx30t-flash"
-#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)"
-
-/*Generic Configs*/
-#include <configs/xilinx-ppc440.h>
-
-#endif /* __CONFIG_H */
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* (C) Copyright 2008
#define CONFIG_SYS_NO_FLASH
#endif
-/* serial communication */
-#ifdef XPAR_UARTLITE_0_BASEADDR
-#define CONFIG_XILINX_UARTLITE
-#define XILINX_UARTLITE_BASEADDR XPAR_UARTLITE_0_BASEADDR
-#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
-#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-#else
-#ifdef XPAR_UARTNS550_0_BASEADDR
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 4
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR
-#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 }
-#endif
-#endif
+/* The following table includes the supported baudrates */
+# define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#endif /* __CONFIG_H */
/*
*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* (C) Copyright 2008
#include "../board/xilinx/ppc405-generic/xparameters.h"
+#define CONFIG_405 1
+#define CONFIG_XILINX_405 1
+
/* sdram */
#define CONFIG_SYS_SDRAM_SIZE_MB 256
#define CONFIG_ENV_OVERWRITE 1
/*Misc*/
-#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
+#define CONFIG_PREBOOT "echo U-Boot is up and running;"
/*Flash*/
-#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
-#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 71
+#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
+#define CONFIG_SYS_FLASH_SIZE (128*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
-#define MTDIDS_DEFAULT "nor0=ppc405-flash"
-#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)"
+#define MTDIDS_DEFAULT "nor0=flash"
+#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)"
-#include <configs/xilinx-ppc405.h>
+#include <configs/xilinx-ppc.h>
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- *
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com/
- *
- * (C) Copyright 2008
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* cpu parameter */
-#define CONFIG_405 1
-#define CONFIG_XILINX_405 1
-
-#include <configs/xilinx-ppc.h>
-
-#endif
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/*CPU*/
+/* CPU */
#define CONFIG_440 1
+#define CONFIG_XILINX_440 1
#define CONFIG_XILINX_PPC440_GENERIC 1
#include "../board/xilinx/ppc440-generic/xparameters.h"
-/*Mem Map*/
+/* Mem Map */
#define CONFIG_SYS_SDRAM_SIZE_MB 256
-/*Env*/
+/* Env */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OFFSET 0x340000
+#define CONFIG_ENV_OFFSET 0x340000
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
-/*Misc*/
-#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
-
-/*Flash*/
-#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 259
-#define MTDIDS_DEFAULT "nor0=ml507-flash"
-#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
-
-/*Generic Configs*/
-#include <configs/xilinx-ppc440.h>
+/* Misc */
+#define CONFIG_PREBOOT "echo U-Boot is up and running;"
+
+/* Flash */
+#define CONFIG_SYS_FLASH_SIZE (128*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define MTDIDS_DEFAULT "nor0=flash"
+#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)"
+
+/* Net */
+#ifdef XPAR_LLTEMAC_0_BASEADDR
+#define CONFIG_XILINX_LL_TEMAC
+#define CONFIG_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+#define CONFIG_NET_RANDOM_ETHADDR
+#define CONFIG_LIB_RAND
+#endif
+
+/* Generic Configs */
+#include <configs/xilinx-ppc.h>
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology http://qtec.com/
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef __CONFIG_GEN_H
-#define __CONFIG_GEN_H
-
-/*CPU*/
-#define CONFIG_440 1
-#define CONFIG_XILINX_440 1
-
-#include <configs/xilinx-ppc.h>
-
-#endif /* __CONFIG_H */
#define GICD_BASE 0xF9010000
#define GICC_BASE 0xF9020000
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE
/* Cache Definitions */
#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_IDENT_STRING " Xilinx ZynqMP"
+#if !defined(CONFIG_IDENT_STRING)
+# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
+#endif
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#define CONFIG_OF_LIBFDT
/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
-#define COUNTER_FREQUENCY 4000000
+#if !defined(COUNTER_FREQUENCY)
+# define COUNTER_FREQUENCY 100000000
+#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000)
#define CONFIG_THOR_RESET_OFF
#define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
- "set dfu_alt_info " \
- "Image ram 0x200000 0x1800000\\\\;" \
- "system.dtb ram 0x7000000 0x40000\0" \
+ "setenv dfu_alt_info " \
+ "Image ram $kernel_addr $kernel_size\\\\;" \
+ "system.dtb ram $fdt_addr $fdt_size\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
"kernel_addr=0x80000\0" \
"fdt_addr=0x7000000\0" \
"fdt_high=0x10000000\0" \
- "sdboot=mmcinfo && load mmc 0:0 $fdt_addr system.dtb && " \
- "load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" \
+ "kernel_size=0x2000000\0" \
+ "fdt_size=0x80000\0" \
+ "sdbootdev=0\0"\
+ "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \
+ "load mmc $sdbootdev:$partid $kernel_addr Image && " \
+ "booti $kernel_addr - $fdt_addr\0" \
DFU_ALT_INFO
-#define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \
- "earlycon=cdns,mmio,0xff000000,${baudrate}n8"
#define CONFIG_PREBOOT "run bootargs"
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 5
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHY_MARVELL
+# define CONFIG_PHY_NATSEMI
# define CONFIG_PHY_TI
+# define CONFIG_PHY_GIGE
+# define PHY_ANEG_TIMEOUT 20000
#endif
/* I2C */
/*
- * Configuration for Xilinx ZynqMP emulation
- * platforms. See zynqmp-common.h for ZynqMP
- * common configs
+ * Configuration for Xilinx ZynqMP emulation platforms
*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
+#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
#define CONFIG_ZYNQ_I2C0
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
ZYNQMP_USB1_XHCI_BASEADDR}
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
+#define COUNTER_FREQUENCY 4000000
+
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_EP_H */
#ifdef CONFIG_ZYNQ_QSPI
# define CONFIG_SF_DEFAULT_SPEED 30000000
# define CONFIG_SPI_FLASH_ISSI
-# define CONFIG_SPI_FLASH_BAR
# define CONFIG_CMD_SF
#endif
typedef enum {
BIT_FULL = 0,
BIT_PARTIAL,
+ BIT_NONE = 0xFF,
} bitstream_type;
/* root function definitions */
/* DPBP Version */
#define DPBP_VER_MAJOR 2
-#define DPBP_VER_MINOR 1
+#define DPBP_VER_MINOR 2
/* Command IDs */
#define DPBP_CMDID_CLOSE 0x800
/* DPIO Version */
#define DPIO_VER_MAJOR 3
-#define DPIO_VER_MINOR 1
+#define DPIO_VER_MINOR 2
/* Command IDs */
#define DPIO_CMDID_CLOSE 0x800
MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\
MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\
MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\
+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\
} while (0)
/* Data Path I/O Portal API
* @channel_mode: Notification channel mode
* @num_priorities: Number of priorities for the notification channel (1-8);
* relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
+ * @qbman_version: QBMAN version
*/
struct dpio_attr {
int id;
uint16_t qbman_portal_id;
enum dpio_channel_mode channel_mode;
uint8_t num_priorities;
+ uint32_t qbman_version;
};
/**
/* DPMAC Version */
#define DPMAC_VER_MAJOR 3
-#define DPMAC_VER_MINOR 1
+#define DPMAC_VER_MINOR 2
/* Command IDs */
#define DPMAC_CMDID_CLOSE 0x800
/**
* Management Complex firmware version information
*/
-#define MC_VER_MAJOR 8
+#define MC_VER_MAJOR 9
#define MC_VER_MINOR 0
/**
#define _FSL_DPNI_H
/* DPNI Version */
-#define DPNI_VER_MAJOR 5
-#define DPNI_VER_MINOR 1
+#define DPNI_VER_MAJOR 6
+#define DPNI_VER_MINOR 0
/* Command IDs */
#define DPNI_CMDID_OPEN 0x801
#define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204
#define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205
#define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206
+#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B
#define DPNI_CMDID_GET_QDID 0x210
#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212
#define DPNI_CMDID_GET_TX_FLOW 0x237
#define DPNI_CMDID_SET_RX_FLOW 0x238
#define DPNI_CMDID_GET_RX_FLOW 0x239
+#define DPNI_CMDID_SET_TX_CONF 0x257
+#define DPNI_CMDID_GET_TX_CONF 0x258
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_OPEN(cmd, dpni_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id)
+#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \
+do { \
+ MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
+ MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
+ MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
+ MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
+ MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
+ MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
+ MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
+ MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
+ MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
+ MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \
+ MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \
+ MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \
+ MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \
+ MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \
+ MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \
+ MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \
+ MC_PREP_OP(ext, 4, 0, 16, uint16_t, \
+ cfg->ipr_cfg.max_open_frames_ipv4); \
+ MC_PREP_OP(ext, 4, 16, 16, uint16_t, \
+ cfg->ipr_cfg.max_open_frames_ipv6); \
+ MC_PREP_OP(ext, 4, 32, 16, uint16_t, \
+ cfg->ipr_cfg.max_reass_frm_size); \
+ MC_PREP_OP(ext, 5, 0, 16, uint16_t, \
+ cfg->ipr_cfg.min_frag_size_ipv4); \
+ MC_PREP_OP(ext, 5, 16, 16, uint16_t, \
+ cfg->ipr_cfg.min_frag_size_ipv6); \
+} while (0)
+
+#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \
+do { \
+ MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
+ MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
+ MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
+ MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
+ MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
+ MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
+ MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
+ MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
+ MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
+ MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \
+ MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \
+ MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \
+ MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \
+ MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \
+ MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \
+ MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \
+ MC_EXT_OP(ext, 4, 0, 16, uint16_t, \
+ cfg->ipr_cfg.max_open_frames_ipv4); \
+ MC_EXT_OP(ext, 4, 16, 16, uint16_t, \
+ cfg->ipr_cfg.max_open_frames_ipv6); \
+ MC_EXT_OP(ext, 4, 32, 16, uint16_t, \
+ cfg->ipr_cfg.max_reass_frm_size); \
+ MC_EXT_OP(ext, 5, 0, 16, uint16_t, \
+ cfg->ipr_cfg.min_frag_size_ipv4); \
+ MC_EXT_OP(ext, 5, 16, 16, uint16_t, \
+ cfg->ipr_cfg.min_frag_size_ipv6); \
+} while (0)
+
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_CREATE(cmd, cfg) \
do { \
MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \
MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \
MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \
- MC_CMD_OP(cmd, 3, 0, 8, uint8_t, cfg->adv.max_dist_per_tc[0]); \
- MC_CMD_OP(cmd, 3, 8, 8, uint8_t, cfg->adv.max_dist_per_tc[1]); \
- MC_CMD_OP(cmd, 3, 16, 8, uint8_t, cfg->adv.max_dist_per_tc[2]); \
- MC_CMD_OP(cmd, 3, 24, 8, uint8_t, cfg->adv.max_dist_per_tc[3]); \
- MC_CMD_OP(cmd, 3, 32, 8, uint8_t, cfg->adv.max_dist_per_tc[4]); \
- MC_CMD_OP(cmd, 3, 40, 8, uint8_t, cfg->adv.max_dist_per_tc[5]); \
- MC_CMD_OP(cmd, 3, 48, 8, uint8_t, cfg->adv.max_dist_per_tc[6]); \
- MC_CMD_OP(cmd, 3, 56, 8, uint8_t, cfg->adv.max_dist_per_tc[7]); \
- MC_CMD_OP(cmd, 4, 0, 16, uint16_t, \
- cfg->adv.ipr_cfg.max_reass_frm_size); \
- MC_CMD_OP(cmd, 4, 16, 16, uint16_t, \
- cfg->adv.ipr_cfg.min_frag_size_ipv4); \
- MC_CMD_OP(cmd, 4, 32, 16, uint16_t, \
- cfg->adv.ipr_cfg.min_frag_size_ipv6); \
MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \
MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \
- MC_CMD_OP(cmd, 5, 0, 16, uint16_t, \
- cfg->adv.ipr_cfg.max_open_frames_ipv4); \
- MC_CMD_OP(cmd, 5, 16, 16, uint16_t, \
- cfg->adv.ipr_cfg.max_open_frames_ipv6); \
+ MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \
} while (0)
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_SET_POOLS(cmd, cfg) \
do { \
MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \
+ MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \
+ MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \
+ MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \
+ MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \
+ MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \
+ MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \
+ MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \
+ MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \
MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \
MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\
MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \
MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\
} while (0)
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_GET_ATTR(cmd, attr) \
+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova)
+
/* cmd, param, offset, width, type, arg_name */
#define DPNI_RSP_GET_ATTR(cmd, attr) \
do { \
MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \
MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \
MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \
- MC_RSP_OP(cmd, 3, 0, 8, uint8_t, attr->max_dist_per_tc[0]); \
- MC_RSP_OP(cmd, 3, 8, 8, uint8_t, attr->max_dist_per_tc[1]); \
- MC_RSP_OP(cmd, 3, 16, 8, uint8_t, attr->max_dist_per_tc[2]); \
- MC_RSP_OP(cmd, 3, 24, 8, uint8_t, attr->max_dist_per_tc[3]); \
- MC_RSP_OP(cmd, 3, 32, 8, uint8_t, attr->max_dist_per_tc[4]); \
- MC_RSP_OP(cmd, 3, 40, 8, uint8_t, attr->max_dist_per_tc[5]); \
- MC_RSP_OP(cmd, 3, 48, 8, uint8_t, attr->max_dist_per_tc[6]); \
- MC_RSP_OP(cmd, 3, 56, 8, uint8_t, attr->max_dist_per_tc[7]); \
- MC_RSP_OP(cmd, 4, 0, 16, uint16_t, \
- attr->ipr_cfg.max_reass_frm_size); \
- MC_RSP_OP(cmd, 4, 16, 16, uint16_t, \
- attr->ipr_cfg.min_frag_size_ipv4); \
- MC_RSP_OP(cmd, 4, 32, 16, uint16_t, \
- attr->ipr_cfg.min_frag_size_ipv6);\
- MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \
- MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \
- MC_RSP_OP(cmd, 5, 0, 16, uint16_t, \
- attr->ipr_cfg.max_open_frames_ipv4); \
- MC_RSP_OP(cmd, 5, 16, 16, uint16_t, \
- attr->ipr_cfg.max_open_frames_ipv6); \
+ MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \
+ MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \
MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\
MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\
} while (0)
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \
+ MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \
+ MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \
+} while (0)
+
/* cmd, param, offset, width, type, arg_name */
#define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \
do { \
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \
do { \
- MC_CMD_OP(cmd, 0, 0, 32, int, \
- cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_id);\
- MC_CMD_OP(cmd, 0, 32, 8, uint8_t, \
- cfg->conf_err_cfg.queue_cfg.dest_cfg.priority);\
- MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \
- cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_type);\
- MC_CMD_OP(cmd, 0, 42, 1, int, cfg->conf_err_cfg.errors_only);\
MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\
MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\
- MC_CMD_OP(cmd, 0, 45, 1, int, \
- cfg->conf_err_cfg.use_default_queue);\
+ MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\
MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\
- MC_CMD_OP(cmd, 1, 0, 64, uint64_t, \
- cfg->conf_err_cfg.queue_cfg.user_ctx);\
MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
- MC_CMD_OP(cmd, 2, 32, 32, uint32_t, \
- cfg->conf_err_cfg.queue_cfg.options);\
} while (0)
/* cmd, param, offset, width, type, arg_name */
/* cmd, param, offset, width, type, arg_name */
#define DPNI_RSP_GET_TX_FLOW(cmd, attr) \
do { \
- MC_RSP_OP(cmd, 0, 0, 32, int, \
- attr->conf_err_attr.queue_attr.dest_cfg.dest_id);\
- MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \
- attr->conf_err_attr.queue_attr.dest_cfg.priority);\
- MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \
- attr->conf_err_attr.queue_attr.dest_cfg.dest_type);\
- MC_RSP_OP(cmd, 0, 42, 1, int, attr->conf_err_attr.errors_only);\
MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\
MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\
- MC_RSP_OP(cmd, 0, 45, 1, int, \
- attr->conf_err_attr.use_default_queue);\
- MC_RSP_OP(cmd, 1, 0, 64, uint64_t, \
- attr->conf_err_attr.queue_attr.user_ctx);\
- MC_RSP_OP(cmd, 2, 32, 32, uint32_t, \
- attr->conf_err_attr.queue_attr.fqid);\
+ MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\
} while (0)
/* cmd, param, offset, width, type, arg_name */
MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \
- MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \
+ MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \
MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \
MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
cfg->flc_cfg.frame_data_size);\
cfg->flc_cfg.flow_context_size);\
MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\
MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\
+ MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \
} while (0)
/* cmd, param, offset, width, type, arg_name */
MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \
MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \
- MC_CMD_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\
+ MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\
MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \
+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \
MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \
MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \
MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\
} while (0)
+#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \
+ MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \
+ cfg->queue_cfg.dest_cfg.dest_type); \
+ MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \
+ MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \
+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \
+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \
+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \
+ MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \
+ cfg->queue_cfg.tail_drop_threshold); \
+ MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \
+ cfg->queue_cfg.flc_cfg.flc_type); \
+ MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \
+ cfg->queue_cfg.flc_cfg.frame_data_size); \
+ MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \
+ cfg->queue_cfg.flc_cfg.flow_context_size); \
+ MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \
+ MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \
+ cfg->queue_cfg.flc_cfg.flow_context); \
+} while (0)
+
+#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \
+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id)
+
+#define DPNI_RSP_GET_TX_CONF(cmd, attr) \
+do { \
+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \
+ attr->queue_attr.dest_cfg.priority); \
+ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \
+ attr->queue_attr.dest_cfg.dest_type); \
+ MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \
+ MC_RSP_OP(cmd, 0, 46, 1, int, \
+ attr->queue_attr.order_preservation_en); \
+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \
+ MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \
+ MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \
+ attr->queue_attr.tail_drop_threshold); \
+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \
+ MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \
+ attr->queue_attr.flc_cfg.flc_type); \
+ MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \
+ attr->queue_attr.flc_cfg.frame_data_size); \
+ MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \
+ attr->queue_attr.flc_cfg.flow_context_size); \
+ MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \
+ MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \
+ attr->queue_attr.flc_cfg.flow_context); \
+} while (0)
+
enum net_prot {
NET_PROT_NONE = 0,
NET_PROT_PAYLOAD,
#define DPNI_ALL_TC_FLOWS (uint16_t)(-1)
/* Generate new flow ID; see dpni_set_tx_flow() */
#define DPNI_NEW_FLOW_ID (uint16_t)(-1)
+/* use for common tx-conf queue; see dpni_set_tx_conf_<x>() */
+#define DPNI_COMMON_TX_CONF (uint16_t)(-1)
/**
* dpni_open() - Open a control session for the specified object
#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000
/**
- * struct dpni_ipr_cfg - Structure representing IP reassembly configuration
- * @max_reass_frm_size: Maximum size of the reassembled frame
- * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments
- * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments
- * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly process
- * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly process
+ * struct dpni_extended_cfg - Structure representing extended DPNI configuration
+ * @tc_cfg: TCs configuration
+ * @ipr_cfg: IP reassembly configuration
*/
-struct dpni_ipr_cfg {
- uint16_t max_reass_frm_size;
- uint16_t min_frag_size_ipv4;
- uint16_t min_frag_size_ipv6;
- uint16_t max_open_frames_ipv4;
- uint16_t max_open_frames_ipv6;
+struct dpni_extended_cfg {
+ /**
+ * struct tc_cfg - TC configuration
+ * @max_dist: Maximum distribution size for Rx traffic class;
+ * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,
+ * 112,128,192,224,256,384,448,512,768,896,1024;
+ * value '0' will be treated as '1'.
+ * other unsupported values will be round down to the nearest
+ * supported value.
+ * @max_fs_entries: Maximum FS entries for Rx traffic class;
+ * '0' means no support for this TC;
+ */
+ struct {
+ uint16_t max_dist;
+ uint16_t max_fs_entries;
+ } tc_cfg[DPNI_MAX_TC];
+ /**
+ * struct ipr_cfg - Structure representing IP reassembly configuration
+ * @max_reass_frm_size: Maximum size of the reassembled frame
+ * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments
+ * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments
+ * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly
+ * process
+ * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly
+ * process
+ */
+ struct {
+ uint16_t max_reass_frm_size;
+ uint16_t min_frag_size_ipv4;
+ uint16_t min_frag_size_ipv6;
+ uint16_t max_open_frames_ipv4;
+ uint16_t max_open_frames_ipv6;
+ } ipr_cfg;
};
+/**
+ * dpni_prepare_extended_cfg() - function prepare extended parameters
+ * @cfg: extended structure
+ * @ext_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
+ *
+ * This function has to be called before dpni_create()
+ */
+int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg,
+ uint8_t *ext_cfg_buf);
+
/**
* struct dpni_cfg - Structure representing DPNI configuration
* @mac_addr: Primary MAC address
* '0' will be treated as '1'
* @max_tcs: Maximum number of traffic classes (for both Tx and Rx);
* '0' will e treated as '1'
- * @max_dist_per_tc: Maximum distribution size per Rx traffic class;
- * Must be set to the required value minus 1;
- * i.e. 0->1, 1->2, ... ,255->256;
- * Non-power-of-2 values are rounded up to the next
- * power-of-2 value as hardware demands it
* @max_unicast_filters: Maximum number of unicast filters;
* '0' is treated as '16'
* @max_multicast_filters: Maximum number of multicast filters;
* should be between '0' and max_tcs
* @max_congestion_ctrl: Maximum number of congestion control groups
* (CGs); covers early drop and congestion notification
- * requirements for traffic classes;
- * should be between '0' and max_tcs
- * @ipr_cfg: IP reassembly configuration
+ * requirements;
+ * should be between '0' and ('max_tcs' + 'max_senders')
+ * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory
+ * filled with the extended configuration by calling
+ * dpni_prepare_extended_cfg()
*/
struct {
uint32_t options;
enum net_prot start_hdr;
uint8_t max_senders;
uint8_t max_tcs;
- uint8_t max_dist_per_tc[DPNI_MAX_TC];
uint8_t max_unicast_filters;
uint8_t max_multicast_filters;
uint8_t max_vlan_filters;
uint8_t max_dist_key_size;
uint8_t max_policers;
uint8_t max_congestion_ctrl;
- struct dpni_ipr_cfg ipr_cfg;
+ uint64_t ext_cfg_iova;
} adv;
};
* @max_senders: Maximum number of different senders; used as the number
* of dedicated Tx flows;
* @max_tcs: Maximum number of traffic classes (for both Tx and Rx)
- * @max_dist_per_tc: Maximum distribution size per Rx traffic class;
- * Set to the required value minus 1
* @max_unicast_filters: Maximum number of unicast filters
* @max_multicast_filters: Maximum number of multicast filters
* @max_vlan_filters: Maximum number of VLAN filters
* @max_dist_key_size: Maximum key size for the distribution look-up
* @max_policers: Maximum number of policers;
* @max_congestion_ctrl: Maximum number of congestion control groups (CGs);
- * @ipr_cfg: IP reassembly configuration
+ * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory;
+ * call dpni_extract_extended_cfg() to extract the extended configuration
*/
struct dpni_attr {
int id;
uint32_t options;
uint8_t max_senders;
uint8_t max_tcs;
- uint8_t max_dist_per_tc[DPNI_MAX_TC];
uint8_t max_unicast_filters;
uint8_t max_multicast_filters;
uint8_t max_vlan_filters;
uint8_t max_dist_key_size;
uint8_t max_policers;
uint8_t max_congestion_ctrl;
- struct dpni_ipr_cfg ipr_cfg;
+ uint64_t ext_cfg_iova;
};
/**
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPNI object
- * @attr: Returned object's attributes
+ * @attr: Object's attributes
*
* Return: '0' on Success; Error code otherwise.
*/
uint16_t token,
struct dpni_attr *attr);
+/**
+ * dpni_extract_extended_cfg() - extract the extended parameters
+ * @cfg: extended structure
+ * @ext_cfg_buf: 256 bytes of DMA-able memory
+ *
+ * This function has to be called after dpni_get_attributes()
+ */
+int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg,
+ const uint8_t *ext_cfg_buf);
+
+/**
+ * DPNI errors
+ */
+
+/**
+ * Extract out of frame header error
+ */
+#define DPNI_ERROR_EOFHE 0x00020000
+/**
+ * Frame length error
+ */
+#define DPNI_ERROR_FLE 0x00002000
+/**
+ * Frame physical error
+ */
+#define DPNI_ERROR_FPE 0x00001000
+/**
+ * Parsing header error
+ */
+#define DPNI_ERROR_PHE 0x00000020
+/**
+ * Parser L3 checksum error
+ */
+#define DPNI_ERROR_L3CE 0x00000004
+/**
+ * Parser L3 checksum error
+ */
+#define DPNI_ERROR_L4CE 0x00000001
+
+/**
+ * enum dpni_error_action - Defines DPNI behavior for errors
+ * @DPNI_ERROR_ACTION_DISCARD: Discard the frame
+ * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow
+ * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue
+ */
+enum dpni_error_action {
+ DPNI_ERROR_ACTION_DISCARD = 0,
+ DPNI_ERROR_ACTION_CONTINUE = 1,
+ DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2
+};
+
+/**
+ * struct dpni_error_cfg - Structure representing DPNI errors treatment
+ * @errors: Errors mask; use 'DPNI_ERROR__<X>
+ * @error_action: The desired action for the errors mask
+ * @set_frame_annotation: Set to '1' to mark the errors in frame annotation
+ * status (FAS); relevant only for the non-discard action
+ */
+struct dpni_error_cfg {
+ uint32_t errors;
+ enum dpni_error_action error_action;
+ int set_frame_annotation;
+};
+
+/**
+ * dpni_set_errors_behavior() - Set errors behavior
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @cfg: Errors configuration
+ *
+ * this function may be called numerous times with different
+ * error masks
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpni_error_cfg *cfg);
+
/* DPNI buffer layout modification options */
/* Select to modify the time-stamp setting */
#define DPNI_QUEUE_OPT_FLC 0x00000004
/* Select to modify the queue's order preservation */
#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008
+/* Select to modify the queue's tail-drop threshold */
+#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010
/**
* struct dpni_queue_cfg - Structure representing queue configuration
* @order_preservation_en: enable/disable order preservation;
* valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained
* in 'options'
+ * @tail_drop_threshold: set the queue's tail drop threshold in bytes;
+ * '0' value disable the threshold; maximum value is 0xE000000;
+ * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained
+ * in 'options'
*/
struct dpni_queue_cfg {
uint32_t options;
struct dpni_dest_cfg dest_cfg;
struct dpni_flc_cfg flc_cfg;
int order_preservation_en;
+ uint32_t tail_drop_threshold;
};
/**
* @dest_cfg: Queue destination configuration
* @flc_cfg: Flow context configuration
* @order_preservation_en: enable/disable order preservation
+ * @tail_drop_threshold: queue's tail drop threshold in bytes;
* @fqid: Virtual fqid value to be used for dequeue operations
*/
struct dpni_queue_attr {
struct dpni_dest_cfg dest_cfg;
struct dpni_flc_cfg flc_cfg;
int order_preservation_en;
+ uint32_t tail_drop_threshold;
uint32_t fqid;
};
/* Select to modify the settings for dedicate Tx confirmation/error */
#define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001
-/*!< Select to modify the Tx confirmation and/or error setting */
-#define DPNI_TX_FLOW_OPT_ONLY_TX_ERROR 0x00000002
-/*!< Select to modify the queue configuration */
-#define DPNI_TX_FLOW_OPT_QUEUE 0x00000004
/*!< Select to modify the L3 checksum generation setting */
#define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010
/*!< Select to modify the L4 checksum generation setting */
/**
* struct dpni_tx_flow_cfg - Structure representing Tx flow configuration
* @options: Flags representing the suggested modifications to the Tx flow;
- * Use any combination 'DPNI_TX_FLOW_OPT_<X>' flags
- * @conf_err_cfg: Tx confirmation and error configuration; these settings are
- * ignored if 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' was set at
- * DPNI creation
+ * Use any combination 'DPNI_TX_FLOW_OPT_<X>' flags
+ * @use_common_tx_conf_queue: Set to '1' to use the common (default) Tx
+ * confirmation and error queue; Set to '0' to use the private
+ * Tx confirmation and error queue; valid only if
+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation
+ * and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'options'
* @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable;
- * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in
- * 'options'
+ * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in 'options'
* @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable;
- * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in
- * 'options'
+ * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in 'options'
*/
struct dpni_tx_flow_cfg {
- uint32_t options;
- /**
- * struct cnf_err_cfg - Tx confirmation and error configuration
- * @use_default_queue: Set to '1' to use the common (default) Tx
- * confirmation and error queue; Set to '0' to use the
- * private Tx confirmation and error queue; valid only if
- * 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in
- * 'options'
- * @errors_only: Set to '1' to report back only error frames;
- * Set to '0' to confirm transmission/error for all
- * transmitted frames;
- * valid only if 'DPNI_TX_FLOW_OPT_ONLY_TX_ERROR' is
- * contained in 'options' and 'use_default_queue = 0';
- * @queue_cfg: Queue configuration; valid only if
- * 'DPNI_TX_FLOW_OPT_QUEUE' is contained in 'options'
- */
- struct {
- int use_default_queue;
- int errors_only;
- struct dpni_queue_cfg queue_cfg;
- } conf_err_cfg;
- int l3_chksum_gen;
- int l4_chksum_gen;
+ uint32_t options;
+ int use_common_tx_conf_queue;
+ int l3_chksum_gen;
+ int l4_chksum_gen;
};
/**
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPNI object
* @flow_id: Provides (or returns) the sender's flow ID;
- * for each new sender set (*flow_id) to
- * 'DPNI_NEW_FLOW_ID' to generate a new flow_id;
- * this ID should be used as the QDBIN argument
- * in enqueue operations
+ * for each new sender set (*flow_id) to 'DPNI_NEW_FLOW_ID' to generate
+ * a new flow_id; this ID should be used as the QDBIN argument
+ * in enqueue operations
* @cfg: Tx flow configuration
*
* Return: '0' on Success; Error code otherwise.
/**
* struct dpni_tx_flow_attr - Structure representing Tx flow attributes
- * @conf_err_attr: Tx confirmation and error attributes
+ * @use_common_tx_conf_queue: '1' if using common (default) Tx confirmation and
+ * error queue; '0' if using private Tx confirmation and error queue
* @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled
* @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled
*/
struct dpni_tx_flow_attr {
- /**
- * struct conf_err_attr - Tx confirmation and error attributes
- * @use_default_queue: '1' if using common (default) Tx confirmation and
- * error queue;
- * '0' if using private Tx confirmation and error
- * queue
- * @errors_only: '1' if only error frames are reported back; '0' if all
- * transmitted frames are confirmed
- * @queue_attr: Queue attributes
- */
- struct {
- int use_default_queue;
- int errors_only;
- struct dpni_queue_attr queue_attr;
- } conf_err_attr;
- int l3_chksum_gen;
- int l4_chksum_gen;
+ int use_common_tx_conf_queue;
+ int l3_chksum_gen;
+ int l4_chksum_gen;
};
/**
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPNI object
* @flow_id: The sender's flow ID, as returned by the
- * dpni_set_tx_flow() function
+ * dpni_set_tx_flow() function
* @attr: Returned Tx flow attributes
*
* Return: '0' on Success; Error code otherwise.
uint16_t flow_id,
struct dpni_tx_flow_attr *attr);
+/**
+ * struct dpni_tx_conf_cfg - Structure representing Tx conf configuration
+ * @errors_only: Set to '1' to report back only error frames;
+ * Set to '0' to confirm transmission/error for all transmitted frames;
+ * @queue_cfg: Queue configuration
+ */
+struct dpni_tx_conf_cfg {
+ int errors_only;
+ struct dpni_queue_cfg queue_cfg;
+};
+
+/**
+ * dpni_set_tx_conf() - Set Tx confirmation and error queue configuration
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @flow_id: The sender's flow ID, as returned by the
+ * dpni_set_tx_flow() function;
+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf
+ * @cfg: Queue configuration
+ *
+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or
+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation,
+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF';
+ * i.e. only serve the common tx-conf-err queue;
+ * if 'DPNI_OPT_TX_CONF_DISABLED' was selected, only error frames are reported
+ * back - successfully transmitted frames are not confirmed. Otherwise, all
+ * transmitted frames are sent for confirmation.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_tx_conf(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint16_t flow_id,
+ const struct dpni_tx_conf_cfg *cfg);
+
+/**
+ * struct dpni_tx_conf_attr - Structure representing Tx conf attributes
+ * @errors_only: '1' if only error frames are reported back; '0' if all
+ * transmitted frames are confirmed
+ * @queue_attr: Queue attributes
+ */
+struct dpni_tx_conf_attr {
+ int errors_only;
+ struct dpni_queue_attr queue_attr;
+};
+
+/**
+ * dpni_get_tx_conf() - Get Tx confirmation and error queue attributes
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @flow_id: The sender's flow ID, as returned by the
+ * dpni_set_tx_flow() function;
+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf
+ * @attr: Returned tx-conf attributes
+ *
+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or
+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation,
+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF';
+ * i.e. only serve the common tx-conf-err queue;
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_tx_conf(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint16_t flow_id,
+ struct dpni_tx_conf_attr *attr);
/**
* dpni_set_rx_flow() - Set Rx flow configuration
* @mc_io: Pointer to MC portal's I/O object
/* DPRC Version */
#define DPRC_VER_MAJOR 5
-#define DPRC_VER_MINOR 0
+#define DPRC_VER_MINOR 1
/* Command IDs */
#define DPRC_CMDID_CLOSE 0x800
MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\
MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\
MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\
+ MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \
+ MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\
+ MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\
+ MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\
+ MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\
+ MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\
+ MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\
+ MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\
+ MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\
+ MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\
+ MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\
+ MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\
+ MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\
+ MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\
+ MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\
+ MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\
+ MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\
+ MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\
+ MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\
+ MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\
+ MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\
+ MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\
+ MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\
+ MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\
+ MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\
+ MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\
+ MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\
+ MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\
+ MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\
+ MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\
+ MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\
+ MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\
+ MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\
+ MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\
+ MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\
+ MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\
+ MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\
+ MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\
+ MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\
+ MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\
+ MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\
+ MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\
+ MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\
+ MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\
+ MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\
+ MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\
+ MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\
+ MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\
+ MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \
+do { \
+ MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \
+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \
+ MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \
+ MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \
+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\
+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\
+ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\
+ MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \
MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\
MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\
MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\
*/
#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008
-/* IOMMU bypass - indicates whether objects of this container are permitted
- * to bypass the IOMMU.
- */
-#define DPRC_CFG_OPT_IOMMU_BYPASS 0x00000010
-/* AIOP - Indicates that container belongs to AIOP. */
+/* AIOP - Indicates that container belongs to AIOP. */
#define DPRC_CFG_OPT_AIOP 0x00000020
+/* IRQ Config - Indicates that the container allowed to configure its IRQs.*/
+#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040
+
/**
* struct dprc_cfg - Container configuration options
* @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free
/* Plugged state - Indicates that the object is plugged */
#define DPRC_OBJ_STATE_PLUGGED 0x00000002
+/**
+ * Shareability flag - Object flag indicating no memory shareability.
+ * the object generates memory accesses that are non coherent with other
+ * masters;
+ * user is responsible for proper memory handling through IOMMU configuration.
+ */
+#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
+
/**
* struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
* @type: Type of object: NULL terminated string
* @region_count: Number of mappable regions supported by the object
* @state: Object state: combination of DPRC_OBJ_STATE_ states
* @label: Object label
+ * @flags: Object's flags
*/
struct dprc_obj_desc {
char type[16];
uint8_t region_count;
uint32_t state;
char label[16];
+ uint16_t flags;
};
/**
* @token: Token of DPRC object
* @endpoint1: Endpoint 1 configuration parameters
* @endpoint2: Returned endpoint 2 configuration parameters
-* @state: Returned link state: 1 - link is up, 0 - link is down
+* @state: Returned link state:
+* 1 - link is up;
+* 0 - link is down;
+* -1 - no connection (endpoint2 information is irrelevant)
*
* Return: '0' on Success; -ENAVAIL if connection does not exist.
*/
#define MC_CMD_HDR_READ_TOKEN(_hdr) \
((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S))
+#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \
+ ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg)))
+
#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \
- ((_ext)[_param] |= mc_enc((_offset), (_width), _arg))
+ (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width)))
#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
#define SDRAM_CFG2_ODT_ONLY_READ 2
#define SDRAM_CFG2_ODT_ALWAYS 3
+#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
#define TIMING_CFG_2_CPO_MASK 0x0F800000
#if defined(CONFIG_SYS_FSL_DDR_VER) && \
*/
struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */
- u32 ehdrloc; /* ESBC client location */
+ uintptr_t ehdrloc; /* ESBC Header location */
+ uintptr_t img_addr; /* ESBC Image Location */
+ uint32_t img_size; /* ESBC Image Size */
};
-int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[]);
+int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
+ uintptr_t img_loc);
int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[]);
int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[]);
+int fsl_check_boot_mode_secure(void);
+int fsl_setenv_chain_of_trust(void);
#endif
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
int armada100_fec_register(unsigned long base_addr);
-int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
- unsigned long dma_addr);
-int xilinx_emaclite_of_init(const void *blob);
-int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
- int txpp, int rxpp);
int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
unsigned long ctrl_addr);
/*
projects / project / bcm63xx / u-boot.git / commitdiff