-From 93e42b137d18a96dfdcb84cc154a0396b494c123 Mon Sep 17 00:00:00 2001
+From ffd7ee4fbd69d477a2156d9cba6ae80434a4c894 Mon Sep 17 00:00:00 2001
From: Xingyu Wu <xingyu.wu@starfivetech.com>
Date: Tue, 14 Mar 2023 17:16:07 +0800
-Subject: [PATCH 034/129] clk: starfive: jh7110-sys: Modify PLL clocks source
+Subject: [PATCH 034/122] clk: starfive: jh7110-sys: Modify PLL clocks source
Modify PLL clocks source to be got from dts instead of
the fixed factor clocks.
2 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
-index e306edf4d..903a5097c 100644
+index e306edf4defa..903a5097c642 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS
help
Say yes here to support the system clock controller on the
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
-index 851b93d0f..d46c7a3b7 100644
+index 851b93d0f371..d46c7a3b782d 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -404,29 +404,6 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
clk->hw.init = &init;
--
-2.25.1
+2.20.1