ipq806x: convert each device to DSA implementation
[openwrt/staging/svanheule.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8064-g10.dts
index 45efb2b46fd0eb4f6a91d63fe1c427c70e42dce6..6795e8fa4fb33f889c709e56a96aa05246011b0d 100644 (file)
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
-#include "qcom-ipq8064-v2.0.dtsi"
+#include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
        pinctrl-0 = <&mdio0_pins>;
        pinctrl-names = "default";
 
-       ethernet-phy@0 {
-               reg = <0>;
-               qca,ar8327-initvals = <
-                       0x00004 0x7600000   /* PAD0_MODE */
-                       0x00008 0x1000000   /* PAD5_MODE */
-                       0x0000c 0x80        /* PAD6_MODE */
-                       0x000e4 0x6a545     /* MAC_POWER_SEL */
-                       0x000e0 0xc74164de  /* SGMII_CTRL */
-                       0x0007c 0x4e        /* PORT0_STATUS */
-                       0x00094 0x4e        /* PORT6_STATUS */
-                       >;
+       switch@10 {
+               compatible = "qca,qca8337";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x10>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               label = "cpu";
+                               ethernet = <&gmac1>;
+                               phy-mode = "rgmii";
+                               tx-internal-delay-ps = <1000>;
+                               rx-internal-delay-ps = <1000>;
+
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               label = "wan";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port1>;
+                       };
+
+                       port@2 {
+                               reg = <2>;
+                               label = "lan1";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port2>;
+                       };
+
+                       port@3 {
+                               reg = <3>;
+                               label = "lan2";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port3>;
+                       };
+
+                       port@4 {
+                               reg = <4>;
+                               label = "lan3";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port4>;
+                       };
+
+                       port@5 {
+                               reg = <5>;
+                               label = "lan4";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port5>;
+                       };
+
+                       /*
+                       port@6 {
+                               reg = <0>;
+                               label = "cpu";
+                               ethernet = <&gmac2>;
+                               phy-mode = "rgmii";
+
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                                       pause;
+                                       asym-pause;
+                               };
+                       };
+                       */
+               };
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       phy_port1: phy@0 {
+                               reg = <0>;
+                       };
+
+                       phy_port2: phy@1 {
+                               reg = <1>;
+                       };
+
+                       phy_port3: phy@2 {
+                               reg = <2>;
+                       };
+
+                       phy_port4: phy@3 {
+                               reg = <3>;
+                       };
+
+                       phy_port5: phy@4 {
+                               reg = <4>;
+                       };
+               };
        };
 };
 
-&nand_controller {
+&nand {
        status = "okay";
 
-       pinctrl-0 = <&nand_pins>;
-       pinctrl-names = "default";
-
        nand@0 {
                reg = <0>;
                compatible = "qcom,nandcs";
                nand-bus-width = <8>;
                nand-ecc-step-size = <512>;
 
+               nand-is-boot-medium;
+               qcom,boot-partitions = <0x0 0x1200000>;
+
                partitions {
                        compatible = "qcom,smem-part";
                };
 
 &pcie0 {
        status = "okay";
+
+       bridge@0,0 {
+               reg = <0x00000000 0 0 0 0>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               ranges;
+
+               wifi5g: wifi@1,0 {
+                       reg = <0x00010000 0 0 0 0>;
+                       compatible = "qcom,ath10k";
+                       qcom,ath10k-calibration-variant = "ASRock-G10";
+               };
+       };
 };
 
 &pcie1 {
        status = "okay";
+
+       bridge@0,0 {
+               reg = <0x00000000 0 0 0 0>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               ranges;
+
+               wifi2g: wifi@1,0 {
+                       reg = <0x00010000 0 0 0 0>;
+                       compatible = "qcom,ath10k";
+                       qcom,ath10k-calibration-variant = "ASRock-G10";
+               };
+       };
 };
 
 &qcom_pinmux {
        pinctrl-names = "default";
 };
 
+&hs_phy_0 {
+       status = "okay";
+};
+
+&ss_phy_0 {
+       status = "okay";
+};
+
 &usb3_0 {
        status = "okay";
 };
 
+&hs_phy_1 {
+       status = "okay";
+};
+
+&ss_phy_1 {
+       status = "okay";
+};
+
 &usb3_1 {
        status = "okay";
 };