Merge changes from topic "intel-plat-refactor" into integration

[project/bcm63xx/atf.git] / plat / intel / soc / stratix10 / bl31_plat_setup.c

diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index d81d5df5ab556155c9386c697fc2ea0567e2a8a1..7c9833b338b62b5fd050c3c26e8fa4526d23aa29 100644 (file)
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -110,16 +110,21 @@ void bl31_platform_setup(void)
 }
 
 const mmap_region_t plat_stratix10_mmap[] = {
-       MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
-       MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
-       MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS),
+       MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
+               MT_MEMORY | MT_RW | MT_NS),
+       MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
+               MT_DEVICE | MT_RW | MT_NS),
+       MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
+               MT_DEVICE | MT_RW | MT_SECURE),
        MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
                MT_NON_CACHEABLE | MT_RW | MT_SECURE),
        MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
                MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
-       MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
-       {0},
+       MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
+               MT_DEVICE | MT_RW | MT_NS),
+       MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
+               MT_DEVICE | MT_RW | MT_NS),
+       {0}
 };
 
 /*******************************************************************************
@@ -141,7 +146,7 @@ void bl31_plat_arch_setup(void)
                        BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
                        MT_DEVICE | MT_RW | MT_SECURE),
 #endif
-               {0},
+               {0}
        };
 
        setup_page_tables(bl_regions, plat_stratix10_mmap);