uboot-rockchip: update to v2021.01

[openwrt/staging/svanheule.git] / package / boot / uboot-rockchip / src / of-platdata / nanopi-r2s-rk3328 / dt-structs-gen.h

diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h
index 88291627b8c500548fd27f97ea3155767f61aaba..6dcb4c1f1bc98484291e6254af38a1d43cdf4d8e 100644 (file)
--- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h
+++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h
@@ -6,6 +6,18 @@
 
 #include <stdbool.h>
 #include <linux/libfdt.h>
+struct dtd_ns16550_serial {
+       fdt32_t         clock_frequency;
+       struct phandle_1_arg clocks[2];
+       const char *    dma_names[2];
+       fdt32_t         dmas[4];
+       fdt32_t         interrupts[3];
+       fdt32_t         pinctrl_0;
+       const char *    pinctrl_names;
+       fdt64_t         reg[2];
+       fdt32_t         reg_io_width;
+       fdt32_t         reg_shift;
+};
 struct dtd_regulator_fixed {
        fdt32_t         gpio[3];
        fdt32_t         pinctrl_0;
@@ -22,15 +34,7 @@ struct dtd_rockchip_gpio_bank {
        fdt32_t         interrupts[3];
        fdt64_t         reg[2];
 };
-struct dtd_rockchip_rk3328_cru {
-       fdt64_t         reg[2];
-       fdt32_t         rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
-       fdt64_t         reg[12];
-       fdt32_t         rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_dw_mshc {
+struct dtd_rockchip_rk3288_dw_mshc {
        fdt32_t         bus_width;
        bool            cap_mmc_highspeed;
        bool            cap_sd_highspeed;
@@ -46,6 +50,14 @@ struct dtd_rockchip_rk3328_dw_mshc {
        fdt32_t         vmmc_supply;
        fdt32_t         vqmmc_supply;
 };
+struct dtd_rockchip_rk3328_cru {
+       fdt64_t         reg[2];
+       fdt32_t         rockchip_grf;
+};
+struct dtd_rockchip_rk3328_dmc {
+       fdt64_t         reg[12];
+       fdt32_t         rockchip_sdram_params[196];
+};
 struct dtd_rockchip_rk3328_grf {
        fdt64_t         reg[2];
 };
@@ -53,20 +65,3 @@ struct dtd_rockchip_rk3328_pinctrl {
        bool            ranges;
        fdt32_t         rockchip_grf;
 };
-struct dtd_rockchip_rk3328_uart {
-       fdt32_t         clock_frequency;
-       struct phandle_1_arg clocks[2];
-       const char *    dma_names[2];
-       fdt32_t         dmas[4];
-       fdt32_t         interrupts[3];
-       fdt32_t         pinctrl_0;
-       const char *    pinctrl_names;
-       fdt64_t         reg[2];
-       fdt32_t         reg_io_width;
-       fdt32_t         reg_shift;
-};
-#define dtd_syscon dtd_rockchip_rk3328_cru
-#define dtd_simple_mfd dtd_rockchip_rk3328_grf
-#define dtd_snps_dw_apb_uart dtd_rockchip_rk3328_uart
-#define dtd_rockchip_cru dtd_rockchip_rk3328_cru
-#define dtd_rockchip_rk3288_dw_mshc dtd_rockchip_rk3328_dw_mshc