Explicitly disable the SPME bit in MDCR_EL3

[project/bcm63xx/atf.git] / include / arch / aarch64 / el3_common_macros.S

diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 22b32b491c53df0b0b4c20dc88375e28065f1753..378e827ce1c57427d00b477fa785151ebb14fab1 100644 (file)
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -113,14 +113,51 @@
         *  prohibited in Secure state. This bit is RES0 in versions of the
         *  architecture earlier than ARMv8.5, setting it to 1 doesn't have any
         *  effect on them.
+        *
+        * MDCR_EL3.SPME: Set to zero so that event counting by the programmable
+        *  counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2
+        *  Debug is not implemented this bit does not have any effect on the
+        *  counters unless there is support for the implementation defined
+        *  authentication interface ExternalSecureNoninvasiveDebugEnabled().
         * ---------------------------------------------------------------------
         */
        mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
-                     MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) \
-                   & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
+                     MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \
+                   ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \
+                     MDCR_TPM_BIT))
 
        msr     mdcr_el3, x0
 
+       /* ---------------------------------------------------------------------
+        * Initialise PMCR_EL0 setting all fields rather than relying
+        * on hw. Some fields are architecturally UNKNOWN on reset.
+        *
+        * PMCR_EL0.LP: Set to one so that event counter overflow, that
+        *  is recorded in PMOVSCLR_EL0[0-30], occurs on the increment
+        *  that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU
+        *  is implemented. This bit is RES0 in versions of the architecture
+        *  earlier than ARMv8.5, setting it to 1 doesn't have any effect
+        *  on them.
+        *
+        * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
+        *  is recorded in PMOVSCLR_EL0[31], occurs on the increment
+        *  that changes PMCCNTR_EL0[63] from 1 to 0.
+        *
+        * PMCR_EL0.DP: Set to one so that the cycle counter,
+        *  PMCCNTR_EL0 does not count when event counting is prohibited.
+        *
+        * PMCR_EL0.X: Set to zero to disable export of events.
+        *
+        * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
+        *  counts on every clock cycle.
+        * ---------------------------------------------------------------------
+        */
+       mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \
+                     PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \
+                   ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT))
+
+       msr     pmcr_el0, x0
+
        /* ---------------------------------------------------------------------
         * Enable External Aborts and SError Interrupts now that the exception
         * vectors have been setup.
@@ -303,7 +340,7 @@
         * ---------------------------------------------------------------------
         */
        .if \_init_c_runtime
-#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
+#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE)
                /* -------------------------------------------------------------
                 * Invalidate the RW memory used by the BL31 image. This
                 * includes the data and NOBITS sections. This is done to
@@ -336,7 +373,7 @@
                bl      zeromem
 #endif
 
-#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM)
+#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
                adrp    x0, __DATA_RAM_START__
                add     x0, x0, :lo12:__DATA_RAM_START__
                adrp    x1, __DATA_ROM_START__