1 From e2078ae0c559b6ac91db19262b56d8cf334354cb Mon Sep 17 00:00:00 2001
2 From: Andre Przywara <andre.przywara@arm.com>
3 Date: Mon, 12 Sep 2022 00:03:22 +0100
4 Subject: [PATCH 5001/5006] dt-bindings: phy: Add special clock for Allwinner
7 The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
8 some resources from port 2's PHY and HCI IP. In particular the PMU clock
9 for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
10 register of port 2. To allow each USB port to be controlled
11 independently of port 2, we need a handle to that particular PMU clock
12 in the *PHY* node, as the HCI and PHY part might be handled by separate
15 Add that clock to the requirements of the H616 PHY binding, so that a
16 PHY driver can apply the quirk in isolation, without requiring help from
19 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
21 .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
22 1 file changed, 26 insertions(+)
24 --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
25 +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
26 @@ -36,18 +36,22 @@ properties:
32 - description: USB OTG PHY bus clock
33 - description: USB Host 0 PHY bus clock
34 - description: USB Host 1 PHY bus clock
35 - description: USB Host 2 PHY bus clock
36 + - description: PMU clock for host port 2
49 @@ -96,6 +100,28 @@ required:
59 + - allwinner,sun50i-h616-usb-phy
75 additionalProperties: false