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Revert "rtl83xx: add biot's spi driver"
[openwrt/staging/blogic.git] / target / linux / rtl838x / files-5.4 / drivers / mtd / spi-nor / rtl838x-nor.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/device.h>
4 #include <linux/init.h>
5 #include <linux/module.h>
6 #include <linux/mutex.h>
7 #include <linux/of.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/spi-nor.h>
14
15 #include "rtl838x-spi.h"
16 #include <asm/mach-rtl838x/mach-rtl83xx.h>
17
18 extern struct rtl83xx_soc_info soc_info;
19
20 struct rtl838x_nor {
21 struct spi_nor nor;
22 struct device *dev;
23 volatile void __iomem *base;
24 bool fourByteMode;
25 u32 chipSize;
26 uint32_t flags;
27 uint32_t io_status;
28 };
29
30 static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor)
31 {
32 /* Needed because of MMU constraints */
33 SPI_WAIT_READY;
34 spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1
35 spi_w32w(0, SFCSR); //activate CS0,CS1
36 spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1
37
38 return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT)
39 : ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL);
40 }
41
42 static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor)
43 {
44 uint32_t sfcsr, sfdr;
45
46 sfcsr = spi_prep(rtl838x_nor);
47 sfdr = (SPINOR_OP_RDSR)<<24;
48
49 pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr);
50 pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4);
51 spi_w32w(sfcsr, SFCSR);
52 spi_w32w(sfdr, SFDR);
53 spi_w32_mask(0, SPI_LEN4, SFCSR);
54 SPI_WAIT_READY;
55
56 return spi_r32(SFDR);
57 }
58
59 static void spi_write_disable(struct rtl838x_nor *rtl838x_nor)
60 {
61 uint32_t sfcsr, sfdr;
62
63 sfcsr = spi_prep(rtl838x_nor);
64 sfdr = (SPINOR_OP_WRDI) << 24;
65 spi_w32w(sfcsr, SFCSR);
66 spi_w32w(sfdr, SFDR);
67 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
68
69 spi_prep(rtl838x_nor);
70 }
71
72 static void spi_write_enable(struct rtl838x_nor *rtl838x_nor)
73 {
74 uint32_t sfcsr, sfdr;
75
76 sfcsr = spi_prep(rtl838x_nor);
77 sfdr = (SPINOR_OP_WREN) << 24;
78 spi_w32w(sfcsr, SFCSR);
79 spi_w32w(sfdr, SFDR);
80 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
81
82 spi_prep(rtl838x_nor);
83 }
84
85 static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable)
86 {
87 uint32_t sfcsr, sfdr;
88
89 sfcsr = spi_prep(rtl838x_nor);
90 if (enable)
91 sfdr = (SPINOR_OP_EN4B) << 24;
92 else
93 sfdr = (SPINOR_OP_EX4B) << 24;
94
95 spi_w32w(sfcsr, SFCSR);
96 spi_w32w(sfdr, SFDR);
97 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
98
99 spi_prep(rtl838x_nor);
100 }
101
102 static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
103 {
104 int res = 3;
105 u32 reg;
106
107 sw_w32(0x3, RTL838X_INT_RW_CTRL);
108 if (!sw_r32(RTL838X_EXT_VERSION)) {
109 if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
110 res = 4;
111 } else {
112 reg = sw_r32(RTL838X_PLL_CML_CTRL);
113 if ((reg & (1 << 30)) && (reg & (1 << 31)))
114 res = 4;
115 if ((!(reg & (1 << 30)))
116 && sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
117 res = 4;
118 }
119 sw_w32(0x0, RTL838X_INT_RW_CTRL);
120 return res;
121 }
122
123 static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
124 {
125 if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9))
126 return 4;
127 return 3;
128 }
129
130 ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
131 size_t length, u_char *buffer, uint8_t command)
132 {
133 uint32_t sfcsr, sfdr;
134 uint32_t len = length;
135
136 sfcsr = spi_prep(rtl838x_nor);
137 sfdr = command << 24;
138
139 /* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/
140 sfcsr |= SPI_LEN4;
141 sfdr |= from;
142
143 spi_w32w(sfcsr, SFCSR);
144 spi_w32w(sfdr, SFDR);
145
146 /* Read Data, 4 bytes at a time */
147 while (length >= 4) {
148 SPI_WAIT_READY;
149 *((uint32_t *) buffer) = spi_r32(SFDR);
150 buffer += 4;
151 length -= 4;
152 }
153
154 /* The rest needs to be read 1 byte a time */
155 sfcsr &= SPI_LEN_INIT|SPI_LEN1;
156 SPI_WAIT_READY;
157 spi_w32w(sfcsr, SFCSR);
158 while (length > 0) {
159 SPI_WAIT_READY;
160 *(buffer) = spi_r32(SFDR) >> 24;
161 buffer++;
162 length--;
163 }
164 return len;
165 }
166
167 /*
168 * Do fast read in 3 or 4 Byte addressing mode
169 */
170 static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
171 size_t length, u_char *buffer, uint8_t command)
172 {
173 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
174 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
175 uint32_t sfcsr;
176 uint32_t len = length;
177
178 pr_debug("Fast read from %llx, len %x, shift %d\n",
179 from, sfcsr_addr_len, sfdr_addr_shift);
180 sfcsr = spi_prep(rtl838x_nor);
181
182 /* Send read command */
183 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
184 spi_w32w(command << 24, SFDR);
185
186 /* Send address */
187 spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR);
188 spi_w32w(from << sfdr_addr_shift, SFDR);
189
190 /* Dummy cycles */
191 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
192 spi_w32w(0, SFDR);
193
194 /* Start reading */
195 spi_w32w(sfcsr | SPI_LEN4, SFCSR);
196
197 /* Read Data, 4 bytes at a time */
198 while (length >= 4) {
199 SPI_WAIT_READY;
200 *((uint32_t *) buffer) = spi_r32(SFDR);
201 buffer += 4;
202 length -= 4;
203 }
204
205 /* The rest needs to be read 1 byte a time */
206 sfcsr &= SPI_LEN_INIT|SPI_LEN1;
207 SPI_WAIT_READY;
208 spi_w32w(sfcsr, SFCSR);
209 while (length > 0) {
210 SPI_WAIT_READY;
211 *(buffer) = spi_r32(SFDR) >> 24;
212 buffer++;
213 length--;
214 }
215 return len;
216
217 }
218
219 /*
220 * Do write (Page Programming) in 3 or 4 Byte addressing mode
221 */
222 static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to,
223 size_t length, const u_char *buffer,
224 uint8_t command)
225 {
226 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
227 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
228 uint32_t sfcsr;
229 uint32_t len = length;
230
231 pr_debug("Write to %llx, len %x, shift %d\n",
232 to, sfcsr_addr_len, sfdr_addr_shift);
233 sfcsr = spi_prep(rtl838x_nor);
234
235 /* Send write command, command IO-width is 1 (bit 25/26) */
236 spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
237 spi_w32w(command << 24, SFDR);
238
239 /* Send address */
240 spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
241 spi_w32w(to << sfdr_addr_shift, SFDR);
242
243 /* Write Data, 1 byte at a time, if we are not 4-byte aligned */
244 if (((long)buffer) % 4) {
245 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
246 while (length > 0 && (((long)buffer) % 4)) {
247 SPI_WAIT_READY;
248 spi_w32(*(buffer) << 24, SFDR);
249 buffer += 1;
250 length -= 1;
251 }
252 }
253
254 /* Now we can write 4 bytes at a time */
255 SPI_WAIT_READY;
256 spi_w32w(sfcsr | SPI_LEN4, SFCSR);
257 while (length >= 4) {
258 SPI_WAIT_READY;
259 spi_w32(*((uint32_t *)buffer), SFDR);
260 buffer += 4;
261 length -= 4;
262 }
263
264 /* Final bytes might need to be written 1 byte at a time, again */
265 SPI_WAIT_READY;
266 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
267 while (length > 0) {
268 SPI_WAIT_READY;
269 spi_w32(*(buffer) << 24, SFDR);
270 buffer++;
271 length--;
272 }
273 return len;
274 }
275
276 static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len,
277 const u_char *buffer)
278 {
279 int ret = 0;
280 uint32_t offset = 0;
281 struct rtl838x_nor *rtl838x_nor = nor->priv;
282 size_t l = len;
283 uint8_t cmd = SPINOR_OP_PP;
284
285 /* Do write in 4-byte mode on large Macronix chips */
286 if (rtl838x_nor->fourByteMode) {
287 cmd = SPINOR_OP_PP_4B;
288 spi_4b_set(rtl838x_nor, true);
289 }
290
291 pr_debug("In %s %8x to: %llx\n", __func__,
292 (unsigned int) rtl838x_nor, to);
293
294 while (l >= SPI_MAX_TRANSFER_SIZE) {
295 while
296 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
297 do {
298 spi_write_enable(rtl838x_nor);
299 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
300 ret = rtl838x_do_4b_write(rtl838x_nor, to + offset,
301 SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
302 l -= SPI_MAX_TRANSFER_SIZE;
303 offset += SPI_MAX_TRANSFER_SIZE;
304 }
305
306 if (l > 0) {
307 while
308 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
309 do {
310 spi_write_enable(rtl838x_nor);
311 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
312 ret = rtl838x_do_4b_write(rtl838x_nor, to+offset,
313 len, buffer+offset, cmd);
314 }
315
316 return len;
317 }
318
319 static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from,
320 size_t length, u_char *buffer)
321 {
322 uint32_t offset = 0;
323 uint8_t cmd = SPINOR_OP_READ_FAST;
324 size_t l = length;
325 struct rtl838x_nor *rtl838x_nor = nor->priv;
326
327 /* Do fast read in 3, or 4-byte mode on large Macronix chips */
328 if (rtl838x_nor->fourByteMode) {
329 cmd = SPINOR_OP_READ_FAST_4B;
330 spi_4b_set(rtl838x_nor, true);
331 }
332
333 /* TODO: do timeout and return error */
334 pr_debug("Waiting for pending writes\n");
335 while
336 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
337 do {
338 spi_write_enable(rtl838x_nor);
339 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
340
341 pr_debug("cmd is %d\n", cmd);
342 pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__,
343 from, (u32)buffer, (u32)cmd, length);
344
345 while (l >= SPI_MAX_TRANSFER_SIZE) {
346 rtl838x_do_4bf_read(rtl838x_nor, from + offset,
347 SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
348 l -= SPI_MAX_TRANSFER_SIZE;
349 offset += SPI_MAX_TRANSFER_SIZE;
350 }
351
352 if (l > 0)
353 rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd);
354
355 return length;
356 }
357
358 static int rtl838x_erase(struct spi_nor *nor, loff_t offs)
359 {
360 struct rtl838x_nor *rtl838x_nor = nor->priv;
361 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
362 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
363 uint32_t sfcsr;
364 uint8_t cmd = SPINOR_OP_SE;
365
366 pr_debug("Erasing sector at %llx\n", offs);
367
368 /* Do erase in 4-byte mode on large Macronix chips */
369 if (rtl838x_nor->fourByteMode) {
370 cmd = SPINOR_OP_SE_4B;
371 spi_4b_set(rtl838x_nor, true);
372 }
373 /* TODO: do timeout and return error */
374 while
375 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
376 do {
377 spi_write_enable(rtl838x_nor);
378 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
379
380 sfcsr = spi_prep(rtl838x_nor);
381
382 /* Send erase command, command IO-width is 1 (bit 25/26) */
383 spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
384 spi_w32w(cmd << 24, SFDR);
385
386 /* Send address */
387 spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
388 spi_w32w(offs << sfdr_addr_shift, SFDR);
389
390 return 0;
391 }
392
393 static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
394 {
395 int length = len;
396 u8 *buffer = buf;
397 uint32_t sfcsr, sfdr;
398 struct rtl838x_nor *rtl838x_nor = nor->priv;
399
400 pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len);
401
402 sfcsr = spi_prep(rtl838x_nor);
403 sfdr = opcode << 24;
404
405 sfcsr |= SPI_LEN1;
406
407 spi_w32w(sfcsr, SFCSR);
408 spi_w32w(sfdr, SFDR);
409
410 while (length > 0) {
411 SPI_WAIT_READY;
412 *(buffer) = spi_r32(SFDR) >> 24;
413 buffer++;
414 length--;
415 }
416
417 return len;
418 }
419
420 static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
421 {
422 uint32_t sfcsr, sfdr;
423 struct rtl838x_nor *rtl838x_nor = nor->priv;
424
425 pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len);
426 sfcsr = spi_prep(rtl838x_nor);
427 sfdr = opcode << 24;
428
429 if (len == 1) { /* SPINOR_OP_WRSR */
430 sfdr |= buf[0];
431 sfcsr |= SPI_LEN2;
432 }
433 spi_w32w(sfcsr, SFCSR);
434 spi_w32w(sfdr, SFDR);
435 return 0;
436 }
437
438 static int spi_enter_sio(struct spi_nor *nor)
439 {
440 uint32_t sfcsr, sfcr2, sfdr;
441 uint32_t ret = 0, reg = 0, size_bits;
442 struct rtl838x_nor *rtl838x_nor = nor->priv;
443
444 pr_debug("In %s\n", __func__);
445 rtl838x_nor->io_status = 0;
446 sfdr = SPI_C_RSTQIO << 24;
447 sfcsr = spi_prep(rtl838x_nor);
448
449 reg = spi_r32(SFCR2);
450 pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg),
451 (reg & SFCR2_RDOPT));
452 size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7);
453
454 sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits
455 | (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0)
456 | SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4)
457 | SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST);
458 pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg));
459
460 SPI_WAIT_READY;
461 spi_w32w(sfcr2, SFCR2);
462 spi_w32w(sfcsr, SFCSR);
463 spi_w32w(sfdr, SFDR);
464
465 spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2);
466 rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK;
467 rtl838x_nor->io_status |= CIO1;
468
469 spi_prep(rtl838x_nor);
470
471 return ret;
472 }
473
474 int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name)
475 {
476 static const struct spi_nor_hwcaps hwcaps = {
477 .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP
478 | SNOR_HWCAPS_READ_FAST
479 };
480
481 struct rtl838x_nor *rtl838x_nor = nor->priv;
482
483 pr_debug("In %s\n", __func__);
484
485 spi_w32_mask(0, SFCR_EnableWBO, SFCR);
486 spi_w32_mask(0, SFCR_EnableRBO, SFCR);
487
488 rtl838x_nor->flags = CS0 | R_MODE;
489
490 spi_nor_scan(nor, NULL, &hwcaps);
491 pr_debug("------------- Got size: %llx\n", nor->mtd.size);
492
493 return 0;
494 }
495
496 int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor,
497 struct device_node *flash_node)
498 {
499 int ret;
500 struct spi_nor *nor;
501
502 pr_info("%s called\n", __func__);
503 nor = &rtl838x_nor->nor;
504 nor->dev = rtl838x_nor->dev;
505 nor->priv = rtl838x_nor;
506 spi_nor_set_flash_node(nor, flash_node);
507
508 nor->read_reg = rtl838x_nor_read_reg;
509 nor->write_reg = rtl838x_nor_write_reg;
510 nor->read = rtl838x_nor_read;
511 nor->write = rtl838x_nor_write;
512 nor->erase = rtl838x_erase;
513 nor->mtd.name = "rtl838x_nor";
514 nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B
515 : SPINOR_OP_SE;
516 /* initialized with NULL */
517 ret = rtl838x_spi_nor_scan(nor, NULL);
518 if (ret)
519 return ret;
520
521 spi_enter_sio(nor);
522 spi_write_disable(rtl838x_nor);
523
524 ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0);
525 return ret;
526 }
527
528 static int rtl838x_nor_drv_probe(struct platform_device *pdev)
529 {
530 struct device_node *flash_np;
531 struct resource *res;
532 int ret;
533 struct rtl838x_nor *rtl838x_nor;
534 int addrMode;
535
536 pr_info("Initializing rtl838x_nor_driver\n");
537 if (!pdev->dev.of_node) {
538 dev_err(&pdev->dev, "No DT found\n");
539 return -EINVAL;
540 }
541
542 rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL);
543 if (!rtl838x_nor)
544 return -ENOMEM;
545 platform_set_drvdata(pdev, rtl838x_nor);
546
547 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
548 rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res);
549 if (IS_ERR((void *)rtl838x_nor->base))
550 return PTR_ERR((void *)rtl838x_nor->base);
551
552 pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base);
553 rtl838x_nor->dev = &pdev->dev;
554
555 /* only support one attached flash */
556 flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
557 if (!flash_np) {
558 dev_err(&pdev->dev, "no SPI flash device to configure\n");
559 ret = -ENODEV;
560 goto nor_free;
561 }
562
563 /* Get the 3/4 byte address mode as configure by bootloader */
564 if (soc_info.family == RTL8390_FAMILY_ID)
565 addrMode = rtl8390_get_addr_mode(rtl838x_nor);
566 else
567 addrMode = rtl838x_get_addr_mode(rtl838x_nor);
568 pr_info("Address mode is %d bytes\n", addrMode);
569 if (addrMode == 4)
570 rtl838x_nor->fourByteMode = true;
571
572 ret = rtl838x_nor_init(rtl838x_nor, flash_np);
573
574 nor_free:
575 return ret;
576 }
577
578 static int rtl838x_nor_drv_remove(struct platform_device *pdev)
579 {
580 /* struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */
581 return 0;
582 }
583
584 static const struct of_device_id rtl838x_nor_of_ids[] = {
585 { .compatible = "realtek,rtl838x-nor"},
586 { /* sentinel */ }
587 };
588 MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids);
589
590 static struct platform_driver rtl838x_nor_driver = {
591 .probe = rtl838x_nor_drv_probe,
592 .remove = rtl838x_nor_drv_remove,
593 .driver = {
594 .name = "rtl838x-nor",
595 .pm = NULL,
596 .of_match_table = rtl838x_nor_of_ids,
597 },
598 };
599
600 module_platform_driver(rtl838x_nor_driver);
601
602 MODULE_LICENSE("GPL v2");
603 MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver");
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