target/linux/rockchip/patches-6.6/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch

   1 From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001
   2 From: Shawn Lin <shawn.lin@rock-chips.com>
   3 Date: Thu, 2 Feb 2023 08:35:16 +0800
   4 Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for
   5  rockchip platform
   6
   7 For Rockchip platform, DLL bypass bit and start bit need to be set if
   8 DLL is not locked. And adjust pre-change delay to 0x3 for better signal
   9 test result.
  10
  11 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
  12 Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com
  13 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
  14 ---
  15  drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++----
  16  1 file changed, 9 insertions(+), 4 deletions(-)
  17
  18 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
  19 +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
  20 @@ -48,6 +48,7 @@
  21  #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL  29
  22  #define DWCMSHC_EMMC_DLL_START_POINT   16
  23  #define DWCMSHC_EMMC_DLL_INC           8
  24 +#define DWCMSHC_EMMC_DLL_BYPASS                BIT(24)
  25  #define DWCMSHC_EMMC_DLL_DLYENA                BIT(27)
  26  #define DLL_TXCLK_TAPNUM_DEFAULT       0x10
  27  #define DLL_TXCLK_TAPNUM_90_DEGREES    0xA
  28 @@ -60,6 +61,7 @@
  29  #define DLL_RXCLK_NO_INVERTER          1
  30  #define DLL_RXCLK_INVERTER             0
  31  #define DLL_CMDOUT_TAPNUM_90_DEGREES   0x8
  32 +#define DLL_RXCLK_ORI_GATE             BIT(31)
  33  #define DLL_CMDOUT_TAPNUM_FROM_SW      BIT(24)
  34  #define DLL_CMDOUT_SRC_CLK_NEG         BIT(28)
  35  #define DLL_CMDOUT_EN_SRC_CLK_NEG      BIT(29)
  36 @@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str
  37         sdhci_writel(host, extra, reg);
  38
  39         if (clock <= 52000000) {
  40 -               /* Disable DLL and reset both of sample and drive clock */
  41 -               sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
  42 -               sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
  43 +               /*
  44 +                * Disable DLL and reset both of sample and drive clock.
  45 +                * The bypass bit and start bit need to be set if DLL is not locked.
  46 +                */
  47 +               sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
  48 +               sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
  49                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
  50                 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
  51                 /*
  52 @@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str
  53         }
  54
  55         extra = 0x1 << 16 | /* tune clock stop en */
  56 -               0x2 << 17 | /* pre-change delay */
  57 +               0x3 << 17 | /* pre-change delay */
  58                 0x3 << 19;  /* post-change delay */
  59         sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
  60