2cda3c15a34f1f342e4e755c8ada5f4ff4741ce7
[openwrt/staging/adrian.git] / target / linux / realtek / dts / rtl8380_netgear_gigabit.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "rtl838x.dtsi"
4
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
7
8 / {
9 compatible = "realtek,rtl838x-soc";
10
11 chosen {
12 bootargs = "console=ttyS0,115200";
13 };
14
15 memory@0 {
16 device_type = "memory";
17 reg = <0x0 0x8000000>;
18 };
19
20 keys {
21 compatible = "gpio-keys-polled";
22 poll-interval = <20>;
23
24 mode {
25 label = "reset";
26 gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
27 linux,code = <KEY_RESTART>;
28 };
29 };
30 };
31
32 &gpio0 {
33 indirect-access-bus-id = <0>;
34 };
35
36 &spi0 {
37 status = "okay";
38
39 flash@0 {
40 compatible = "jedec,spi-nor";
41 reg = <0>;
42 spi-max-frequency = <50000000>;
43
44 partitions {
45 compatible = "fixed-partitions";
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 partition@0 {
50 label = "loader";
51 reg = <0x0000000 0x00e0000>;
52 read-only;
53 };
54
55 partition@e0000 {
56 label = "bdinfo";
57 reg = <0x00e0000 0x0010000>;
58 read-only;
59 };
60
61 partition@f0000 {
62 label = "sysinfo";
63 reg = <0x00f0000 0x0010000>;
64 read-only;
65 };
66
67 partition@100000 {
68 label = "jffs2_cfg";
69 reg = <0x0100000 0x0100000>;
70 read-only;
71 };
72
73 partition@200000 {
74 label = "jffs2_log";
75 reg = <0x0200000 0x0100000>;
76 read-only;
77 };
78
79 partition@300000 {
80 label = "firmware";
81 compatible = "openwrt,uimage", "denx,uimage";
82 openwrt,ih-magic = <0x4e474520>;
83 reg = <0x0300000 0x0e80000>;
84 };
85
86 partition@1180000 {
87 label = "runtime2";
88 reg = <0x1180000 0x0e80000>;
89 read-only;
90 };
91 };
92 };
93 };
94
95 &ethernet0 {
96 mdio: mdio-bus {
97 compatible = "realtek,rtl838x-mdio";
98 regmap = <&ethernet0>;
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 INTERNAL_PHY(8)
103 INTERNAL_PHY(9)
104 INTERNAL_PHY(10)
105 INTERNAL_PHY(11)
106 INTERNAL_PHY(12)
107 INTERNAL_PHY(13)
108 INTERNAL_PHY(14)
109 INTERNAL_PHY(15)
110 };
111 };
112
113 &switch0 {
114 ports {
115 #address-cells = <1>;
116 #size-cells = <0>;
117
118 SWITCH_PORT(8, 1, internal)
119 SWITCH_PORT(9, 2, internal)
120 SWITCH_PORT(10, 3, internal)
121 SWITCH_PORT(11, 4, internal)
122 SWITCH_PORT(12, 5, internal)
123 SWITCH_PORT(13, 6, internal)
124 SWITCH_PORT(14, 7, internal)
125 SWITCH_PORT(15, 8, internal)
126
127 port@28 {
128 ethernet = <&ethernet0>;
129 reg = <28>;
130 phy-mode = "internal";
131 fixed-link {
132 speed = <1000>;
133 full-duplex;
134 };
135 };
136 };
137 };