target/linux/ramips/dts/mt7621.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/clock/mt7621-clk.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/interrupt-controller/mips-gic.h>
   6 #include <dt-bindings/reset/mt7621-reset.h>
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11         compatible = "mediatek,mt7621-soc";
  12
  13         aliases {
  14                 serial0 = &uartlite;
  15         };
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "mips,mips1004Kc";
  24                         reg = <0>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "mips,mips1004Kc";
  30                         reg = <1>;
  31                 };
  32         };
  33
  34         cpuintc: cpuintc {
  35                 #address-cells = <0>;
  36                 #interrupt-cells = <1>;
  37                 interrupt-controller;
  38                 compatible = "mti,cpu-interrupt-controller";
  39         };
  40
  41         chosen {
  42                 bootargs = "console=ttyS0,57600";
  43         };
  44
  45         palmbus: palmbus@1e000000 {
  46                 compatible = "palmbus";
  47                 reg = <0x1e000000 0x100000>;
  48                 ranges = <0x0 0x1e000000 0x0fffff>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 sysc: syscon@0 {
  54                         compatible = "mediatek,mt7621-sysc", "syscon";
  55                         #clock-cells = <1>;
  56                         #reset-cells = <1>;
  57                         ralink,memctl = <&memc>;
  58                         clock-output-names = "xtal", "cpu", "bus",
  59                                              "50m", "125m", "150m",
  60                                              "250m", "270m";
  61                         reg = <0x0 0x100>;
  62                 };
  63
  64                 wdt: watchdog@100 {
  65                         compatible = "mediatek,mt7621-wdt";
  66                         reg = <0x100 0x100>;
  67                         mediatek,sysctl = <&sysc>;
  68                 };
  69
  70                 gpio: gpio@600 {
  71                         #gpio-cells = <2>;
  72                         #interrupt-cells = <2>;
  73                         compatible = "mediatek,mt7621-gpio";
  74                         gpio-controller;
  75                         gpio-ranges = <&pinctrl 0 0 95>;
  76                         interrupt-controller;
  77                         reg = <0x600 0x100>;
  78                         interrupt-parent = <&gic>;
  79                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  80                 };
  81
  82                 i2c: i2c@900 {
  83                         compatible = "mediatek,mt7621-i2c";
  84                         reg = <0x900 0x100>;
  85
  86                         clocks = <&sysc MT7621_CLK_I2C>;
  87                         clock-names = "i2c";
  88
  89                         resets = <&sysc MT7621_RST_I2C>;
  90                         reset-names = "i2c";
  91
  92                         #address-cells = <1>;
  93                         #size-cells = <0>;
  94
  95                         status = "disabled";
  96
  97                         pinctrl-names = "default";
  98                         pinctrl-0 = <&i2c_pins>;
  99                 };
 100
 101                 i2s: i2s@a00 {
 102                         compatible = "mediatek,mt7621-i2s";
 103                         reg = <0xa00 0x100>;
 104
 105                         clocks = <&sysc MT7621_CLK_I2S>;
 106
 107                         resets = <&sysc MT7621_RST_I2S>;
 108                         reset-names = "i2s";
 109
 110                         interrupt-parent = <&gic>;
 111                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 112
 113                         txdma-req = <2>;
 114                         rxdma-req = <3>;
 115
 116                         dmas = <&gdma 4>,
 117                                 <&gdma 6>;
 118                         dma-names = "tx", "rx";
 119
 120                         status = "disabled";
 121                 };
 122
 123                 systick: systick@500 {
 124                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 125                         reg = <0x500 0x10>;
 126
 127                         interrupt-parent = <&gic>;
 128                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 129                 };
 130
 131                 memc: memory-controller@5000 {
 132                         compatible = "mediatek,mt7621-memc", "syscon";
 133                         reg = <0x5000 0x1000>;
 134                 };
 135
 136                 uartlite: uartlite@c00 {
 137                         compatible = "ns16550a";
 138                         reg = <0xc00 0x100>;
 139
 140                         clocks = <&sysc MT7621_CLK_UART1>;
 141
 142                         resets = <&sysc MT7621_RST_UART1>;
 143
 144                         interrupt-parent = <&gic>;
 145                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 146
 147                         reg-shift = <2>;
 148                         reg-io-width = <4>;
 149                         no-loopback-test;
 150                 };
 151
 152                 uartlite2: uartlite2@d00 {
 153                         compatible = "ns16550a";
 154                         reg = <0xd00 0x100>;
 155
 156                         clocks = <&sysc MT7621_CLK_UART2>;
 157
 158                         resets = <&sysc MT7621_RST_UART2>;
 159
 160                         interrupt-parent = <&gic>;
 161                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 162
 163                         reg-shift = <2>;
 164                         reg-io-width = <4>;
 165
 166                         pinctrl-names = "default";
 167                         pinctrl-0 = <&uart2_pins>;
 168
 169                         status = "disabled";
 170                 };
 171
 172                 uartlite3: uartlite3@e00 {
 173                         compatible = "ns16550a";
 174                         reg = <0xe00 0x100>;
 175
 176                         clocks = <&sysc MT7621_CLK_UART3>;
 177
 178                         resets = <&sysc MT7621_RST_UART3>;
 179
 180                         interrupt-parent = <&gic>;
 181                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 182
 183                         reg-shift = <2>;
 184                         reg-io-width = <4>;
 185
 186                         pinctrl-names = "default";
 187                         pinctrl-0 = <&uart3_pins>;
 188
 189                         status = "disabled";
 190                 };
 191
 192                 spi0: spi@b00 {
 193                         status = "disabled";
 194
 195                         compatible = "ralink,mt7621-spi";
 196                         reg = <0xb00 0x100>;
 197
 198                         clocks = <&sysc MT7621_CLK_SPI>;
 199                         clock-names = "spi";
 200
 201                         resets = <&sysc MT7621_RST_SPI>;
 202                         reset-names = "spi";
 203
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206
 207                         pinctrl-names = "default";
 208                         pinctrl-0 = <&spi_pins>;
 209                 };
 210
 211                 gdma: gdma@2800 {
 212                         compatible = "ralink,rt3883-gdma";
 213                         reg = <0x2800 0x800>;
 214
 215                         resets = <&sysc MT7621_RST_GDMA>;
 216                         reset-names = "dma";
 217
 218                         interrupt-parent = <&gic>;
 219                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 220
 221                         #dma-cells = <1>;
 222                         #dma-channels = <16>;
 223                         #dma-requests = <16>;
 224
 225                         status = "disabled";
 226                 };
 227
 228                 hsdma: hsdma@7000 {
 229                         compatible = "mediatek,mt7621-hsdma";
 230                         reg = <0x7000 0x1000>;
 231
 232                         resets = <&sysc MT7621_RST_HSDMA>;
 233                         reset-names = "hsdma";
 234
 235                         interrupt-parent = <&gic>;
 236                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 237
 238                         #dma-cells = <1>;
 239                         #dma-channels = <1>;
 240                         #dma-requests = <1>;
 241
 242                         status = "disabled";
 243                 };
 244         };
 245
 246         pinctrl: pinctrl {
 247                 compatible = "ralink,rt2880-pinmux";
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&state_default>;
 250
 251                 state_default: pinctrl0 {
 252                 };
 253
 254                 i2c_pins: i2c_pins {
 255                         i2c_pins {
 256                                 groups = "i2c";
 257                                 function = "i2c";
 258                         };
 259                 };
 260
 261                 spi_pins: spi_pins {
 262                         spi_pins {
 263                                 groups = "spi";
 264                                 function = "spi";
 265                         };
 266                 };
 267
 268                 uart1_pins: uart1 {
 269                         uart1 {
 270                                 groups = "uart1";
 271                                 function = "uart1";
 272                         };
 273                 };
 274
 275                 uart2_pins: uart2 {
 276                         uart2 {
 277                                 groups = "uart2";
 278                                 function = "uart2";
 279                         };
 280                 };
 281
 282                 uart3_pins: uart3 {
 283                         uart3 {
 284                                 groups = "uart3";
 285                                 function = "uart3";
 286                         };
 287                 };
 288
 289                 rgmii1_pins: rgmii1 {
 290                         rgmii1 {
 291                                 groups = "rgmii1";
 292                                 function = "rgmii1";
 293                         };
 294                 };
 295
 296                 rgmii2_pins: rgmii2 {
 297                         rgmii2 {
 298                                 groups = "rgmii2";
 299                                 function = "rgmii2";
 300                         };
 301                 };
 302
 303                 mdio_pins: mdio {
 304                         mdio {
 305                                 groups = "mdio";
 306                                 function = "mdio";
 307                         };
 308                 };
 309
 310                 pcie_pins: pcie {
 311                         pcie {
 312                                 groups = "pcie";
 313                                 function = "gpio";
 314                         };
 315                 };
 316
 317                 nand_pins: nand {
 318                         spi-nand {
 319                                 groups = "spi";
 320                                 function = "nand1";
 321                         };
 322
 323                         sdhci-nand {
 324                                 groups = "sdhci";
 325                                 function = "nand2";
 326                         };
 327                 };
 328
 329                 sdhci_pins: sdhci {
 330                         sdhci {
 331                                 groups = "sdhci";
 332                                 function = "sdhci";
 333                         };
 334                 };
 335         };
 336
 337         sdhci: sdhci@1e130000 {
 338                 status = "disabled";
 339
 340                 compatible = "ralink,mt7620-sdhci";
 341                 reg = <0x1e130000 0x4000>;
 342
 343                 interrupt-parent = <&gic>;
 344                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 345
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&sdhci_pins>;
 348         };
 349
 350         xhci: xhci@1e1c0000 {
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353
 354                 compatible = "mediatek,mt8173-xhci";
 355                 reg = <0x1e1c0000 0x1000
 356                        0x1e1d0700 0x0100>;
 357                 reg-names = "mac", "ippc";
 358
 359                 clocks = <&sysc MT7621_CLK_XTAL>;
 360                 clock-names = "sys_ck";
 361
 362                 interrupt-parent = <&gic>;
 363                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 364
 365                 /*
 366                  * Port 1 of both hubs is one usb slot and referenced here.
 367                  * The binding doesn't allow to address individual hubs.
 368                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 369                  */
 370                 xhci_ehci_port1: port@1 {
 371                         reg = <1>;
 372                         #trigger-source-cells = <0>;
 373                 };
 374
 375                 /*
 376                  * Only the second usb hub has a second port. That port serves
 377                  * ehci and ohci.
 378                  */
 379                 ehci_port2: port@2 {
 380                         reg = <2>;
 381                         #trigger-source-cells = <0>;
 382                 };
 383         };
 384
 385         gic: interrupt-controller@1fbc0000 {
 386                 compatible = "mti,gic";
 387                 reg = <0x1fbc0000 0x2000>;
 388
 389                 interrupt-controller;
 390                 #interrupt-cells = <3>;
 391
 392                 mti,reserved-cpu-vectors = <7>;
 393
 394                 timer {
 395                         compatible = "mti,gic-timer";
 396                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 397                         clocks = <&sysc MT7621_CLK_CPU>;
 398                 };
 399         };
 400
 401         cpc: cpc@1fbf0000 {
 402                 compatible = "mti,mips-cpc";
 403                 reg = <0x1fbf0000 0x8000>;
 404         };
 405
 406         mc: mc@1fbf8000 {
 407                 compatible = "mti,mips-cdmm";
 408                 reg = <0x1fbf8000 0x8000>;
 409         };
 410
 411         nand: nand@1e003000 {
 412                 status = "disabled";
 413
 414                 compatible = "mediatek,mt7621-nfc";
 415                 reg = <0x1e003000 0x800
 416                         0x1e003800 0x800>;
 417                 reg-names = "nfi", "ecc";
 418
 419                 clocks = <&sysc MT7621_CLK_NAND>;
 420                 clock-names = "nfi_clk";
 421         };
 422
 423         crypto: crypto@1e004000 {
 424                 compatible = "mediatek,mtk-eip93";
 425                 reg = <0x1e004000 0x1000>;
 426
 427                 interrupt-parent = <&gic>;
 428                 interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
 429         };
 430
 431         ethernet: ethernet@1e100000 {
 432                 compatible = "mediatek,mt7621-eth";
 433                 reg = <0x1e100000 0x10000>;
 434
 435                 clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
 436                 clock-names = "fe", "ethif";
 437
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440
 441                 resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
 442                 reset-names = "fe", "eth";
 443
 444                 interrupt-parent = <&gic>;
 445                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 446
 447                 mediatek,ethsys = <&sysc>;
 448
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
 451
 452                 gmac0: mac@0 {
 453                         compatible = "mediatek,eth-mac";
 454                         reg = <0>;
 455                         phy-mode = "rgmii";
 456
 457                         fixed-link {
 458                                 speed = <1000>;
 459                                 full-duplex;
 460                                 pause;
 461                         };
 462                 };
 463
 464                 gmac1: mac@1 {
 465                         compatible = "mediatek,eth-mac";
 466                         reg = <1>;
 467                         status = "disabled";
 468                         phy-mode = "rgmii";
 469                 };
 470
 471                 mdio: mdio-bus {
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474
 475                         switch0: switch@1f {
 476                                 compatible = "mediatek,mt7621";
 477                                 reg = <0x1f>;
 478                                 mediatek,mcm;
 479                                 resets = <&sysc MT7621_RST_MCM>;
 480                                 reset-names = "mcm";
 481                                 interrupt-controller;
 482                                 #interrupt-cells = <1>;
 483                                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 484
 485                                 ports {
 486                                         #address-cells = <1>;
 487                                         #size-cells = <0>;
 488
 489                                         port@0 {
 490                                                 status = "disabled";
 491                                                 reg = <0>;
 492                                                 label = "lan0";
 493                                         };
 494
 495                                         port@1 {
 496                                                 status = "disabled";
 497                                                 reg = <1>;
 498                                                 label = "lan1";
 499                                         };
 500
 501                                         port@2 {
 502                                                 status = "disabled";
 503                                                 reg = <2>;
 504                                                 label = "lan2";
 505                                         };
 506
 507                                         port@3 {
 508                                                 status = "disabled";
 509                                                 reg = <3>;
 510                                                 label = "lan3";
 511                                         };
 512
 513                                         port@4 {
 514                                                 status = "disabled";
 515                                                 reg = <4>;
 516                                                 label = "lan4";
 517                                         };
 518
 519                                         port@6 {
 520                                                 reg = <6>;
 521                                                 ethernet = <&gmac0>;
 522                                                 phy-mode = "rgmii";
 523
 524                                                 fixed-link {
 525                                                         speed = <1000>;
 526                                                         full-duplex;
 527                                                         pause;
 528                                                 };
 529                                         };
 530                                 };
 531                         };
 532                 };
 533         };
 534
 535         pcie: pcie@1e140000 {
 536                 compatible = "mediatek,mt7621-pci";
 537                 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
 538                       <0x1e142000 0x100>, /* pcie port 0 RC control registers */
 539                       <0x1e143000 0x100>, /* pcie port 1 RC control registers */
 540                       <0x1e144000 0x100>; /* pcie port 2 RC control registers */
 541                 #address-cells = <3>;
 542                 #size-cells = <2>;
 543
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&pcie_pins>;
 546
 547                 device_type = "pci";
 548
 549                 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
 550                          <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
 551
 552                 status = "disabled";
 553
 554                 #interrupt-cells = <1>;
 555                 interrupt-map-mask = <0xF800 0 0 0>;
 556                 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
 557                                 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
 558                                 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 559
 560                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 561
 562                 pcie0: pcie@0,0 {
 563                         reg = <0x0000 0 0 0 0>;
 564                         #address-cells = <3>;
 565                         #size-cells = <2>;
 566                         device_type = "pci";
 567                         ranges;
 568                         #interrupt-cells = <1>;
 569                         interrupt-map-mask = <0 0 0 0>;
 570                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
 571                         resets = <&sysc MT7621_RST_PCIE0>;
 572                         clocks = <&sysc MT7621_CLK_PCIE0>;
 573                         phys = <&pcie0_phy 1>;
 574                         phy-names = "pcie-phy0";
 575                 };
 576
 577                 pcie1: pcie@1,0 {
 578                         reg = <0x0800 0 0 0 0>;
 579                         #address-cells = <3>;
 580                         #size-cells = <2>;
 581                         device_type = "pci";
 582                         ranges;
 583                         #interrupt-cells = <1>;
 584                         interrupt-map-mask = <0 0 0 0>;
 585                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 586                         resets = <&sysc MT7621_RST_PCIE1>;
 587                         clocks = <&sysc MT7621_CLK_PCIE1>;
 588                         phys = <&pcie0_phy 1>;
 589                         phy-names = "pcie-phy1";
 590                 };
 591
 592                 pcie2: pcie@2,0 {
 593                         reg = <0x1000 0 0 0 0>;
 594                         #address-cells = <3>;
 595                         #size-cells = <2>;
 596                         device_type = "pci";
 597                         ranges;
 598                         #interrupt-cells = <1>;
 599                         interrupt-map-mask = <0 0 0 0>;
 600                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 601                         resets = <&sysc MT7621_RST_PCIE2>;
 602                         clocks = <&sysc MT7621_CLK_PCIE2>;
 603                         phys = <&pcie2_phy 0>;
 604                         phy-names = "pcie-phy2";
 605                 };
 606         };
 607
 608         pcie0_phy: pcie-phy@1e149000 {
 609                 compatible = "mediatek,mt7621-pci-phy";
 610                 reg = <0x1e149000 0x0700>;
 611                 clocks = <&sysc MT7621_CLK_XTAL>;
 612                 #phy-cells = <1>;
 613         };
 614
 615         pcie2_phy: pcie-phy@1e14a000 {
 616                 compatible = "mediatek,mt7621-pci-phy";
 617                 reg = <0x1e14a000 0x0700>;
 618                 clocks = <&sysc MT7621_CLK_XTAL>;
 619                 #phy-cells = <1>;
 620         };
 621 };