target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         compatible = "lb-link,bl-w1200", "ralink,mt7620a-soc";
  10         model = "LB-Link BL-W1200";
  11
  12         aliases {
  13                 led-boot = &led_wps;
  14                 led-failsafe = &led_wps;
  15                 led-upgrade = &led_wps;
  16         };
  17
  18         keys {
  19                 compatible = "gpio-keys";
  20
  21                 reset_wps {
  22                         label = "reset_wps";
  23                         gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  24                         linux,code = <KEY_RESTART>;
  25                 };
  26         };
  27
  28         leds {
  29                 compatible = "gpio-leds";
  30
  31                 led_wps: wps {
  32                         label = "green:wps";
  33                         gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  34                 };
  35         };
  36 };
  37
  38 &gpio1 {
  39         status = "okay";
  40 };
  41
  42 &spi0 {
  43         status = "okay";
  44
  45         flash@0 {
  46                 compatible = "jedec,spi-nor";
  47                 reg = <0>;
  48                 spi-max-frequency = <50000000>;
  49
  50                 partitions {
  51                         compatible = "fixed-partitions";
  52                         #address-cells = <1>;
  53                         #size-cells = <1>;
  54
  55                         partition@0 {
  56                                 label = "u-boot";
  57                                 reg = <0x0 0x30000>;
  58                                 read-only;
  59                         };
  60
  61                         partition@30000 {
  62                                 label = "config";
  63                                 reg = <0x30000 0x10000>;
  64                                 read-only;
  65                         };
  66
  67                         factory: partition@40000 {
  68                                 compatible = "nvmem-cells";
  69                                 label = "factory";
  70                                 reg = <0x40000 0x10000>;
  71                                 #address-cells = <1>;
  72                                 #size-cells = <1>;
  73                                 read-only;
  74
  75                                 eeprom_factory_0: eeprom@0 {
  76                                         reg = <0x0 0x200>;
  77                                 };
  78
  79                                 eeprom_factory_8000: eeprom@8000 {
  80                                         reg = <0x8000 0x200>;
  81                                 };
  82
  83                                 macaddr_factory_28: macaddr@28 {
  84                                         reg = <0x28 0x6>;
  85                                 };
  86                         };
  87
  88                         partition@50000 {
  89                                 compatible = "denx,uimage";
  90                                 label = "firmware";
  91                                 reg = <0x50000 0x7b0000>;
  92                         };
  93                 };
  94         };
  95 };
  96
  97 &state_default {
  98         gpio {
  99                 groups = "uartf", "spi refclk";
 100                 function = "gpio";
 101         };
 102 };
 103
 104 &ethernet {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&rgmii2_pins &mdio_pins>;
 107
 108         nvmem-cells = <&macaddr_factory_28>;
 109         nvmem-cell-names = "mac-address";
 110
 111         mediatek,portmap = "wllll";
 112
 113         port@5 {
 114                 status = "okay";
 115                 mediatek,fixed-link = <1000 1 1 1>;
 116                 phy-mode = "rgmii";
 117         };
 118
 119         mdio-bus {
 120                 status = "okay";
 121
 122                 ethernet-phy@0 {
 123                         reg = <0>;
 124                         phy-mode = "rgmii";
 125                 };
 126
 127                 ethernet-phy@1 {
 128                         reg = <1>;
 129                         phy-mode = "rgmii";
 130                 };
 131
 132                 ethernet-phy@2 {
 133                         reg = <2>;
 134                         phy-mode = "rgmii";
 135                 };
 136
 137                 ethernet-phy@3 {
 138                         reg = <3>;
 139                         phy-mode = "rgmii";
 140                 };
 141
 142                 ethernet-phy@4 {
 143                         reg = <4>;
 144                         phy-mode = "rgmii";
 145                 };
 146
 147                 ethernet-phy@1f {
 148                         reg = <0x1f>;
 149                         phy-mode = "rgmii";
 150                 };
 151         };
 152 };
 153
 154 &gsw {
 155         mediatek,ephy-base = /bits/ 8 <12>;
 156 };
 157
 158 &wmac {
 159         nvmem-cells = <&eeprom_factory_0>;
 160         nvmem-cell-names = "eeprom";
 161 };
 162
 163 &pcie {
 164         status = "okay";
 165 };
 166
 167 &pcie0 {
 168         wifi@0,0 {
 169                 compatible = "mediatek,mt76";
 170                 reg = <0x0000 0 0 0 0>;
 171                 ieee80211-freq-limit = <5000000 6000000>;
 172                 nvmem-cells = <&eeprom_factory_8000>;
 173                 nvmem-cell-names = "eeprom";
 174
 175                 led {
 176                         led-sources = <2>;
 177                         led-active-low;
 178                 };
 179         };
 180 };
 181
 182 &ehci {
 183         status = "okay";
 184 };
 185
 186 &ohci {
 187         status = "okay";
 188 };