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[openwrt/staging/stintel.git] / target / linux / octeon / files / arch / mips / boot / dts / cavium-octeon / snic10e.dts
1 /dts-v1/;
2 /*
3 * Cavium Inc. (Small) NIC10e board
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7
8 / {
9 model = "cavium,snic10e";
10 compatible = "cavium,snic10e";
11 #address-cells = <2>;
12 #size-cells = <2>;
13 interrupt-parent = <&ciu>;
14
15 soc@0 {
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges; /* Direct mapping */
20
21 ciu: interrupt-controller@1070000000000 {
22 compatible = "cavium,octeon-3860-ciu";
23 interrupt-controller;
24 /* Interrupts are specified by two parts:
25 * 1) Controller register (0 or 1)
26 * 2) Bit within the register (0..63)
27 */
28 #address-cells = <0>;
29 #interrupt-cells = <2>;
30 reg = <0x10700 0x00000000 0x0 0x7000>;
31 };
32
33 gpio: gpio-controller@1070000000800 {
34 #gpio-cells = <2>;
35 compatible = "cavium,octeon-3860-gpio";
36 reg = <0x10700 0x00000800 0x0 0x100>;
37 gpio-controller;
38 /* Interrupts are specified by two parts:
39 * 1) GPIO pin number (0..15)
40 * 2) Triggering (1 - edge rising
41 * 2 - edge falling
42 * 4 - level active high
43 * 8 - level active low)
44 */
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 /* The GPIO pins connect to 16 consecutive CUI bits */
48 interrupts = <0 16>; /* <0 17> <0 18> <0 19>
49 <0 20> <0 21> <0 22> <0 23>
50 <0 24> <0 25> <0 26> <0 27>
51 <0 28> <0 29> <0 30> <0 31>; */
52 };
53
54 twsi0: i2c@1180000001000 {
55 #address-cells = <1>;
56 #size-cells = <0>;
57 compatible = "cavium,octeon-3860-twsi";
58 reg = <0x11800 0x00001000 0x0 0x200>;
59 interrupts = <0 45>;
60 /* NOTE: In order to get the proper delay between
61 * i2c bus transactions for the SFP we need to either
62 * slow the bus down to no more than 30KHz or else
63 * somehow insert a delay between transactions. Only
64 * U-Boot is capable of inserting the appropriate delay
65 * at this time.
66 */
67 clock-frequency = <30000>;
68
69 tmp@4c {
70 compatible = "ti,tmp421";
71 reg = <0x4c>;
72 };
73 sfp0: eeprom@50 {
74 compatible = "atmel,24c01";
75 reg = <0x50>;
76 };
77 tlv-eeprom@53 {
78 compatible = "atmel,24c256";
79 reg = <0x53>;
80 pagesize = <64>;
81 };
82 };
83
84 twsi1: i2c@1180000001200 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 compatible = "cavium,octeon-3860-twsi";
88 reg = <0x11800 0x00001200 0x0 0x200>;
89 interrupts = <0 59>;
90 /* NOTE: In order to get the proper delay between
91 * i2c bus transactions for the SFP we need to either
92 * slow the bus down to no more than 30KHz or else
93 * somehow insert a delay between transactions. Only
94 * U-Boot is capable of inserting the appropriate delay
95 * at this time.
96 */
97 clock-frequency = <30000>;
98
99 sfp1: eeprom@50 {
100 compatible = "atmel,24c01";
101 reg = <0x50>;
102 };
103 gpio1: gpio@20 {
104 reg = <0x20>;
105 compatible = "nxp,pca9554";
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-parent = <&gpio>;
109 interrupt = <13 2>; /* OCTEON GPIO 13, falling edge */
110 #interrupt-cells = <1>;
111 };
112
113 };
114
115 smi0: mdio@1180000001800 {
116 compatible = "cavium,octeon-3860-mdio";
117 #address-cells = <1>;
118 #size-cells = <0>;
119 reg = <0x11800 0x00001800 0x0 0x40>;
120
121 mphyA: ethernet-phy-nexus@A {
122 reg = <0>;
123 /* The Vitesse VSC8488 is a dual-PHY where
124 * some of the configuration is common across
125 * both of the phy devices such as the reset
126 * line and the base MDIO address.
127 */
128 compatible = "vitesse,vsc8488-nexus", "ethernet-phy-nexus";
129 #address-cells = <1>;
130 #size-cells = <0>;
131 ranges;
132
133 /* Hardware reset signal */
134 reset = <&gpio 17 GPIO_ACTIVE_HIGH>;
135
136 phy0: ethernet-phy@0 {
137 /* Absolute address */
138 reg = <0>;
139 compatible = "vitesse,vsc8488", "ethernet-phy-ieee802.3-c45";
140 interrupt-parent = <&gpio>;
141 interrupts = <13 8>;
142
143 mod_abs = <0>;
144 /* TX Fault GPIO line */
145 tx_fault = <1>;
146 /* GPIO that enables output */
147 txon = <4>;
148 /* INT A GPIO output */
149 inta = <5>;
150
151 /* Optional equalization value to
152 * program into the PHY XS XAUI Rx
153 * Equalization control register.
154 * It is broken up into one nibble for
155 * each lane with lane 0 using bits
156 * 12 - 15.
157 * Use the following table:
158 * 0x0 - 0dB
159 * 0x1 - 1.41dB
160 * 0x2 - 2.24dB
161 * 0x3 - 2.83dB
162 * 0x5 - 4.48dB
163 * 0x6 - 5.39dB
164 * 0x7 - 6.07dB
165 * 0x9 - 6.18dB
166 * 0xA - 7.08dB (default)
167 * 0xB - 7.79dB
168 * 0xD - 9.96dB
169 * 0xE - 10.84dB
170 * 0xF - 11.55dB
171 *
172 * This is board specific and should
173 * only be defined by the hardware
174 * vendor.
175 */
176 vitesse,rx_equalization = <0x0000>;
177 /* Optional transmit pre-emphasis
178 * control. This sets the
179 * PHY XS XAUI TX pre-emphasis control
180 * register.
181 *
182 * It uses bits 13-14 for lane 0,
183 * 10-11 for lane 1, 7-8 for lane 2
184 * and 4-5 for lane 3.
185 *
186 * Bits 2-3 are the LOS threshold
187 * setting and bit 1 enables
188 * the XAUI output high swing mode.
189 *
190 * Use the following table for
191 * pre-emphasis:
192 * 0b00 - 0dB
193 * 0b01 - 2.5dB
194 * 0b10 - 6dB (default)
195 * 0b11 - 12dB
196 *
197 * Use the following table for the LOS
198 * threshold setting:
199 *
200 * 0b00 - 50mV - 175mV (default)
201 * 0b01 - 60mV - 185mV
202 * 0b10 - 70mV - 195mV
203 * 0b11 - 80mV - 205mV
204 */
205 vitesse,tx_preemphasis = <0x0000>;
206
207 /* TX output driver slew rate control
208 * is bits 8-11 where 0x0 is the minimum
209 * and 0xF is the maximum.
210 * Default is 0xA.
211 *
212 * The TX output driver C(-1)
213 * coefficient is bits 0-4 where
214 * 0b00000 is the minimum (-4ma) and
215 * 0b11111 is the maximum (4ma). The
216 * default 0x 0b01111.
217 */
218 vitesse,txout_driver_ctrl1 = <0x0A0F>;
219
220 /* The TX output driver C(0) coefficient
221 * is bits 8-12 with 0b00000 being the
222 * minimum (0mA) and 0b11111 being
223 * the maximum (16mA). The default is
224 * 0b10011
225 *
226 * The C(+1) coefficient is bits 0-5
227 * with 0b000000 being the minimum
228 * (-0.25mA) and 0b111111 being the
229 * maximum (-16mA). The default is
230 * 0b000000.
231 */
232 /*vitesse,txout_driver_ctrl2 = <0x1300>;*/
233
234 /* DC_AGC_LOS_CONFIG1:
235 * 15: Suppress_Coarse_Adj_on_LOS_Clear
236 * 0: DC offset correction performed using coarse
237 * resolution mode (default)
238 * 1: DC offset correction performed using fine resolution
239 * mode when correction resumes after LOPC/LOS alarms
240 * clear. This guarantees there will be no big jumps in
241 * the offset at the expense of taking longer to reach
242 * optimal setting.
243 * 14: Force_DC2_Fine_Adj:
244 * Forces the DC offset correction to operate in fine
245 * resolution adjustment mode at times when the algorithm.
246 * 0: DC offset correction makes coarse adjustments when
247 * correction mode is first enabled (default)
248 * 1: DC offset correction performed using fine resolution
249 * at all times. This is slower.
250 * 13: Force_DC1_Fine_Adj:
251 * Forces the DC offset correction to operate in fine
252 * resolution adjustment mode at times when the algorithm.
253 * 0: DC offset correction makes coarse adjustments when
254 * correction mode is first enabled (default)
255 * 1: DC offset correction performed using fine resolution
256 * at all times. This is slower.
257 * 12: Force_DC0_Fine_Adj:
258 * Forces the DC offset correction to operate in fine
259 * resolution adjustment mode at times when the algorithm.
260 * 0: DC offset correction makes coarse adjustments when
261 * correction mode is first enabled (default)
262 * 1: DC offset correction performed using fine resolution
263 * at all times. This is slower.
264 * 10: Skip_DC2_Adj, 1 = skip DC2 offset correction
265 * 9: Skip_DC1_Adj, 1 = skip DC1 offset correction
266 * 8: Skip_DC0_Adj, 1 = skip DC0 offset correction
267 *
268 * 6-4: DC_Offset_Alarm_Mode (default 1)
269 * Selects the alarm condition that will halt the DC offset
270 * correction logic when the alarm(s) are set.
271 * 111: reserved
272 * 110: reserved
273 * 101: LOPC and software LOS detection
274 * 100: LOPC and hardware LOS detection
275 * 011: Software LOS detection
276 * 010: Hardware LOS detection
277 * 001: LOPC
278 * 000: Never. DC offset correction will continue to make
279 * fine resolution adjustments to the offsets even
280 * when LOPC and LOS alarms are present.
281 *
282 * 3: AGC_Enable
283 * Selects when hardware AGC adjustment logic and LOS
284 * detection logic is enabled (default 1)
285 * 0: disabled
286 * 1: enabled
287 * 2: AGC_Suspend
288 * Suspends the LOS detection logic and AGC logic
289 * from making adjustments to the gain. Bit valid only
290 * if AGC_Enable=1
291 * 0: AGC adjustment enabled (default)
292 * 1: AGC adjustment suspended
293 * 1: DC_Offset_Adj_Enable
294 * Select when the hardware DC offset correction logic is
295 * enabled.
296 * 0: disable
297 * 1: enable (default)
298 * 0: DC_Offset_Adj_Suspend
299 * Suspends the DC offset correction logic from making
300 * adjustments to all offset settings. Bit valid only if
301 * DC_Offset_Adj_Enable=1
302 * 0: DC offset correction enabled (default)
303 * 1: DC offset correction suspended
304 *
305 * This setting is only applied for
306 * passive copper.
307 */
308 vitesse,copper_dc_agc_los_config1 = <0x000A>;
309
310 /* Disable aggressive track phase during
311 * firmware convergence if 0, enabled
312 * otherwise (default).
313 *
314 * This setting is only applied for
315 * passive copper.
316 */
317 vitesse,copper_agg_track_phase = <0>;
318
319 /* AGC_Config4
320 *
321 * 13-8: Ampl_Tolerance
322 * This defines the hysterisis
323 * built in to the AGC adjustment
324 * circuit. The VGA gain will not
325 * be adjusted as long as the
326 * measured input amplitude is
327 * Inp_Ampl_Target +/- Amnpl_Tolerance.
328 * Default is 4.
329 * 7-0: Inp_Ampl_Target
330 * This is the target amplitude
331 * desired to be measured at the
332 * peak detector when measuring
333 * input amplitude. The VGA gain
334 * is adjusted to achieve this
335 * target setting.
336 * Default is 0x6E.
337 *
338 * This setting is only applied for
339 * passive copper.
340 */
341 vitesse,copper_agc_config4 = <0x0496>;
342
343 /* The Vitesse 10G PHY does not
344 * automatically read the SFP EEPROM
345 * so the host needs to do it to put
346 * the PHY in the proper mode for
347 * copper or optical.
348 */
349 sfp-eeprom = <&sfp0>;
350 };
351
352 phy1: ethernet-phy@1 {
353 /* Absolute address */
354 reg = <0x1>;
355 compatible = "vitesse,vsc8488", "ethernet-phy-ieee802.3-c45";
356 interrupt-parent = <&gpio>;
357 interrupts = <13 8>;
358
359 mod_abs = <9>;
360 /* TX Fault GPIO line */
361 tx_fault = <8>;
362 /* GPIO that enables output */
363 txon = <10>;
364 /* INT A GPIO output */
365 inta = <5>;
366
367 /* Optional equalization value to
368 * program into the PHY XS XAUI Rx
369 * Equalization control register.
370 * It is broken up into one nibble for
371 * each lane with lane 0 using bits
372 * 12 - 15.
373 * Use the following table:
374 * 0x0 - 0dB
375 * 0x1 - 1.41dB
376 * 0x2 - 2.24dB
377 * 0x3 - 2.83dB
378 * 0x5 - 4.48dB
379 * 0x6 - 5.39dB
380 * 0x7 - 6.07dB
381 * 0x9 - 6.18dB
382 * 0xA - 7.08dB (default)
383 * 0xB - 7.79dB
384 * 0xD - 9.96dB
385 * 0xE - 10.84dB
386 * 0xF - 11.55dB
387 *
388 * This is board specific and should
389 * only be defined by the hardware
390 * vendor.
391 */
392 rx_equalization = <0x0000>;
393 /* Optional transmit pre-emphasis
394 * control. This sets the
395 * PHY XS XAUI TX pre-emphasis control
396 * register.
397 *
398 * It uses bits 13-14 for lane 0,
399 * 10-11 for lane 1, 7-8 for lane 2
400 * and 4-5 for lane 3.
401 *
402 * Bits 2-3 are the LOS threshold
403 * setting and bit 1 enables
404 * the XAUI output high swing mode.
405 *
406 * Use the following table for
407 * pre-emphasis:
408 * 0b00 - 0dB
409 * 0b01 - 2.5dB
410 * 0b10 - 6dB (default)
411 * 0b11 - 12dB
412 *
413 * Use the following table for the LOS
414 * threshold setting:
415 *
416 * 0b00 - 50mV - 175mV (default)
417 * 0b01 - 60mV - 185mV
418 * 0b10 - 70mV - 195mV
419 * 0b11 - 80mV - 205mV
420 */
421 tx_preemphasis = <0x0000>;
422
423 /* TX output driver slew rate control
424 * is bits 8-11 where 0x0 is the minimum
425 * and 0xF is the maximum.
426 * Default is 0xA.
427 *
428 * The TX output driver C(-1)
429 * coefficient is bits 0-4 where
430 * 0b00000 is the minimum (-4ma) and
431 * 0b11111 is the maximum (4ma). The
432 * default 0x 0b01111.
433 */
434 txout_driver_ctrl1 = <0x0A0F>;
435
436 /* The TX output driver C(0) coefficient
437 * is bits 8-12 with 0b00000 being the
438 * minimum (0mA) and 0b11111 being
439 * the maximum (16mA). The default is
440 * 0b10011
441 *
442 * The C(+1) coefficient is bits 0-5
443 * with 0b000000 being the minimum
444 * (-0.25mA) and 0b111111 being the
445 * maximum (-16mA). The default is
446 * 0b000000.
447 */
448 /*txout_driver_ctrl2 = <0x1300>;*/
449
450 /* DC_AGC_LOS_CONFIG1:
451 * 15: Suppress_Coarse_Adj_on_LOS_Clear
452 * 0: DC offset correction performed using coarse
453 * resolution mode (default)
454 * 1: DC offset correction performed using fine resolution
455 * mode when correction resumes after LOPC/LOS alarms
456 * clear. This guarantees there will be no big jumps in
457 * the offset at the expense of taking longer to reach
458 * optimal setting.
459 * 14: Force_DC2_Fine_Adj:
460 * Forces the DC offset correction to operate in fine
461 * resolution adjustment mode at times when the algorithm.
462 * 0: DC offset correction makes coarse adjustments when
463 * correction mode is first enabled (default)
464 * 1: DC offset correction performed using fine resolution
465 * at all times. This is slower.
466 * 13: Force_DC1_Fine_Adj:
467 * Forces the DC offset correction to operate in fine
468 * resolution adjustment mode at times when the algorithm.
469 * 0: DC offset correction makes coarse adjustments when
470 * correction mode is first enabled (default)
471 * 1: DC offset correction performed using fine resolution
472 * at all times. This is slower.
473 * 12: Force_DC0_Fine_Adj:
474 * Forces the DC offset correction to operate in fine
475 * resolution adjustment mode at times when the algorithm.
476 * 0: DC offset correction makes coarse adjustments when
477 * correction mode is first enabled (default)
478 * 1: DC offset correction performed using fine resolution
479 * at all times. This is slower.
480 * 10: Skip_DC2_Adj, 1 = skip DC2 offset correction
481 * 9: Skip_DC1_Adj, 1 = skip DC1 offset correction
482 * 8: Skip_DC0_Adj, 1 = skip DC0 offset correction
483 *
484 * 6-4: DC_Offset_Alarm_Mode (default 1)
485 * Selects the alarm condition that will halt the DC offset
486 * correction logic when the alarm(s) are set.
487 * 111: reserved
488 * 110: reserved
489 * 101: LOPC and software LOS detection
490 * 100: LOPC and hardware LOS detection
491 * 011: Software LOS detection
492 * 010: Hardware LOS detection
493 * 001: LOPC
494 * 000: Never. DC offset correction will continue to make
495 * fine resolution adjustments to the offsets even
496 * when LOPC and LOS alarms are present.
497 *
498 * 3: AGC_Enable
499 * Selects when hardware AGC adjustment logic and LOS
500 * detection logic is enabled (default 1)
501 * 0: disabled
502 * 1: enabled
503 * 2: AGC_Suspend
504 * Suspends the LOS detection logic and AGC logic
505 * from making adjustments to the gain. Bit valid only
506 * if AGC_Enable=1
507 * 0: AGC adjustment enabled (default)
508 * 1: AGC adjustment suspended
509 * 1: DC_Offset_Adj_Enable
510 * Select when the hardware DC offset correction logic is
511 * enabled.
512 * 0: disable
513 * 1: enable (default)
514 * 0: DC_Offset_Adj_Suspend
515 * Suspends the DC offset correction logic from making
516 * adjustments to all offset settings. Bit valid only if
517 * DC_Offset_Adj_Enable=1
518 * 0: DC offset correction enabled (default)
519 * 1: DC offset correction suspended
520 *
521 * This setting is only applied for
522 * passive copper.
523 */
524 vitesse,copper_dc_agc_los_config1 = <0x000A>;
525
526 /* Disable aggressive track phase during
527 * firmware convergence if 0, enabled
528 * otherwise (default).
529 *
530 * This setting is only applied for
531 * passive copper.
532 */
533 vitesse,copper_agg_track_phase = <0>;
534
535 /* AGC_Config4
536 *
537 * 13-8: Ampl_Tolerance
538 * This defines the hysterisis
539 * built in to the AGC adjustment
540 * circuit. The VGA gain will not
541 * be adjusted as long as the
542 * measured input amplitude is
543 * Inp_Ampl_Target +/- Amnpl_Tolerance.
544 * Default is 4.
545 * 7-0: Inp_Ampl_Target
546 * This is the target amplitude
547 * desired to be measured at the
548 * peak detector when measuring
549 * input amplitude. The VGA gain
550 * is adjusted to achieve this
551 * target setting.
552 * Default is 0x6E.
553 *
554 * This setting is only applied for
555 * passive copper.
556 */
557 vitesse,copper_agc_config4 = <0x0496>;
558
559 /* The Vitesse 10G PHY does not
560 * automatically read the SFP EEPROM
561 * so the host needs to do it to put
562 * the PHY in the proper mode for
563 * copper or optical.
564 */
565 sfp-eeprom = <&sfp1>;
566 };
567 };
568 mphyB: ethernet-phy-nexus@B {
569 reg = <0>;
570 /* The TI TLK10232 is a dual-PHY where
571 * some of the configuration is common across
572 * both of the phy devices such as the reset
573 * line and the base MDIO address.
574 */
575 compatible = "ti,tlk10232-nexus", "ethernet-phy-nexus";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 ranges;
579
580 /* Hardware reset signal open-drain active low on GPIO 17, must not be driven high. */
581 reset = <&gpio 17 GPIO_LINE_OPEN_DRAIN>;
582
583 phy11: ethernet-phy@0 {
584 /* Absolute address */
585 reg = <0>;
586 compatible = "ti,tlk10232", "ethernet-phy-ieee802.3-c45";
587
588 /* The TI 10G PHY does not
589 * automatically read the SFP EEPROM
590 * so the host needs to do it to put
591 * the PHY in the proper mode for
592 * copper or optical.
593 */
594 sfp-eeprom = <&sfp0>;
595
596 /* TX fault input signal for PHY from SFP+ */
597 tx-fault = <&gpio1 4 GPIO_ACTIVE_HIGH>;
598 /* TX disable for PHY to SFP+ */
599 tx-disable = <&gpio1 5 GPIO_ACTIVE_HIGH>;
600 /* MOD ABS signal for PHY from SFP+ */
601 mod-abs = <&gpio1 6 GPIO_ACTIVE_HIGH>;
602 /* RX los of singal for PHY from SFP+ */
603 rx-los = <&gpio1 7 GPIO_ACTIVE_HIGH>;
604 };
605
606 phy10: ethernet-phy@1 {
607 /* Absolute address */
608 reg = <0x1>;
609 compatible = "ti,tlk10232", "ethernet-phy-ieee802.3-c45";
610
611 /* The TI 10G PHY does not
612 * automatically read the SFP EEPROM
613 * so the host needs to do it to put
614 * the PHY in the proper mode for
615 * copper or optical.
616 */
617 sfp-eeprom = <&sfp1>;
618 /* TX fault input signal for PHY */
619 tx-fault = <&gpio1 0 GPIO_ACTIVE_HIGH>;
620 /* TX disable for PHY */
621 tx-disable = <&gpio1 1 GPIO_ACTIVE_HIGH>;
622 /* MOD ABS signal for PHY */
623 mod-abs = <&gpio1 2 GPIO_ACTIVE_HIGH>;
624 /* RX los of singal for PHY */
625 rx-los = <&gpio1 3 GPIO_ACTIVE_HIGH>;
626 };
627 };
628 };
629
630 pip: pip@11800a0000000 {
631 compatible = "cavium,octeon-3860-pip";
632 #address-cells = <1>;
633 #size-cells = <0>;
634 reg = <0x11800 0xa0000000 0x0 0x2000>;
635
636 interface@A {
637 compatible = "cavium,octeon-3860-pip-interface";
638 #address-cells = <1>;
639 #size-cells = <0>;
640 reg = <0>; /* interface */
641
642 ethernet@0 {
643 compatible = "cavium,octeon-3860-pip-port";
644 reg = <0x0>; /* Port */
645 local-mac-address = [ 00 00 00 00 00 00 ];
646 phy-handle = <&phy0>;
647 };
648 };
649 interface@B {
650 compatible = "cavium,octeon-3860-pip-interface";
651 #address-cells = <1>;
652 #size-cells = <0>;
653 reg = <1>; /* interface */
654
655 ethernet@0 {
656 compatible = "cavium,octeon-3860-pip-port";
657 reg = <0x0>; /* Port */
658 local-mac-address = [ 00 00 00 00 00 00 ];
659 phy-handle = <&phy1>;
660 };
661 };
662 interface@C {
663 compatible = "cavium,octeon-3860-pip-interface";
664 #address-cells = <1>;
665 #size-cells = <0>;
666 reg = <0>; /* interface */
667
668 ethernet@0 {
669 compatible = "cavium,octeon-3860-pip-port";
670 reg = <0x0>; /* Port */
671 local-mac-address = [ 00 00 00 00 00 00 ];
672 phy-handle = <&phy10>;
673 };
674 };
675 interface@D {
676 compatible = "cavium,octeon-3860-pip-interface";
677 #address-cells = <1>;
678 #size-cells = <0>;
679 reg = <1>; /* interface */
680
681 ethernet@0 {
682 compatible = "cavium,octeon-3860-pip-port";
683 reg = <0x0>; /* Port */
684 local-mac-address = [ 00 00 00 00 00 00 ];
685 phy-handle = <&phy11>;
686 };
687 };
688 };
689
690 uart0: serial@1180000000800 {
691 compatible = "cavium,octeon-3860-uart","ns16550";
692 reg = <0x11800 0x00000800 0x0 0x400>;
693 clock-frequency = <800000000>;
694 current-speed = <115200>;
695 reg-shift = <3>;
696 interrupts = <0 34>;
697 };
698
699 uart1: serial@1180000000c00 {
700 compatible = "cavium,octeon-3860-uart","ns16550";
701 reg = <0x11800 0x00000c00 0x0 0x400>;
702 clock-frequency = <800000000>;
703 current-speed = <115200>;
704 reg-shift = <3>;
705 interrupts = <0 35>;
706 };
707
708 bootbus: bootbus@1180000000000 {
709 compatible = "cavium,octeon-3860-bootbus";
710 reg = <0x11800 0x00000000 0x0 0x200>;
711 /* The chip select number and offset */
712 #address-cells = <2>;
713 /* The size of the chip select region */
714 #size-cells = <1>;
715 ranges = <0 0 0 0x1f400000 0xc00000>,
716 <1 0 0x10000 0x30000000 0>,
717 <2 0 0 0x1f000000 0x100000>,
718 <3 0 0x10000 0x50000000 0>,
719 <4 0 0x10000 0x60000000 0>,
720 <5 0 0x10000 0x70000000 0>,
721 <6 0 0x10000 0x80000000 0>,
722 <7 0 0x10000 0x90000000 0>;
723
724 cavium,cs-config@0 {
725 compatible = "cavium,octeon-3860-bootbus-config";
726 cavium,cs-index = <0>;
727 cavium,t-adr = <10>;
728 cavium,t-ce = <50>;
729 cavium,t-oe = <50>;
730 cavium,t-we = <35>;
731 cavium,t-rd-hld = <25>;
732 cavium,t-wr-hld = <35>;
733 cavium,t-pause = <0>;
734 cavium,t-wait = <300>;
735 cavium,t-page = <25>;
736 cavium,t-rd-dly = <0>;
737
738 cavium,pages = <0>;
739 cavium,bus-width = <8>;
740 };
741 cavium,cs-config@2 {
742 compatible = "cavium,octeon-3860-bootbus-config";
743 cavium,cs-index = <2>;
744 cavium,t-adr = <0>;
745 cavium,t-ce = <50>;
746 cavium,t-oe = <20>;
747 cavium,t-we = <46>;
748 cavium,t-rd-hld = <8>;
749 cavium,t-wr-hld = <10>;
750 cavium,t-pause = <0>;
751 cavium,t-wait = <0>;
752 cavium,t-page = <1>;
753 cavium,t-ale = <1>;
754 cavium,t-rd-dly = <0>;
755
756 cavium,pages = <0>;
757 cavium,bus-width = <8>;
758 };
759 flash0: nor@0,0 {
760 compatible = "cfi-flash";
761 reg = <0 0 0x800000>;
762 #address-cells = <1>;
763 #size-cells = <1>;
764
765 partition@0 {
766 label = "bootloader";
767 reg = <0x0 0x1c0000>;
768 read-only;
769 };
770 partition@1c0000 {
771 label = "kernel";
772 reg = <0x1c0000 0x63e000>;
773 };
774 partition@7fe000 {
775 label = "environment";
776 reg = <0x7fe0000 0x2000>;
777 read-only;
778 };
779 };
780 psram0: psram@2,0 {
781 compatible = "micron,mt45w1mw16pd";
782 reg = <2 0x20 0x20>, <2 0 0x20>;
783 };
784 };
785
786 dma0: dma-engine@1180000000100 {
787 compatible = "cavium,octeon-5750-bootbus-dma";
788 reg = <0x11800 0x00000100 0x0 0x8>;
789 interrupts = <0 63>;
790 };
791 dma1: dma-engine@1180000000108 {
792 compatible = "cavium,octeon-5750-bootbus-dma";
793 reg = <0x11800 0x00000108 0x0 0x8>;
794 interrupts = <0 63>;
795 };
796 nand-flash-interface@1070001000000 {
797 compatible = "cavium,octeon-5230-nand";
798 reg = <0x10700 0x1000000 0x0 0x100 0x11800 0x168 0x0 0x20>;
799 #address-cells = <0x1>;
800 #size-cells = <0x0>;
801 interrupts = <0x0 0x3f>;
802 flash@1 {
803 compatible = "nand-flash";
804 reg = <0x1>;
805 nand-ecc-mode = "soft";
806 nand-ecc-size = <0x200>;
807 nand-ecc-bytes = <0x7>;
808 nand-bus-width = <0x8>;
809 };
810 };
811 };
812 gpio-leds {
813 compatible = "gpio-leds";
814
815 d1a {
816 label = "bottom";
817 gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
818 default-state = "keep";
819 };
820 d1b-t {
821 label = "top";
822 gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
823 default-state = "keep";
824 };
825 d1b-v {
826 label = "top";
827 gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
828 default-state = "keep";
829 };
830 };
831
832 aliases {
833 pip = &pip;
834 smi0 = &smi0;
835 twsi0 = &twsi0;
836 twsi1 = &twsi1;
837 uart0 = &uart0;
838 uart1 = &uart1;
839 flash0 = &flash0;
840 };
841 };
Staging tree of Stijn Tintel