d5b283658f37b61c71e22ea7f1dcbd2f69c530c8
[openwrt/staging/wigyori.git] / target / linux / mpc85xx / files / arch / powerpc / boot / dts / br200-wp.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Aerohive BR200-WP Device Tree Source
4 *
5 * Based on: Aerohive HiveAP-330 Device Tree Source
6 *
7 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
8 * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
9 */
10
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/gpio/gpio.h>
14
15 /include/ "fsl/p1020si-pre.dtsi"
16
17 / {
18 model = "Aerohive BR200-WP";
19 compatible = "aerohive,br200-wp";
20
21 chosen {
22 bootargs = "console=ttyS0,9600";
23 bootargs-override = "console=ttyS0,9600 noinitrd";
24 };
25
26 aliases {
27 led-boot = &led_attention;
28 led-failsafe = &led_attention;
29 led-running = &led_status;
30 led-upgrade = &led_status;
31 label-mac-device = &enet0;
32 };
33
34 memory {
35 device_type = "memory";
36 };
37
38 cpus {
39 /delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
40 };
41
42 board_lbc: lbc: localbus@ffe05000 {
43 reg = <0 0xffe05000 0 0x1000>;
44 ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
45
46 nor@0,0 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "cfi-flash";
50 reg = <0x0 0x0 0x4000000>;
51 bank-width = <2>;
52 device-width = <1>;
53
54 partitions {
55 compatible = "fixed-partitions";
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 partition@0 {
60 reg = <0x0 0x40000>;
61 label = "dtb";
62 };
63
64 partition@40000 {
65 reg = <0x40000 0x40000>;
66 label = "initramfs";
67 };
68
69 partition@80000 {
70 reg = <0x80000 0x27c0000>;
71 label = "rootfs";
72 };
73
74 partition@2840000 {
75 reg = <0x2840000 0x800000>;
76 label = "kernel";
77 };
78
79 partition@3040000 {
80 reg = <0x3040000 0xec0000>;
81 label = "stock-jffs2";
82 read-only;
83 };
84
85 partition@3f00000 {
86 reg = <0x3f00000 0x20000>;
87 label = "hw-info";
88 read-only;
89
90 compatible = "nvmem-cells";
91 #address-cells = <1>;
92 #size-cells = <1>;
93
94 macaddr_hwinfo_0: macaddr@0 {
95 reg = <0x0 0x6>;
96 };
97 };
98
99 partition@3f20000 {
100 reg = <0x3f20000 0x20000>;
101 label = "boot-info";
102 read-only;
103 };
104
105 partition@3f40000 {
106 reg = <0x3f40000 0x20000>;
107 label = "boot-info-backup";
108 read-only;
109 };
110
111 partition@3f60000 {
112 reg = <0x3f60000 0x20000>;
113 label = "u-boot-env";
114 };
115
116 partition@3f80000 {
117 reg = <0x3f80000 0x80000>;
118 label = "u-boot";
119 read-only;
120 };
121
122 firmware@0 {
123 reg = <0x0 0x3040000>;
124 label = "firmware";
125 };
126 };
127 };
128 };
129
130 board_soc: soc: soc@ffe00000 {
131 ranges = <0x0 0x0 0xffe00000 0x100000>;
132
133 mdio@24000 {
134
135 phy_port1: phy@0 {
136 reg = <0>;
137 };
138
139 phy_port2: phy@1 {
140 reg = <1>;
141 };
142
143 phy_port3: phy@2 {
144 reg = <2>;
145 };
146
147 phy_port4: phy@3 {
148 reg = <3>;
149 };
150
151 phy_port5: phy@4 {
152 reg = <4>;
153 };
154
155 switch@10 {
156 compatible = "qca,qca8327";
157 #address-cells = <1>;
158 #size-cells = <0>;
159 reg = <0x10>;
160 reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
161
162 ports {
163 #address-cells = <1>;
164 #size-cells = <0>;
165
166 port@1 {
167 reg = <1>;
168 label = "lan1";
169 phy-handle = <&phy_port1>;
170 nvmem-cells = <&macaddr_hwinfo_0>;
171 nvmem-cell-names = "mac-address";
172 mac-address-increment = <2>;
173 };
174
175 port@2 {
176 reg = <2>;
177 label = "lan2";
178 phy-handle = <&phy_port2>;
179 nvmem-cells = <&macaddr_hwinfo_0>;
180 nvmem-cell-names = "mac-address";
181 mac-address-increment = <3>;
182 };
183
184 port@3 {
185 reg = <3>;
186 label = "lan3";
187 phy-handle = <&phy_port3>;
188 nvmem-cells = <&macaddr_hwinfo_0>;
189 nvmem-cell-names = "mac-address";
190 mac-address-increment = <4>;
191 };
192
193 port@4 {
194 reg = <4>;
195 label = "lan4";
196 phy-handle = <&phy_port4>;
197 nvmem-cells = <&macaddr_hwinfo_0>;
198 nvmem-cell-names = "mac-address";
199 mac-address-increment = <5>;
200 };
201
202 port@5 {
203 reg = <5>;
204 label = "wan";
205 phy-handle = <&phy_port5>;
206 nvmem-cells = <&macaddr_hwinfo_0>;
207 nvmem-cell-names = "mac-address";
208 };
209
210 port@6 {
211 reg = <6>;
212 ethernet = <&enet0>;
213 phy-mode = "rgmii-id";
214
215 fixed-link {
216 speed = <1000>;
217 full-duplex;
218 };
219 };
220 };
221 };
222 };
223
224 mdio@25000 {
225 status = "disabled";
226 };
227
228 mdio@26000 {
229 status = "disabled";
230 };
231
232 enet0: ethernet@b0000 {
233 status = "okay";
234 phy-connection-type = "rgmii-id";
235 nvmem-cells = <&macaddr_hwinfo_0>;
236 nvmem-cell-names = "mac-address";
237
238 fixed-link {
239 speed = <1000>;
240 full-duplex;
241 };
242 };
243
244 enet1: ethernet@b1000 {
245 status = "disabled";
246 };
247
248 enet2: ethernet@b2000 {
249 status = "disabled";
250 };
251
252 gpio0: gpio-controller@fc00 {
253 };
254
255 usb@22000 {
256 phy_type = "ulpi";
257 dr_mode = "host";
258 };
259
260 usb@23000 {
261 status = "disabled";
262 };
263 };
264
265 pci0: pcie@ffe09000 {
266 status = "disabled";
267 };
268
269 pci1: pcie@ffe0a000 {
270 reg = <0x0 0xffe0a000 0x0 0x1000>;
271 ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
272 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
273
274 reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
275
276 pcie@0 {
277 ranges = <0x2000000 0x0 0xc0000000
278 0x2000000 0x0 0xc0000000
279 0x0 0x20000000
280
281 0x1000000 0x0 0x0
282 0x1000000 0x0 0x0
283 0x0 0x100000>;
284
285 ath9k: wifi@0,0 {
286 reg = <0x0000 0 0 0 0>;
287 #gpio-cells = <2>;
288 gpio-controller;
289 nvmem-cells = <&macaddr_hwinfo_0>;
290 nvmem-cell-names = "mac-address";
291 mac-address-increment = <16>;
292 };
293 };
294 };
295
296 leds {
297 compatible = "gpio-leds";
298
299 led_attention: led-0 {
300 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
301 label = "amber:status";
302 color = <LED_COLOR_ID_AMBER>;
303 function = LED_FUNCTION_STATUS;
304 };
305
306 led_status: led-1 {
307 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
308 label = "white:status";
309 color = <LED_COLOR_ID_WHITE>;
310 function = LED_FUNCTION_STATUS;
311 };
312 };
313
314 buttons {
315 compatible = "gpio-keys";
316
317 reset {
318 label = "Reset button";
319 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
320 linux,code = <KEY_RESTART>;
321 };
322 };
323 };
324
325 /include/ "fsl/p1020si-post.dtsi"
326
327 / {
328 chosen {
329 stdout-path = "/soc@ffe00000/serial@4500";
330 };
331
332 cpus {
333 PowerPC,P1020@0 {
334 i-cache-sets = <0x80>;
335 i-cache-size = <0x8000>;
336 i-cache-block-size = <0x20>;
337 d-cache-sets = <0x80>;
338 d-cache-size = <0x8000>;
339 d-cache-block-size = <0x20>;
340 clock-frequency = <0x2756cd00>;
341 bus-frequency = <0x13ab6680>;
342 timebase-frequency = <0x2756cd0>;
343 };
344 };
345
346 memory {
347 reg = <0x00 0x00 0x00 0x10000000>;
348 };
349
350 localbus@ffe05000 {
351 bus-frequency = <0x13ab668>;
352 };
353
354 soc@ffe00000 {
355 bus-frequency = <0x13ab6680>;
356
357 serial@4500 {
358 clock-frequency = <0x13ab6680>;
359 };
360
361 serial@4600 {
362 clock-frequency = <0x13ab6680>;
363 };
364 };
365
366 pcie@ffe09000 {
367 clock-frequency = <0x1fca055>;
368 };
369
370 pcie@ffe0a000 {
371 clock-frequency = <0x1fca055>;
372 };
373 };