target/linux/jh71x0/patches-6.1/0125-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch

   1 From 54543412064edcda35437add357705996a96c492 Mon Sep 17 00:00:00 2001
   2 From: "shanlong.li" <shanlong.li@starfivetech.com>
   3 Date: Wed, 31 May 2023 01:14:01 -0700
   4 Subject: [PATCH 073/129] net: phy: motorcomm: Add pad drive strength cfg
   5  support
   6
   7 The motorcomm phy (YT8531) supports the ability to adjust the drive
   8 strength of the rx_clk/rx_data, and the default strength may not be
   9 suitable for all boards. So add configurable options to better match
  10 the boards.(e.g. StarFive VisionFive 2)
  11
  12 Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
  13 ---
  14  drivers/net/phy/motorcomm.c | 62 +++++++++++++++++++++++--------------
  15  1 file changed, 38 insertions(+), 24 deletions(-)
  16
  17 --- a/drivers/net/phy/motorcomm.c
  18 +++ b/drivers/net/phy/motorcomm.c
  19 @@ -238,9 +238,13 @@
  20  #define YTPHY_WCR_TYPE_PULSE                   BIT(0)
  21
  22  #define YTPHY_PAD_DRIVE_STRENGTH_REG           0xA010
  23 -#define YTPHY_RGMII_RXC_DS                     GENMASK(15, 13)
  24 -#define YTPHY_RGMII_RXD_DS                     GENMASK(5, 4)   /* Bit 1 and 0 of rgmii_rxd_ds */
  25 -#define YTPHY_RGMII_RXD_DS2                    BIT(12)         /* Bit 2 of rgmii_rxd_ds */
  26 +#define YT8531_RGMII_RXC_DS_DEFAULT            0x3
  27 +#define YT8531_RGMII_RXC_DS_MAX                        0x7
  28 +#define YT8531_RGMII_RXC_DS                    GENMASK(15, 13)
  29 +#define YT8531_RGMII_RXD_DS_DEFAULT            0x3
  30 +#define YT8531_RGMII_RXD_DS_MAX                        0x7
  31 +#define YT8531_RGMII_RXD_DS_LOW                        GENMASK(5, 4) /* Bit 1/0 of rxd_ds */
  32 +#define YT8531_RGMII_RXD_DS_HI                 BIT(12) /* Bit 2 of rxd_ds */
  33
  34  #define YTPHY_SYNCE_CFG_REG                    0xA012
  35  #define YT8521_SCR_SYNCE_ENABLE                        BIT(5)
  36 @@ -1500,8 +1504,8 @@ err_restore_page:
  37  static int yt8531_config_init(struct phy_device *phydev)
  38  {
  39         struct device_node *node = phydev->mdio.dev.of_node;
  40 +       u32 ds, val;
  41         int ret;
  42 -       u32 val;
  43
  44         ret = ytphy_rgmii_clk_delay_config_with_lock(phydev);
  45         if (ret < 0)
  46 @@ -1525,32 +1529,42 @@ static int yt8531_config_init(struct phy
  47                         return ret;
  48         }
  49
  50 -       if (!of_property_read_u32(node, "rx-clk-driver-strength", &val)) {
  51 -               ret = ytphy_modify_ext_with_lock(phydev,
  52 -                                                YTPHY_PAD_DRIVE_STRENGTH_REG,
  53 -                                                YTPHY_RGMII_RXC_DS,
  54 -                                                FIELD_PREP(YTPHY_RGMII_RXC_DS, val));
  55 -               if (ret < 0)
  56 -                       return ret;
  57 +       ds = YT8531_RGMII_RXC_DS_DEFAULT;
  58 +       if (!of_property_read_u32(node, "motorcomm,rx-clk-driver-strength", &val)) {
  59 +               if (val > YT8531_RGMII_RXC_DS_MAX)
  60 +                       return -EINVAL;
  61 +
  62 +               ds = val;
  63         }
  64
  65 -       if (!of_property_read_u32(node, "rx-data-driver-strength", &val)) {
  66 -               if (val > FIELD_MAX(YTPHY_RGMII_RXD_DS)) {
  67 -                       val &= FIELD_MAX(YTPHY_RGMII_RXD_DS);
  68 -                       val = FIELD_PREP(YTPHY_RGMII_RXD_DS, val);
  69 -                       val |= YTPHY_RGMII_RXD_DS2;
  70 +       ret = ytphy_modify_ext_with_lock(phydev,
  71 +                                        YTPHY_PAD_DRIVE_STRENGTH_REG,
  72 +                                        YT8531_RGMII_RXC_DS,
  73 +                                        FIELD_PREP(YT8531_RGMII_RXC_DS, ds));
  74 +       if (ret < 0)
  75 +               return ret;
  76 +
  77 +       ds = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW, YT8531_RGMII_RXD_DS_DEFAULT);
  78 +       if (!of_property_read_u32(node, "motorcomm,rx-data-driver-strength", &val)) {
  79 +               if (val > YT8531_RGMII_RXD_DS_MAX)
  80 +                       return -EINVAL;
  81 +
  82 +               if (val > FIELD_MAX(YT8531_RGMII_RXD_DS_LOW)) {
  83 +                       ds = val & FIELD_MAX(YT8531_RGMII_RXD_DS_LOW);
  84 +                       ds = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW, ds);
  85 +                       ds |= YT8531_RGMII_RXD_DS_HI;
  86                 } else {
  87 -                       val = FIELD_PREP(YTPHY_RGMII_RXD_DS, val);
  88 +                       ds = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW, val);
  89                 }
  90 -
  91 -               ret = ytphy_modify_ext_with_lock(phydev,
  92 -                                                YTPHY_PAD_DRIVE_STRENGTH_REG,
  93 -                                                YTPHY_RGMII_RXD_DS | YTPHY_RGMII_RXD_DS2,
  94 -                                                val);
  95 -               if (ret < 0)
  96 -                       return ret;
  97         }
  98
  99 +       ret = ytphy_modify_ext_with_lock(phydev,
 100 +                                        YTPHY_PAD_DRIVE_STRENGTH_REG,
 101 +                                        YT8531_RGMII_RXD_DS_LOW | YT8531_RGMII_RXD_DS_HI,
 102 +                                        ds);
 103 +       if (ret < 0)
 104 +               return ret;
 105 +
 106         return 0;
 107  }
 108