jh71x0: refresh patches and configs once again
[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0115-RISC-V-Factor-out-common-code-of-__cpu_resume_enter.patch
1 From f0e2b8f9bb240d7391d3eeca55534160fd385ea8 Mon Sep 17 00:00:00 2001
2 From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
3 Date: Thu, 30 Mar 2023 14:43:19 +0800
4 Subject: [PATCH 115/122] RISC-V: Factor out common code of
5 __cpu_resume_enter()
6
7 The cpu_resume() function is very similar for the suspend to disk and
8 suspend to ram cases. Factor out the common code into suspend_restore_csrs
9 macro and suspend_restore_regs macro.
10
11 Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
12 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
13 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
14 ---
15 arch/riscv/include/asm/assembler.h | 62 ++++++++++++++++++++++++++++++
16 arch/riscv/kernel/suspend_entry.S | 34 ++--------------
17 2 files changed, 65 insertions(+), 31 deletions(-)
18 create mode 100644 arch/riscv/include/asm/assembler.h
19
20 diff --git a/arch/riscv/include/asm/assembler.h b/arch/riscv/include/asm/assembler.h
21 new file mode 100644
22 index 000000000000..ba59d38f8937
23 --- /dev/null
24 +++ b/arch/riscv/include/asm/assembler.h
25 @@ -0,0 +1,62 @@
26 +/* SPDX-License-Identifier: GPL-2.0-only */
27 +/*
28 + * Copyright (C) 2023 StarFive Technology Co., Ltd.
29 + *
30 + * Author: Jee Heng Sia <jeeheng.sia@starfivetech.com>
31 + */
32 +
33 +#ifndef __ASSEMBLY__
34 +#error "Only include this from assembly code"
35 +#endif
36 +
37 +#ifndef __ASM_ASSEMBLER_H
38 +#define __ASM_ASSEMBLER_H
39 +
40 +#include <asm/asm.h>
41 +#include <asm/asm-offsets.h>
42 +#include <asm/csr.h>
43 +
44 +/*
45 + * suspend_restore_csrs - restore CSRs
46 + */
47 + .macro suspend_restore_csrs
48 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
49 + csrw CSR_EPC, t0
50 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
51 + csrw CSR_STATUS, t0
52 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
53 + csrw CSR_TVAL, t0
54 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
55 + csrw CSR_CAUSE, t0
56 + .endm
57 +
58 +/*
59 + * suspend_restore_regs - Restore registers (except A0 and T0-T6)
60 + */
61 + .macro suspend_restore_regs
62 + REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
63 + REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
64 + REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
65 + REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
66 + REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
67 + REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
68 + REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
69 + REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
70 + REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
71 + REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
72 + REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
73 + REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
74 + REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
75 + REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
76 + REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
77 + REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
78 + REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
79 + REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
80 + REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
81 + REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
82 + REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
83 + REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
84 + REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
85 + .endm
86 +
87 +#endif /* __ASM_ASSEMBLER_H */
88 diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S
89 index aafcca58c19d..12b52afe09a4 100644
90 --- a/arch/riscv/kernel/suspend_entry.S
91 +++ b/arch/riscv/kernel/suspend_entry.S
92 @@ -7,6 +7,7 @@
93 #include <linux/linkage.h>
94 #include <asm/asm.h>
95 #include <asm/asm-offsets.h>
96 +#include <asm/assembler.h>
97 #include <asm/csr.h>
98 #include <asm/xip_fixup.h>
99
100 @@ -83,39 +84,10 @@ ENTRY(__cpu_resume_enter)
101 add a0, a1, zero
102
103 /* Restore CSRs */
104 - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
105 - csrw CSR_EPC, t0
106 - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
107 - csrw CSR_STATUS, t0
108 - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
109 - csrw CSR_TVAL, t0
110 - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
111 - csrw CSR_CAUSE, t0
112 + suspend_restore_csrs
113
114 /* Restore registers (except A0 and T0-T6) */
115 - REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
116 - REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
117 - REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
118 - REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
119 - REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
120 - REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
121 - REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
122 - REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
123 - REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
124 - REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
125 - REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
126 - REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
127 - REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
128 - REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
129 - REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
130 - REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
131 - REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
132 - REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
133 - REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
134 - REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
135 - REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
136 - REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
137 - REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
138 + suspend_restore_regs
139
140 /* Return zero value */
141 add a0, zero, zero
142 --
143 2.20.1
144