target/linux/jh71x0/patches-6.1/0103-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch

   1 From c27b091519da0c889fa452e98d44cf8fb431b961 Mon Sep 17 00:00:00 2001
   2 From: Minda Chen <minda.chen@starfivetech.com>
   3 Date: Thu, 18 May 2023 19:27:47 +0800
   4 Subject: [PATCH 103/129] phy: starfive: Add JH7110 PCIE 2.0 PHY driver
   5
   6 Add Starfive JH7110 SoC PCIe 2.0 PHY driver support.
   7 PCIe 2.0 PHY default connect to PCIe controller.
   8 PCIe PHY can connect to USB 3.0 controller.
   9
  10 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
  11 ---
  12  drivers/phy/starfive/Kconfig           |  10 ++
  13  drivers/phy/starfive/Makefile          |   1 +
  14  drivers/phy/starfive/phy-jh7110-pcie.c | 204 +++++++++++++++++++++++++
  15  3 files changed, 215 insertions(+)
  16  create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
  17
  18 diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
  19 index 2c013c390..38eb0c0c8 100644
  20 --- a/drivers/phy/starfive/Kconfig
  21 +++ b/drivers/phy/starfive/Kconfig
  22 @@ -12,6 +12,16 @@ config PHY_STARFIVE_DPHY_RX
  23           system. If M is selected, the module will be called
  24           phy-starfive-dphy-rx.
  25
  26 +config PHY_STARFIVE_JH7110_PCIE
  27 +       tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
  28 +       select GENERIC_PHY
  29 +       select USB_PHY
  30 +       help
  31 +         Enable this to support the StarFive PCIe 2.0 PHY,
  32 +         or used as USB 3.0 PHY.
  33 +         If M is selected, the module will be called
  34 +         phy-jh7110-pcie.ko.
  35 +
  36  config PHY_STARFIVE_JH7110_USB
  37         tristate "Starfive JH7110 USB 2.0 PHY support"
  38         depends on USB_SUPPORT
  39 diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
  40 index 176443852..03a55aad5 100644
  41 --- a/drivers/phy/starfive/Makefile
  42 +++ b/drivers/phy/starfive/Makefile
  43 @@ -1,3 +1,4 @@
  44  # SPDX-License-Identifier: GPL-2.0
  45  obj-$(CONFIG_PHY_STARFIVE_DPHY_RX)      += phy-starfive-dphy-rx.o
  46 +obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
  47  obj-$(CONFIG_PHY_STARFIVE_JH7110_USB)  += phy-jh7110-usb.o
  48 diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
  49 new file mode 100644
  50 index 000000000..cbe79c1f5
  51 --- /dev/null
  52 +++ b/drivers/phy/starfive/phy-jh7110-pcie.c
  53 @@ -0,0 +1,204 @@
  54 +// SPDX-License-Identifier: GPL-2.0+
  55 +/*
  56 + * StarFive JH7110 PCIe 2.0 PHY driver
  57 + *
  58 + * Copyright (C) 2023 StarFive Technology Co., Ltd.
  59 + * Author: Minda Chen <minda.chen@starfivetech.com>
  60 + */
  61 +
  62 +#include <linux/bits.h>
  63 +#include <linux/clk.h>
  64 +#include <linux/err.h>
  65 +#include <linux/io.h>
  66 +#include <linux/module.h>
  67 +#include <linux/mfd/syscon.h>
  68 +#include <linux/phy/phy.h>
  69 +#include <linux/platform_device.h>
  70 +#include <linux/regmap.h>
  71 +
  72 +#define PCIE_KVCO_LEVEL_OFF            0x28
  73 +#define PCIE_USB3_PHY_PLL_CTL_OFF      0x7c
  74 +#define PCIE_KVCO_TUNE_SIGNAL_OFF      0x80
  75 +#define PCIE_USB3_PHY_ENABLE           BIT(4)
  76 +#define PHY_KVCO_FINE_TUNE_LEVEL       0x91
  77 +#define PHY_KVCO_FINE_TUNE_SIGNALS     0xc
  78 +
  79 +#define USB_PDRSTN_SPLIT               BIT(17)
  80 +
  81 +#define PCIE_PHY_MODE                  BIT(20)
  82 +#define PCIE_PHY_MODE_MASK             GENMASK(21, 20)
  83 +#define PCIE_USB3_BUS_WIDTH_MASK       GENMASK(3, 2)
  84 +#define PCIE_USB3_BUS_WIDTH            BIT(3)
  85 +#define PCIE_USB3_RATE_MASK            GENMASK(6, 5)
  86 +#define PCIE_USB3_RX_STANDBY_MASK      BIT(7)
  87 +#define PCIE_USB3_PHY_ENABLE           BIT(4)
  88 +
  89 +struct jh7110_pcie_phy {
  90 +       struct phy *phy;
  91 +       struct regmap *stg_syscon;
  92 +       struct regmap *sys_syscon;
  93 +       void __iomem *regs;
  94 +       u32 sys_phy_connect;
  95 +       u32 stg_pcie_mode;
  96 +       u32 stg_pcie_usb;
  97 +       enum phy_mode mode;
  98 +};
  99 +
 100 +static int phy_usb3_mode_set(struct jh7110_pcie_phy *data)
 101 +{
 102 +       if (!data->stg_syscon || !data->sys_syscon) {
 103 +               dev_err(&data->phy->dev, "doesn't support usb3 mode\n");
 104 +               return -EINVAL;
 105 +       }
 106 +
 107 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
 108 +                          PCIE_PHY_MODE_MASK, PCIE_PHY_MODE);
 109 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
 110 +                          PCIE_USB3_BUS_WIDTH_MASK, 0);
 111 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
 112 +                          PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE);
 113 +
 114 +       /* Connect usb 3.0 phy mode */
 115 +       regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
 116 +                          USB_PDRSTN_SPLIT, 0);
 117 +
 118 +       /* Configuare spread-spectrum mode: down-spread-spectrum */
 119 +       writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
 120 +
 121 +       return 0;
 122 +}
 123 +
 124 +static void phy_pcie_mode_set(struct jh7110_pcie_phy *data)
 125 +{
 126 +       u32 val;
 127 +
 128 +       /* default is PCIe mode */
 129 +       if (!data->stg_syscon || !data->sys_syscon)
 130 +               return;
 131 +
 132 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
 133 +                          PCIE_PHY_MODE_MASK, 0);
 134 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
 135 +                          PCIE_USB3_BUS_WIDTH_MASK,
 136 +                          PCIE_USB3_BUS_WIDTH);
 137 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
 138 +                          PCIE_USB3_PHY_ENABLE, 0);
 139 +
 140 +       regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
 141 +                          USB_PDRSTN_SPLIT, 0);
 142 +
 143 +       val = readl(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
 144 +       val &= ~PCIE_USB3_PHY_ENABLE;
 145 +       writel(val, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
 146 +}
 147 +
 148 +static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
 149 +{
 150 +       /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
 151 +       writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
 152 +       writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
 153 +}
 154 +
 155 +static int jh7110_pcie_phy_set_mode(struct phy *_phy,
 156 +                                   enum phy_mode mode, int submode)
 157 +{
 158 +       struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy);
 159 +       int ret;
 160 +
 161 +       if (mode == phy->mode)
 162 +               return 0;
 163 +
 164 +       switch (mode) {
 165 +       case PHY_MODE_USB_HOST:
 166 +       case PHY_MODE_USB_DEVICE:
 167 +       case PHY_MODE_USB_OTG:
 168 +               ret = phy_usb3_mode_set(phy);
 169 +               if (ret)
 170 +                       return ret;
 171 +               break;
 172 +       case PHY_MODE_PCIE:
 173 +               phy_pcie_mode_set(phy);
 174 +               break;
 175 +       default:
 176 +               return -EINVAL;
 177 +       }
 178 +
 179 +       dev_dbg(&_phy->dev, "Changing phy mode to %d\n", mode);
 180 +       phy->mode = mode;
 181 +
 182 +       return 0;
 183 +}
 184 +
 185 +static const struct phy_ops jh7110_pcie_phy_ops = {
 186 +       .set_mode       = jh7110_pcie_phy_set_mode,
 187 +       .owner          = THIS_MODULE,
 188 +};
 189 +
 190 +static int jh7110_pcie_phy_probe(struct platform_device *pdev)
 191 +{
 192 +       struct jh7110_pcie_phy *phy;
 193 +       struct device *dev = &pdev->dev;
 194 +       struct phy_provider *phy_provider;
 195 +       u32 args[2];
 196 +
 197 +       phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 198 +       if (!phy)
 199 +               return -ENOMEM;
 200 +
 201 +       phy->regs = devm_platform_ioremap_resource(pdev, 0);
 202 +       if (IS_ERR(phy->regs))
 203 +               return PTR_ERR(phy->regs);
 204 +
 205 +       phy->phy = devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops);
 206 +       if (IS_ERR(phy->phy))
 207 +               return dev_err_probe(dev, PTR_ERR(phy->regs),
 208 +                                    "Failed to map phy base\n");
 209 +
 210 +       phy->sys_syscon =
 211 +               syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
 212 +                                                    "starfive,sys-syscon",
 213 +                                                    1, args);
 214 +
 215 +       if (!IS_ERR_OR_NULL(phy->sys_syscon))
 216 +               phy->sys_phy_connect = args[0];
 217 +       else
 218 +               phy->sys_syscon = NULL;
 219 +
 220 +       phy->stg_syscon =
 221 +               syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
 222 +                                                    "starfive,stg-syscon",
 223 +                                                    2, args);
 224 +
 225 +       if (!IS_ERR_OR_NULL(phy->stg_syscon)) {
 226 +               phy->stg_pcie_mode = args[0];
 227 +               phy->stg_pcie_usb = args[1];
 228 +       } else {
 229 +               phy->stg_syscon = NULL;
 230 +       }
 231 +
 232 +       phy_kvco_gain_set(phy);
 233 +
 234 +       phy_set_drvdata(phy->phy, phy);
 235 +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 236 +
 237 +       return PTR_ERR_OR_ZERO(phy_provider);
 238 +}
 239 +
 240 +static const struct of_device_id jh7110_pcie_phy_of_match[] = {
 241 +       { .compatible = "starfive,jh7110-pcie-phy" },
 242 +       { /* sentinel */ },
 243 +};
 244 +MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match);
 245 +
 246 +static struct platform_driver jh7110_pcie_phy_driver = {
 247 +       .probe  = jh7110_pcie_phy_probe,
 248 +       .driver = {
 249 +               .of_match_table = jh7110_pcie_phy_of_match,
 250 +               .name  = "jh7110-pcie-phy",
 251 +       }
 252 +};
 253 +module_platform_driver(jh7110_pcie_phy_driver);
 254 +
 255 +MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver");
 256 +MODULE_AUTHOR("Minda Chen <minda.chen@starfivetech.com>");
 257 +MODULE_LICENSE("GPL");
 258 --
 259 2.25.1
 260