1 From 3d555cfd72df1a02849565f281149d321e0f8425 Mon Sep 17 00:00:00 2001
2 From: Minda Chen <minda.chen@starfivetech.com>
3 Date: Thu, 6 Apr 2023 19:11:40 +0800
4 Subject: [PATCH 094/122] dt-binding: pci: add JH7110 PCIe dt-binding
7 Add PCIe controller driver dt-binding documents
8 for StarFive JH7110 SoC platform.
10 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
12 .../bindings/pci/starfive,jh7110-pcie.yaml | 163 ++++++++++++++++++
13 1 file changed, 163 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
16 diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
18 index 000000000000..fa4829766195
20 +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
22 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
25 +$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
26 +$schema: http://devicetree.org/meta-schemas/core.yaml#
28 +title: StarFive JH7110 PCIe 2.0 host controller
31 + - Minda Chen <minda.chen@starfivetech.com>
34 + - $ref: /schemas/pci/pci-bus.yaml#
35 + - $ref: /schemas/interrupt-controller/msi-controller.yaml#
39 + const: starfive,jh7110-pcie
66 + - description: AXI MST0 reset
67 + - description: AXI SLAVE reset
68 + - description: AXI SLAVE0 reset
69 + - description: PCIE BRIDGE reset
70 + - description: PCIE CORE reset
71 + - description: PCIE APB reset
82 + starfive,stg-syscon:
83 + $ref: /schemas/types.yaml#/definitions/phandle-array
86 + - description: phandle to System Register Controller stg_syscon node.
87 + - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
88 + - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
89 + - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
90 + - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
92 + The phandle to System Register Controller syscon node and the offset
93 + of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset
97 + description: Should specify the GPIO for controlling the PCI bus device power on.
106 + interrupt-controller:
112 + '#interrupt-cells':
115 + interrupt-controller: true
119 + - '#interrupt-cells'
120 + - interrupt-controller
122 + additionalProperties: false
127 + - "#interrupt-cells"
129 + - interrupt-map-mask
136 +unevaluatedProperties: false
141 + #address-cells = <2>;
144 + pcie0: pcie@2B000000 {
145 + compatible = "starfive,jh7110-pcie";
146 + #address-cells = <3>;
148 + #interrupt-cells = <1>;
149 + reg = <0x0 0x2B000000 0x0 0x1000000>,
150 + <0x9 0x40000000 0x0 0x10000000>;
151 + reg-names = "reg", "config";
152 + device_type = "pci";
153 + starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
154 + bus-range = <0x0 0xff>;
155 + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
156 + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
157 + interrupt-parent = <&plic>;
159 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
160 + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
161 + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
162 + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
163 + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
164 + msi-parent = <&pcie0>;
166 + clocks = <&syscrg 86>,
170 + clock-names = "noc", "tl", "axi_mst0", "apb";
171 + resets = <&stgcrg 11>,
178 + pcie_intc0: interrupt-controller {
179 + #address-cells = <0>;
180 + #interrupt-cells = <1>;
181 + interrupt-controller;