target/linux/jh71x0/patches-6.1/0088-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch

   1 From d57245d420a2ced6a588cc6e03e2eaacbbf1bfb2 Mon Sep 17 00:00:00 2001
   2 From: Minda Chen <minda.chen@starfivetech.com>
   3 Date: Thu, 18 May 2023 19:27:45 +0800
   4 Subject: [PATCH 088/122] dt-bindings: phy: Add StarFive JH7110 PCIe PHY
   5
   6 Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
   7 PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
   8
   9 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
  10 Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
  11 Reviewed-by: Rob Herring <robh@kernel.org>
  12 ---
  13  .../phy/starfive,jh7110-pcie-phy.yaml         | 58 +++++++++++++++++++
  14  1 file changed, 58 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
  16
  17 diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
  18 new file mode 100644
  19 index 000000000000..2e83a6164cd1
  20 --- /dev/null
  21 +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
  22 @@ -0,0 +1,58 @@
  23 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  24 +%YAML 1.2
  25 +---
  26 +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
  27 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  28 +
  29 +title: StarFive JH7110 PCIe 2.0 PHY
  30 +
  31 +maintainers:
  32 +  - Minda Chen <minda.chen@starfivetech.com>
  33 +
  34 +properties:
  35 +  compatible:
  36 +    const: starfive,jh7110-pcie-phy
  37 +
  38 +  reg:
  39 +    maxItems: 1
  40 +
  41 +  "#phy-cells":
  42 +    const: 0
  43 +
  44 +  starfive,sys-syscon:
  45 +    $ref: /schemas/types.yaml#/definitions/phandle-array
  46 +    items:
  47 +      - items:
  48 +          - description: phandle to System Register Controller sys_syscon node.
  49 +          - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
  50 +    description:
  51 +      The phandle to System Register Controller syscon node and the PHY connect offset
  52 +      of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
  53 +
  54 +  starfive,stg-syscon:
  55 +    $ref: /schemas/types.yaml#/definitions/phandle-array
  56 +    items:
  57 +      - items:
  58 +          - description: phandle to System Register Controller stg_syscon node.
  59 +          - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
  60 +          - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
  61 +    description:
  62 +      The phandle to System Register Controller syscon node and the offset
  63 +      of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
  64 +
  65 +required:
  66 +  - compatible
  67 +  - reg
  68 +  - "#phy-cells"
  69 +
  70 +additionalProperties: false
  71 +
  72 +examples:
  73 +  - |
  74 +    phy@10210000 {
  75 +        compatible = "starfive,jh7110-pcie-phy";
  76 +        reg = <0x10210000 0x10000>;
  77 +        #phy-cells = <0>;
  78 +        starfive,sys-syscon = <&sys_syscon 0x18>;
  79 +        starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
  80 +    };
  81 --
  82 2.20.1
  83