jh71x0: refresh patches and configs once again
[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0087-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch
1 From 2ebd77fa8fb95f60b275cefb98ea7d6f4df06e55 Mon Sep 17 00:00:00 2001
2 From: Minda Chen <minda.chen@starfivetech.com>
3 Date: Thu, 18 May 2023 19:27:44 +0800
4 Subject: [PATCH 087/122] dt-bindings: phy: Add StarFive JH7110 USB PHY
5
6 Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.
7
8 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
9 Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
10 Reviewed-by: Rob Herring <robh@kernel.org>
11 ---
12 .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++
13 1 file changed, 50 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
15
16 diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
17 new file mode 100644
18 index 000000000000..269e9f9f12b6
19 --- /dev/null
20 +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
21 @@ -0,0 +1,50 @@
22 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
23 +%YAML 1.2
24 +---
25 +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
26 +$schema: http://devicetree.org/meta-schemas/core.yaml#
27 +
28 +title: StarFive JH7110 USB 2.0 PHY
29 +
30 +maintainers:
31 + - Minda Chen <minda.chen@starfivetech.com>
32 +
33 +properties:
34 + compatible:
35 + const: starfive,jh7110-usb-phy
36 +
37 + reg:
38 + maxItems: 1
39 +
40 + "#phy-cells":
41 + const: 0
42 +
43 + clocks:
44 + items:
45 + - description: PHY 125m
46 + - description: app 125m
47 +
48 + clock-names:
49 + items:
50 + - const: 125m
51 + - const: app_125m
52 +
53 +required:
54 + - compatible
55 + - reg
56 + - clocks
57 + - clock-names
58 + - "#phy-cells"
59 +
60 +additionalProperties: false
61 +
62 +examples:
63 + - |
64 + phy@10200000 {
65 + compatible = "starfive,jh7110-usb-phy";
66 + reg = <0x10200000 0x10000>;
67 + clocks = <&syscrg 95>,
68 + <&stgcrg 6>;
69 + clock-names = "125m", "app_125m";
70 + #phy-cells = <0>;
71 + };
72 --
73 2.20.1
74