target/linux/jh71x0/patches-6.1/0047-riscv-dts-starfive-visionfive-2-Add-configuration-of.patch

   1 From 6fd84cb9cceaa711671500a92dcee5b1072ab95a Mon Sep 17 00:00:00 2001
   2 From: Samin Guo <samin.guo@starfivetech.com>
   3 Date: Tue, 1 Nov 2022 18:11:02 +0800
   4 Subject: [PATCH 047/122] riscv: dts: starfive: visionfive 2: Add configuration
   5  of gmac and phy
   6
   7 v1.3B:
   8   v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and
   9   inverse configurations.
  10   The tx_clk of v1.3B uses an external clock and needs to be
  11   switched to an external clock source.
  12
  13 v1.2A:
  14   v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay
  15   configurations.
  16   v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to
  17   switch rx and rx to external clock sources.
  18
  19 Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
  20 Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
  21 ---
  22  .../jh7110-starfive-visionfive-2-v1.2a.dts    | 13 +++++++
  23  .../jh7110-starfive-visionfive-2-v1.3b.dts    | 27 +++++++++++++++
  24  .../jh7110-starfive-visionfive-2.dtsi         | 34 +++++++++++++++++++
  25  3 files changed, 74 insertions(+)
  26
  27 diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
  28 index 4af3300f3cf3..205a13d8c8b1 100644
  29 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
  30 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
  31 @@ -11,3 +11,16 @@
  32         model = "StarFive VisionFive 2 v1.2A";
  33         compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
  34  };
  35 +
  36 +&gmac1 {
  37 +       phy-mode = "rmii";
  38 +       assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
  39 +                         <&syscrg JH7110_SYSCLK_GMAC1_RX>;
  40 +       assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
  41 +                                <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
  42 +};
  43 +
  44 +&phy0 {
  45 +       rx-internal-delay-ps = <1900>;
  46 +       tx-internal-delay-ps = <1350>;
  47 +};
  48 diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
  49 index 9230cc3d8946..ff01bea01372 100644
  50 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
  51 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
  52 @@ -11,3 +11,30 @@
  53         model = "StarFive VisionFive 2 v1.3B";
  54         compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
  55  };
  56 +
  57 +&gmac0 {
  58 +       starfive,tx-use-rgmii-clk;
  59 +       assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
  60 +       assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
  61 +};
  62 +
  63 +&gmac1 {
  64 +       starfive,tx-use-rgmii-clk;
  65 +       assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
  66 +       assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
  67 +};
  68 +
  69 +&phy0 {
  70 +       motorcomm,tx-clk-adj-enabled;
  71 +       motorcomm,tx-clk-100-inverted;
  72 +       motorcomm,tx-clk-1000-inverted;
  73 +       rx-internal-delay-ps = <1500>;
  74 +       tx-internal-delay-ps = <1500>;
  75 +};
  76 +
  77 +&phy1 {
  78 +       motorcomm,tx-clk-adj-enabled;
  79 +       motorcomm,tx-clk-100-inverted;
  80 +       rx-internal-delay-ps = <300>;
  81 +       tx-internal-delay-ps = <0>;
  82 +};
  83 diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
  84 index 2a6d81609284..8d5b36fbd420 100644
  85 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
  86 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
  87 @@ -11,6 +11,8 @@
  88
  89  / {
  90         aliases {
  91 +               ethernet0 = &gmac0;
  92 +               ethernet1 = &gmac1;
  93                 i2c0 = &i2c0;
  94                 i2c2 = &i2c2;
  95                 i2c5 = &i2c5;
  96 @@ -86,6 +88,38 @@
  97         clock-frequency = <49152000>;
  98  };
  99
 100 +&gmac0 {
 101 +       phy-handle = <&phy0>;
 102 +       phy-mode = "rgmii-id";
 103 +       status = "okay";
 104 +
 105 +       mdio {
 106 +               #address-cells = <1>;
 107 +               #size-cells = <0>;
 108 +               compatible = "snps,dwmac-mdio";
 109 +
 110 +               phy0: ethernet-phy@0 {
 111 +                       reg = <0>;
 112 +               };
 113 +       };
 114 +};
 115 +
 116 +&gmac1 {
 117 +       phy-handle = <&phy1>;
 118 +       phy-mode = "rgmii-id";
 119 +       status = "okay";
 120 +
 121 +       mdio {
 122 +               #address-cells = <1>;
 123 +               #size-cells = <0>;
 124 +               compatible = "snps,dwmac-mdio";
 125 +
 126 +               phy1: ethernet-phy@1 {
 127 +                       reg = <0>;
 128 +               };
 129 +       };
 130 +};
 131 +
 132  &i2c0 {
 133         clock-frequency = <100000>;
 134         i2c-sda-hold-time-ns = <300>;
 135 --
 136 2.20.1
 137