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jh71x0: refresh patches and configs once again
[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0028-pinctrl-starfive-Add-StarFive-JH7110-sys-controller-.patch
1 From 4dba3156173e59131d234d702388ee7283bac8a9 Mon Sep 17 00:00:00 2001
2 From: Jianlong Huang <jianlong.huang@starfivetech.com>
3 Date: Thu, 9 Feb 2023 22:37:01 +0800
4 Subject: [PATCH 028/122] pinctrl: starfive: Add StarFive JH7110 sys controller
5 driver
6
7 Add pinctrl driver for StarFive JH7110 SoC sys pinctrl controller.
8
9 Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
10 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
11 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
12 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
13 ---
14 MAINTAINERS | 2 +-
15 drivers/pinctrl/starfive/Kconfig | 21 +
16 drivers/pinctrl/starfive/Makefile | 3 +
17 .../starfive/pinctrl-starfive-jh7110-sys.c | 449 ++++++++
18 .../starfive/pinctrl-starfive-jh7110.c | 982 ++++++++++++++++++
19 .../starfive/pinctrl-starfive-jh7110.h | 70 ++
20 6 files changed, 1526 insertions(+), 1 deletion(-)
21 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
22 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
23 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h
24
25 diff --git a/MAINTAINERS b/MAINTAINERS
26 index e490b6e55d2a..86d60276b2b9 100644
27 --- a/MAINTAINERS
28 +++ b/MAINTAINERS
29 @@ -19648,7 +19648,7 @@ M: Jianlong Huang <jianlong.huang@starfivetech.com>
30 L: linux-gpio@vger.kernel.org
31 S: Maintained
32 F: Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml
33 -F: drivers/pinctrl/starfive/
34 +F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
35 F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
36 F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
37
38 diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
39 index 55c514e622f9..453c8a0b3118 100644
40 --- a/drivers/pinctrl/starfive/Kconfig
41 +++ b/drivers/pinctrl/starfive/Kconfig
42 @@ -16,3 +16,24 @@ config PINCTRL_STARFIVE_JH7100
43 This also provides an interface to the GPIO pins not used by other
44 peripherals supporting inputs, outputs, configuring pull-up/pull-down
45 and interrupts on input changes.
46 +
47 +config PINCTRL_STARFIVE_JH7110
48 + bool
49 + select GENERIC_PINCTRL_GROUPS
50 + select GENERIC_PINMUX_FUNCTIONS
51 + select GENERIC_PINCONF
52 + select GPIOLIB
53 + select GPIOLIB_IRQCHIP
54 + select OF_GPIO
55 +
56 +config PINCTRL_STARFIVE_JH7110_SYS
57 + tristate "System pinctrl and GPIO driver for the StarFive JH7110 SoC"
58 + depends on SOC_STARFIVE || COMPILE_TEST
59 + depends on OF
60 + select PINCTRL_STARFIVE_JH7110
61 + default SOC_STARFIVE
62 + help
63 + Say yes here to support system pin control on the StarFive JH7110 SoC.
64 + This also provides an interface to the GPIO pins not used by other
65 + peripherals supporting inputs, outputs, configuring pull-up/pull-down
66 + and interrupts on input changes.
67 diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
68 index 0293f26a0a99..dc2d1e392314 100644
69 --- a/drivers/pinctrl/starfive/Makefile
70 +++ b/drivers/pinctrl/starfive/Makefile
71 @@ -1,3 +1,6 @@
72 # SPDX-License-Identifier: GPL-2.0
73
74 obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
75 +
76 +obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o
77 +obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
78 diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
79 new file mode 100644
80 index 000000000000..bc279a39613f
81 --- /dev/null
82 +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
83 @@ -0,0 +1,449 @@
84 +// SPDX-License-Identifier: GPL-2.0
85 +/*
86 + * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller
87 + *
88 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
89 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
90 + */
91 +
92 +#include <linux/bits.h>
93 +#include <linux/clk.h>
94 +#include <linux/gpio/driver.h>
95 +#include <linux/io.h>
96 +#include <linux/mod_devicetable.h>
97 +#include <linux/module.h>
98 +#include <linux/mutex.h>
99 +#include <linux/of.h>
100 +#include <linux/of_device.h>
101 +#include <linux/platform_device.h>
102 +#include <linux/reset.h>
103 +#include <linux/spinlock.h>
104 +
105 +#include <linux/pinctrl/pinctrl.h>
106 +#include <linux/pinctrl/pinmux.h>
107 +
108 +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
109 +
110 +#include "../core.h"
111 +#include "../pinctrl-utils.h"
112 +#include "../pinmux.h"
113 +#include "../pinconf.h"
114 +#include "pinctrl-starfive-jh7110.h"
115 +
116 +#define JH7110_SYS_NGPIO 64
117 +#define JH7110_SYS_GC_BASE 0
118 +
119 +/* registers */
120 +#define JH7110_SYS_DOEN 0x000
121 +#define JH7110_SYS_DOUT 0x040
122 +#define JH7110_SYS_GPI 0x080
123 +#define JH7110_SYS_GPIOIN 0x118
124 +
125 +#define JH7110_SYS_GPIOEN 0x0dc
126 +#define JH7110_SYS_GPIOIS0 0x0e0
127 +#define JH7110_SYS_GPIOIS1 0x0e4
128 +#define JH7110_SYS_GPIOIC0 0x0e8
129 +#define JH7110_SYS_GPIOIC1 0x0ec
130 +#define JH7110_SYS_GPIOIBE0 0x0f0
131 +#define JH7110_SYS_GPIOIBE1 0x0f4
132 +#define JH7110_SYS_GPIOIEV0 0x0f8
133 +#define JH7110_SYS_GPIOIEV1 0x0fc
134 +#define JH7110_SYS_GPIOIE0 0x100
135 +#define JH7110_SYS_GPIOIE1 0x104
136 +#define JH7110_SYS_GPIORIS0 0x108
137 +#define JH7110_SYS_GPIORIS1 0x10c
138 +#define JH7110_SYS_GPIOMIS0 0x110
139 +#define JH7110_SYS_GPIOMIS1 0x114
140 +
141 +#define JH7110_SYS_GPO_PDA_0_74_CFG 0x120
142 +#define JH7110_SYS_GPO_PDA_89_94_CFG 0x284
143 +
144 +static const struct pinctrl_pin_desc jh7110_sys_pins[] = {
145 + PINCTRL_PIN(PAD_GPIO0, "GPIO0"),
146 + PINCTRL_PIN(PAD_GPIO1, "GPIO1"),
147 + PINCTRL_PIN(PAD_GPIO2, "GPIO2"),
148 + PINCTRL_PIN(PAD_GPIO3, "GPIO3"),
149 + PINCTRL_PIN(PAD_GPIO4, "GPIO4"),
150 + PINCTRL_PIN(PAD_GPIO5, "GPIO5"),
151 + PINCTRL_PIN(PAD_GPIO6, "GPIO6"),
152 + PINCTRL_PIN(PAD_GPIO7, "GPIO7"),
153 + PINCTRL_PIN(PAD_GPIO8, "GPIO8"),
154 + PINCTRL_PIN(PAD_GPIO9, "GPIO9"),
155 + PINCTRL_PIN(PAD_GPIO10, "GPIO10"),
156 + PINCTRL_PIN(PAD_GPIO11, "GPIO11"),
157 + PINCTRL_PIN(PAD_GPIO12, "GPIO12"),
158 + PINCTRL_PIN(PAD_GPIO13, "GPIO13"),
159 + PINCTRL_PIN(PAD_GPIO14, "GPIO14"),
160 + PINCTRL_PIN(PAD_GPIO15, "GPIO15"),
161 + PINCTRL_PIN(PAD_GPIO16, "GPIO16"),
162 + PINCTRL_PIN(PAD_GPIO17, "GPIO17"),
163 + PINCTRL_PIN(PAD_GPIO18, "GPIO18"),
164 + PINCTRL_PIN(PAD_GPIO19, "GPIO19"),
165 + PINCTRL_PIN(PAD_GPIO20, "GPIO20"),
166 + PINCTRL_PIN(PAD_GPIO21, "GPIO21"),
167 + PINCTRL_PIN(PAD_GPIO22, "GPIO22"),
168 + PINCTRL_PIN(PAD_GPIO23, "GPIO23"),
169 + PINCTRL_PIN(PAD_GPIO24, "GPIO24"),
170 + PINCTRL_PIN(PAD_GPIO25, "GPIO25"),
171 + PINCTRL_PIN(PAD_GPIO26, "GPIO26"),
172 + PINCTRL_PIN(PAD_GPIO27, "GPIO27"),
173 + PINCTRL_PIN(PAD_GPIO28, "GPIO28"),
174 + PINCTRL_PIN(PAD_GPIO29, "GPIO29"),
175 + PINCTRL_PIN(PAD_GPIO30, "GPIO30"),
176 + PINCTRL_PIN(PAD_GPIO31, "GPIO31"),
177 + PINCTRL_PIN(PAD_GPIO32, "GPIO32"),
178 + PINCTRL_PIN(PAD_GPIO33, "GPIO33"),
179 + PINCTRL_PIN(PAD_GPIO34, "GPIO34"),
180 + PINCTRL_PIN(PAD_GPIO35, "GPIO35"),
181 + PINCTRL_PIN(PAD_GPIO36, "GPIO36"),
182 + PINCTRL_PIN(PAD_GPIO37, "GPIO37"),
183 + PINCTRL_PIN(PAD_GPIO38, "GPIO38"),
184 + PINCTRL_PIN(PAD_GPIO39, "GPIO39"),
185 + PINCTRL_PIN(PAD_GPIO40, "GPIO40"),
186 + PINCTRL_PIN(PAD_GPIO41, "GPIO41"),
187 + PINCTRL_PIN(PAD_GPIO42, "GPIO42"),
188 + PINCTRL_PIN(PAD_GPIO43, "GPIO43"),
189 + PINCTRL_PIN(PAD_GPIO44, "GPIO44"),
190 + PINCTRL_PIN(PAD_GPIO45, "GPIO45"),
191 + PINCTRL_PIN(PAD_GPIO46, "GPIO46"),
192 + PINCTRL_PIN(PAD_GPIO47, "GPIO47"),
193 + PINCTRL_PIN(PAD_GPIO48, "GPIO48"),
194 + PINCTRL_PIN(PAD_GPIO49, "GPIO49"),
195 + PINCTRL_PIN(PAD_GPIO50, "GPIO50"),
196 + PINCTRL_PIN(PAD_GPIO51, "GPIO51"),
197 + PINCTRL_PIN(PAD_GPIO52, "GPIO52"),
198 + PINCTRL_PIN(PAD_GPIO53, "GPIO53"),
199 + PINCTRL_PIN(PAD_GPIO54, "GPIO54"),
200 + PINCTRL_PIN(PAD_GPIO55, "GPIO55"),
201 + PINCTRL_PIN(PAD_GPIO56, "GPIO56"),
202 + PINCTRL_PIN(PAD_GPIO57, "GPIO57"),
203 + PINCTRL_PIN(PAD_GPIO58, "GPIO58"),
204 + PINCTRL_PIN(PAD_GPIO59, "GPIO59"),
205 + PINCTRL_PIN(PAD_GPIO60, "GPIO60"),
206 + PINCTRL_PIN(PAD_GPIO61, "GPIO61"),
207 + PINCTRL_PIN(PAD_GPIO62, "GPIO62"),
208 + PINCTRL_PIN(PAD_GPIO63, "GPIO63"),
209 + PINCTRL_PIN(PAD_SD0_CLK, "SD0_CLK"),
210 + PINCTRL_PIN(PAD_SD0_CMD, "SD0_CMD"),
211 + PINCTRL_PIN(PAD_SD0_DATA0, "SD0_DATA0"),
212 + PINCTRL_PIN(PAD_SD0_DATA1, "SD0_DATA1"),
213 + PINCTRL_PIN(PAD_SD0_DATA2, "SD0_DATA2"),
214 + PINCTRL_PIN(PAD_SD0_DATA3, "SD0_DATA3"),
215 + PINCTRL_PIN(PAD_SD0_DATA4, "SD0_DATA4"),
216 + PINCTRL_PIN(PAD_SD0_DATA5, "SD0_DATA5"),
217 + PINCTRL_PIN(PAD_SD0_DATA6, "SD0_DATA6"),
218 + PINCTRL_PIN(PAD_SD0_DATA7, "SD0_DATA7"),
219 + PINCTRL_PIN(PAD_SD0_STRB, "SD0_STRB"),
220 + PINCTRL_PIN(PAD_GMAC1_MDC, "GMAC1_MDC"),
221 + PINCTRL_PIN(PAD_GMAC1_MDIO, "GMAC1_MDIO"),
222 + PINCTRL_PIN(PAD_GMAC1_RXD0, "GMAC1_RXD0"),
223 + PINCTRL_PIN(PAD_GMAC1_RXD1, "GMAC1_RXD1"),
224 + PINCTRL_PIN(PAD_GMAC1_RXD2, "GMAC1_RXD2"),
225 + PINCTRL_PIN(PAD_GMAC1_RXD3, "GMAC1_RXD3"),
226 + PINCTRL_PIN(PAD_GMAC1_RXDV, "GMAC1_RXDV"),
227 + PINCTRL_PIN(PAD_GMAC1_RXC, "GMAC1_RXC"),
228 + PINCTRL_PIN(PAD_GMAC1_TXD0, "GMAC1_TXD0"),
229 + PINCTRL_PIN(PAD_GMAC1_TXD1, "GMAC1_TXD1"),
230 + PINCTRL_PIN(PAD_GMAC1_TXD2, "GMAC1_TXD2"),
231 + PINCTRL_PIN(PAD_GMAC1_TXD3, "GMAC1_TXD3"),
232 + PINCTRL_PIN(PAD_GMAC1_TXEN, "GMAC1_TXEN"),
233 + PINCTRL_PIN(PAD_GMAC1_TXC, "GMAC1_TXC"),
234 + PINCTRL_PIN(PAD_QSPI_SCLK, "QSPI_SCLK"),
235 + PINCTRL_PIN(PAD_QSPI_CS0, "QSPI_CS0"),
236 + PINCTRL_PIN(PAD_QSPI_DATA0, "QSPI_DATA0"),
237 + PINCTRL_PIN(PAD_QSPI_DATA1, "QSPI_DATA1"),
238 + PINCTRL_PIN(PAD_QSPI_DATA2, "QSPI_DATA2"),
239 + PINCTRL_PIN(PAD_QSPI_DATA3, "QSPI_DATA3"),
240 +};
241 +
242 +struct jh7110_func_sel {
243 + u16 offset;
244 + u8 shift;
245 + u8 max;
246 +};
247 +
248 +static const struct jh7110_func_sel
249 + jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
250 + [PAD_GMAC1_RXC] = { 0x29c, 0, 1 },
251 + [PAD_GPIO10] = { 0x29c, 2, 3 },
252 + [PAD_GPIO11] = { 0x29c, 5, 3 },
253 + [PAD_GPIO12] = { 0x29c, 8, 3 },
254 + [PAD_GPIO13] = { 0x29c, 11, 3 },
255 + [PAD_GPIO14] = { 0x29c, 14, 3 },
256 + [PAD_GPIO15] = { 0x29c, 17, 3 },
257 + [PAD_GPIO16] = { 0x29c, 20, 3 },
258 + [PAD_GPIO17] = { 0x29c, 23, 3 },
259 + [PAD_GPIO18] = { 0x29c, 26, 3 },
260 + [PAD_GPIO19] = { 0x29c, 29, 3 },
261 +
262 + [PAD_GPIO20] = { 0x2a0, 0, 3 },
263 + [PAD_GPIO21] = { 0x2a0, 3, 3 },
264 + [PAD_GPIO22] = { 0x2a0, 6, 3 },
265 + [PAD_GPIO23] = { 0x2a0, 9, 3 },
266 + [PAD_GPIO24] = { 0x2a0, 12, 3 },
267 + [PAD_GPIO25] = { 0x2a0, 15, 3 },
268 + [PAD_GPIO26] = { 0x2a0, 18, 3 },
269 + [PAD_GPIO27] = { 0x2a0, 21, 3 },
270 + [PAD_GPIO28] = { 0x2a0, 24, 3 },
271 + [PAD_GPIO29] = { 0x2a0, 27, 3 },
272 +
273 + [PAD_GPIO30] = { 0x2a4, 0, 3 },
274 + [PAD_GPIO31] = { 0x2a4, 3, 3 },
275 + [PAD_GPIO32] = { 0x2a4, 6, 3 },
276 + [PAD_GPIO33] = { 0x2a4, 9, 3 },
277 + [PAD_GPIO34] = { 0x2a4, 12, 3 },
278 + [PAD_GPIO35] = { 0x2a4, 15, 3 },
279 + [PAD_GPIO36] = { 0x2a4, 17, 3 },
280 + [PAD_GPIO37] = { 0x2a4, 20, 3 },
281 + [PAD_GPIO38] = { 0x2a4, 23, 3 },
282 + [PAD_GPIO39] = { 0x2a4, 26, 3 },
283 + [PAD_GPIO40] = { 0x2a4, 29, 3 },
284 +
285 + [PAD_GPIO41] = { 0x2a8, 0, 3 },
286 + [PAD_GPIO42] = { 0x2a8, 3, 3 },
287 + [PAD_GPIO43] = { 0x2a8, 6, 3 },
288 + [PAD_GPIO44] = { 0x2a8, 9, 3 },
289 + [PAD_GPIO45] = { 0x2a8, 12, 3 },
290 + [PAD_GPIO46] = { 0x2a8, 15, 3 },
291 + [PAD_GPIO47] = { 0x2a8, 18, 3 },
292 + [PAD_GPIO48] = { 0x2a8, 21, 3 },
293 + [PAD_GPIO49] = { 0x2a8, 24, 3 },
294 + [PAD_GPIO50] = { 0x2a8, 27, 3 },
295 + [PAD_GPIO51] = { 0x2a8, 30, 3 },
296 +
297 + [PAD_GPIO52] = { 0x2ac, 0, 3 },
298 + [PAD_GPIO53] = { 0x2ac, 2, 3 },
299 + [PAD_GPIO54] = { 0x2ac, 4, 3 },
300 + [PAD_GPIO55] = { 0x2ac, 6, 3 },
301 + [PAD_GPIO56] = { 0x2ac, 9, 3 },
302 + [PAD_GPIO57] = { 0x2ac, 12, 3 },
303 + [PAD_GPIO58] = { 0x2ac, 15, 3 },
304 + [PAD_GPIO59] = { 0x2ac, 18, 3 },
305 + [PAD_GPIO60] = { 0x2ac, 21, 3 },
306 + [PAD_GPIO61] = { 0x2ac, 24, 3 },
307 + [PAD_GPIO62] = { 0x2ac, 27, 3 },
308 + [PAD_GPIO63] = { 0x2ac, 30, 3 },
309 +
310 + [PAD_GPIO6] = { 0x2b0, 0, 3 },
311 + [PAD_GPIO7] = { 0x2b0, 2, 3 },
312 + [PAD_GPIO8] = { 0x2b0, 5, 3 },
313 + [PAD_GPIO9] = { 0x2b0, 8, 3 },
314 +};
315 +
316 +struct jh7110_vin_group_sel {
317 + u16 offset;
318 + u8 shift;
319 + u8 group;
320 +};
321 +
322 +static const struct jh7110_vin_group_sel
323 + jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
324 + [PAD_GPIO6] = { 0x2b4, 21, 0 },
325 + [PAD_GPIO7] = { 0x2b4, 18, 0 },
326 + [PAD_GPIO8] = { 0x2b4, 15, 0 },
327 + [PAD_GPIO9] = { 0x2b0, 11, 0 },
328 + [PAD_GPIO10] = { 0x2b0, 20, 0 },
329 + [PAD_GPIO11] = { 0x2b0, 23, 0 },
330 + [PAD_GPIO12] = { 0x2b0, 26, 0 },
331 + [PAD_GPIO13] = { 0x2b0, 29, 0 },
332 + [PAD_GPIO14] = { 0x2b4, 0, 0 },
333 + [PAD_GPIO15] = { 0x2b4, 3, 0 },
334 + [PAD_GPIO16] = { 0x2b4, 6, 0 },
335 + [PAD_GPIO17] = { 0x2b4, 9, 0 },
336 + [PAD_GPIO18] = { 0x2b4, 12, 0 },
337 + [PAD_GPIO19] = { 0x2b0, 14, 0 },
338 + [PAD_GPIO20] = { 0x2b0, 17, 0 },
339 +
340 + [PAD_GPIO21] = { 0x2b4, 21, 1 },
341 + [PAD_GPIO22] = { 0x2b4, 18, 1 },
342 + [PAD_GPIO23] = { 0x2b4, 15, 1 },
343 + [PAD_GPIO24] = { 0x2b0, 11, 1 },
344 + [PAD_GPIO25] = { 0x2b0, 20, 1 },
345 + [PAD_GPIO26] = { 0x2b0, 23, 1 },
346 + [PAD_GPIO27] = { 0x2b0, 26, 1 },
347 + [PAD_GPIO28] = { 0x2b0, 29, 1 },
348 + [PAD_GPIO29] = { 0x2b4, 0, 1 },
349 + [PAD_GPIO30] = { 0x2b4, 3, 1 },
350 + [PAD_GPIO31] = { 0x2b4, 6, 1 },
351 + [PAD_GPIO32] = { 0x2b4, 9, 1 },
352 + [PAD_GPIO33] = { 0x2b4, 12, 1 },
353 + [PAD_GPIO34] = { 0x2b0, 14, 1 },
354 + [PAD_GPIO35] = { 0x2b0, 17, 1 },
355 +
356 + [PAD_GPIO36] = { 0x2b4, 21, 2 },
357 + [PAD_GPIO37] = { 0x2b4, 18, 2 },
358 + [PAD_GPIO38] = { 0x2b4, 15, 2 },
359 + [PAD_GPIO39] = { 0x2b0, 11, 2 },
360 + [PAD_GPIO40] = { 0x2b0, 20, 2 },
361 + [PAD_GPIO41] = { 0x2b0, 23, 2 },
362 + [PAD_GPIO42] = { 0x2b0, 26, 2 },
363 + [PAD_GPIO43] = { 0x2b0, 29, 2 },
364 + [PAD_GPIO44] = { 0x2b4, 0, 2 },
365 + [PAD_GPIO45] = { 0x2b4, 3, 2 },
366 + [PAD_GPIO46] = { 0x2b4, 6, 2 },
367 + [PAD_GPIO47] = { 0x2b4, 9, 2 },
368 + [PAD_GPIO48] = { 0x2b4, 12, 2 },
369 + [PAD_GPIO49] = { 0x2b0, 14, 2 },
370 + [PAD_GPIO50] = { 0x2b0, 17, 2 },
371 +};
372 +
373 +static void jh7110_set_function(struct jh7110_pinctrl *sfp,
374 + unsigned int pin, u32 func)
375 +{
376 + const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
377 + unsigned long flags;
378 + void __iomem *reg;
379 + u32 mask;
380 +
381 + if (!fs->offset)
382 + return;
383 +
384 + if (func > fs->max)
385 + return;
386 +
387 + reg = sfp->base + fs->offset;
388 + func = func << fs->shift;
389 + mask = 0x3U << fs->shift;
390 +
391 + raw_spin_lock_irqsave(&sfp->lock, flags);
392 + func |= readl_relaxed(reg) & ~mask;
393 + writel_relaxed(func, reg);
394 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
395 +}
396 +
397 +static void jh7110_set_vin_group(struct jh7110_pinctrl *sfp,
398 + unsigned int pin)
399 +{
400 + const struct jh7110_vin_group_sel *gs = &jh7110_sys_vin_group_sel[pin];
401 + unsigned long flags;
402 + void __iomem *reg;
403 + u32 mask;
404 + u32 grp;
405 +
406 + if (!gs->offset)
407 + return;
408 +
409 + reg = sfp->base + gs->offset;
410 + grp = gs->group << gs->shift;
411 + mask = 0x3U << gs->shift;
412 +
413 + raw_spin_lock_irqsave(&sfp->lock, flags);
414 + grp |= readl_relaxed(reg) & ~mask;
415 + writel_relaxed(grp, reg);
416 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
417 +}
418 +
419 +static int jh7110_sys_set_one_pin_mux(struct jh7110_pinctrl *sfp,
420 + unsigned int pin,
421 + unsigned int din, u32 dout,
422 + u32 doen, u32 func)
423 +{
424 + if (pin < sfp->gc.ngpio && func == 0)
425 + jh7110_set_gpiomux(sfp, pin, din, dout, doen);
426 +
427 + jh7110_set_function(sfp, pin, func);
428 +
429 + if (pin < sfp->gc.ngpio && func == 2)
430 + jh7110_set_vin_group(sfp, pin);
431 +
432 + return 0;
433 +}
434 +
435 +static int jh7110_sys_get_padcfg_base(struct jh7110_pinctrl *sfp,
436 + unsigned int pin)
437 +{
438 + if (pin < PAD_GMAC1_MDC)
439 + return JH7110_SYS_GPO_PDA_0_74_CFG;
440 + else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
441 + return JH7110_SYS_GPO_PDA_89_94_CFG;
442 + else
443 + return -1;
444 +}
445 +
446 +static void jh7110_sys_irq_handler(struct irq_desc *desc)
447 +{
448 + struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc);
449 + struct irq_chip *chip = irq_desc_get_chip(desc);
450 + unsigned long mis;
451 + unsigned int pin;
452 +
453 + chained_irq_enter(chip, desc);
454 +
455 + mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0);
456 + for_each_set_bit(pin, &mis, 32)
457 + generic_handle_domain_irq(sfp->gc.irq.domain, pin);
458 +
459 + mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1);
460 + for_each_set_bit(pin, &mis, 32)
461 + generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
462 +
463 + chained_irq_exit(chip, desc);
464 +}
465 +
466 +static int jh7110_sys_init_hw(struct gpio_chip *gc)
467 +{
468 + struct jh7110_pinctrl *sfp = container_of(gc,
469 + struct jh7110_pinctrl, gc);
470 +
471 + /* mask all GPIO interrupts */
472 + writel(0U, sfp->base + JH7110_SYS_GPIOIE0);
473 + writel(0U, sfp->base + JH7110_SYS_GPIOIE1);
474 + /* clear edge interrupt flags */
475 + writel(~0U, sfp->base + JH7110_SYS_GPIOIC0);
476 + writel(~0U, sfp->base + JH7110_SYS_GPIOIC1);
477 + /* enable GPIO interrupts */
478 + writel(1U, sfp->base + JH7110_SYS_GPIOEN);
479 + return 0;
480 +}
481 +
482 +static const struct jh7110_gpio_irq_reg jh7110_sys_irq_reg = {
483 + .is_reg_base = JH7110_SYS_GPIOIS0,
484 + .ic_reg_base = JH7110_SYS_GPIOIC0,
485 + .ibe_reg_base = JH7110_SYS_GPIOIBE0,
486 + .iev_reg_base = JH7110_SYS_GPIOIEV0,
487 + .ie_reg_base = JH7110_SYS_GPIOIE0,
488 + .ris_reg_base = JH7110_SYS_GPIORIS0,
489 + .mis_reg_base = JH7110_SYS_GPIOMIS0,
490 +};
491 +
492 +static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = {
493 + .pins = jh7110_sys_pins,
494 + .npins = ARRAY_SIZE(jh7110_sys_pins),
495 + .ngpios = JH7110_SYS_NGPIO,
496 + .gc_base = JH7110_SYS_GC_BASE,
497 + .dout_reg_base = JH7110_SYS_DOUT,
498 + .dout_mask = GENMASK(6, 0),
499 + .doen_reg_base = JH7110_SYS_DOEN,
500 + .doen_mask = GENMASK(5, 0),
501 + .gpi_reg_base = JH7110_SYS_GPI,
502 + .gpi_mask = GENMASK(6, 0),
503 + .gpioin_reg_base = JH7110_SYS_GPIOIN,
504 + .irq_reg = &jh7110_sys_irq_reg,
505 + .jh7110_set_one_pin_mux = jh7110_sys_set_one_pin_mux,
506 + .jh7110_get_padcfg_base = jh7110_sys_get_padcfg_base,
507 + .jh7110_gpio_irq_handler = jh7110_sys_irq_handler,
508 + .jh7110_gpio_init_hw = jh7110_sys_init_hw,
509 +};
510 +
511 +static const struct of_device_id jh7110_sys_pinctrl_of_match[] = {
512 + {
513 + .compatible = "starfive,jh7110-sys-pinctrl",
514 + .data = &jh7110_sys_pinctrl_info,
515 + },
516 + { /* sentinel */ }
517 +};
518 +MODULE_DEVICE_TABLE(of, jh7110_sys_pinctrl_of_match);
519 +
520 +static struct platform_driver jh7110_sys_pinctrl_driver = {
521 + .probe = jh7110_pinctrl_probe,
522 + .driver = {
523 + .name = "starfive-jh7110-sys-pinctrl",
524 + .of_match_table = jh7110_sys_pinctrl_of_match,
525 + },
526 +};
527 +module_platform_driver(jh7110_sys_pinctrl_driver);
528 +
529 +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC sys controller");
530 +MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
531 +MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
532 +MODULE_LICENSE("GPL");
533 diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
534 new file mode 100644
535 index 000000000000..5fe729b4a03d
536 --- /dev/null
537 +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
538 @@ -0,0 +1,982 @@
539 +// SPDX-License-Identifier: GPL-2.0
540 +/*
541 + * Pinctrl / GPIO driver for StarFive JH7110 SoC
542 + *
543 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
544 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
545 + */
546 +
547 +#include <linux/bits.h>
548 +#include <linux/clk.h>
549 +#include <linux/gpio/driver.h>
550 +#include <linux/io.h>
551 +#include <linux/mod_devicetable.h>
552 +#include <linux/module.h>
553 +#include <linux/mutex.h>
554 +#include <linux/of.h>
555 +#include <linux/of_device.h>
556 +#include <linux/platform_device.h>
557 +#include <linux/reset.h>
558 +#include <linux/seq_file.h>
559 +#include <linux/spinlock.h>
560 +
561 +#include <linux/pinctrl/consumer.h>
562 +#include <linux/pinctrl/pinconf.h>
563 +#include <linux/pinctrl/pinctrl.h>
564 +#include <linux/pinctrl/pinmux.h>
565 +
566 +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
567 +
568 +#include "../core.h"
569 +#include "../pinctrl-utils.h"
570 +#include "../pinmux.h"
571 +#include "../pinconf.h"
572 +#include "pinctrl-starfive-jh7110.h"
573 +
574 +/* pad control bits */
575 +#define JH7110_PADCFG_POS BIT(7)
576 +#define JH7110_PADCFG_SMT BIT(6)
577 +#define JH7110_PADCFG_SLEW BIT(5)
578 +#define JH7110_PADCFG_PD BIT(4)
579 +#define JH7110_PADCFG_PU BIT(3)
580 +#define JH7110_PADCFG_BIAS (JH7110_PADCFG_PD | JH7110_PADCFG_PU)
581 +#define JH7110_PADCFG_DS_MASK GENMASK(2, 1)
582 +#define JH7110_PADCFG_DS_2MA (0U << 1)
583 +#define JH7110_PADCFG_DS_4MA BIT(1)
584 +#define JH7110_PADCFG_DS_8MA (2U << 1)
585 +#define JH7110_PADCFG_DS_12MA (3U << 1)
586 +#define JH7110_PADCFG_IE BIT(0)
587 +
588 +/*
589 + * The packed pinmux values from the device tree look like this:
590 + *
591 + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
592 + * | din | dout | doen | function | pin |
593 + */
594 +static unsigned int jh7110_pinmux_din(u32 v)
595 +{
596 + return (v & GENMASK(31, 24)) >> 24;
597 +}
598 +
599 +static u32 jh7110_pinmux_dout(u32 v)
600 +{
601 + return (v & GENMASK(23, 16)) >> 16;
602 +}
603 +
604 +static u32 jh7110_pinmux_doen(u32 v)
605 +{
606 + return (v & GENMASK(15, 10)) >> 10;
607 +}
608 +
609 +static u32 jh7110_pinmux_function(u32 v)
610 +{
611 + return (v & GENMASK(9, 8)) >> 8;
612 +}
613 +
614 +static unsigned int jh7110_pinmux_pin(u32 v)
615 +{
616 + return v & GENMASK(7, 0);
617 +}
618 +
619 +static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d)
620 +{
621 + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
622 +
623 + return container_of(gc, struct jh7110_pinctrl, gc);
624 +}
625 +
626 +struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc)
627 +{
628 + struct gpio_chip *gc = irq_desc_get_handler_data(desc);
629 +
630 + return container_of(gc, struct jh7110_pinctrl, gc);
631 +}
632 +EXPORT_SYMBOL_GPL(jh7110_from_irq_desc);
633 +
634 +#ifdef CONFIG_DEBUG_FS
635 +static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev,
636 + struct seq_file *s, unsigned int pin)
637 +{
638 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
639 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
640 +
641 + seq_printf(s, "%s", dev_name(pctldev->dev));
642 +
643 + if (pin < sfp->gc.ngpio) {
644 + unsigned int offset = 4 * (pin / 4);
645 + unsigned int shift = 8 * (pin % 4);
646 + u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
647 + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
648 + u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);
649 +
650 + dout = (dout >> shift) & info->dout_mask;
651 + doen = (doen >> shift) & info->doen_mask;
652 + gpi = ((gpi >> shift) - 2) & info->gpi_mask;
653 +
654 + seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi);
655 + }
656 +}
657 +#else
658 +#define jh7110_pin_dbg_show NULL
659 +#endif
660 +
661 +static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
662 + struct device_node *np,
663 + struct pinctrl_map **maps,
664 + unsigned int *num_maps)
665 +{
666 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
667 + struct device *dev = sfp->gc.parent;
668 + struct device_node *child;
669 + struct pinctrl_map *map;
670 + const char **pgnames;
671 + const char *grpname;
672 + int ngroups;
673 + int nmaps;
674 + int ret;
675 +
676 + ngroups = 0;
677 + for_each_child_of_node(np, child)
678 + ngroups += 1;
679 + nmaps = 2 * ngroups;
680 +
681 + pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
682 + if (!pgnames)
683 + return -ENOMEM;
684 +
685 + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
686 + if (!map)
687 + return -ENOMEM;
688 +
689 + nmaps = 0;
690 + ngroups = 0;
691 + mutex_lock(&sfp->mutex);
692 + for_each_child_of_node(np, child) {
693 + int npins = of_property_count_u32_elems(child, "pinmux");
694 + int *pins;
695 + u32 *pinmux;
696 + int i;
697 +
698 + if (npins < 1) {
699 + dev_err(dev,
700 + "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
701 + np, child);
702 + ret = -EINVAL;
703 + goto put_child;
704 + }
705 +
706 + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
707 + if (!grpname) {
708 + ret = -ENOMEM;
709 + goto put_child;
710 + }
711 +
712 + pgnames[ngroups++] = grpname;
713 +
714 + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
715 + if (!pins) {
716 + ret = -ENOMEM;
717 + goto put_child;
718 + }
719 +
720 + pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
721 + if (!pinmux) {
722 + ret = -ENOMEM;
723 + goto put_child;
724 + }
725 +
726 + ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
727 + if (ret)
728 + goto put_child;
729 +
730 + for (i = 0; i < npins; i++)
731 + pins[i] = jh7110_pinmux_pin(pinmux[i]);
732 +
733 + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
734 + map[nmaps].data.mux.function = np->name;
735 + map[nmaps].data.mux.group = grpname;
736 + nmaps += 1;
737 +
738 + ret = pinctrl_generic_add_group(pctldev, grpname,
739 + pins, npins, pinmux);
740 + if (ret < 0) {
741 + dev_err(dev, "error adding group %s: %d\n", grpname, ret);
742 + goto put_child;
743 + }
744 +
745 + ret = pinconf_generic_parse_dt_config(child, pctldev,
746 + &map[nmaps].data.configs.configs,
747 + &map[nmaps].data.configs.num_configs);
748 + if (ret) {
749 + dev_err(dev, "error parsing pin config of group %s: %d\n",
750 + grpname, ret);
751 + goto put_child;
752 + }
753 +
754 + /* don't create a map if there are no pinconf settings */
755 + if (map[nmaps].data.configs.num_configs == 0)
756 + continue;
757 +
758 + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
759 + map[nmaps].data.configs.group_or_pin = grpname;
760 + nmaps += 1;
761 + }
762 +
763 + ret = pinmux_generic_add_function(pctldev, np->name,
764 + pgnames, ngroups, NULL);
765 + if (ret < 0) {
766 + dev_err(dev, "error adding function %s: %d\n", np->name, ret);
767 + goto free_map;
768 + }
769 + mutex_unlock(&sfp->mutex);
770 +
771 + *maps = map;
772 + *num_maps = nmaps;
773 + return 0;
774 +
775 +put_child:
776 + of_node_put(child);
777 +free_map:
778 + pinctrl_utils_free_map(pctldev, map, nmaps);
779 + mutex_unlock(&sfp->mutex);
780 + return ret;
781 +}
782 +
783 +static const struct pinctrl_ops jh7110_pinctrl_ops = {
784 + .get_groups_count = pinctrl_generic_get_group_count,
785 + .get_group_name = pinctrl_generic_get_group_name,
786 + .get_group_pins = pinctrl_generic_get_group_pins,
787 + .pin_dbg_show = jh7110_pin_dbg_show,
788 + .dt_node_to_map = jh7110_dt_node_to_map,
789 + .dt_free_map = pinctrl_utils_free_map,
790 +};
791 +
792 +void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
793 + unsigned int din, u32 dout, u32 doen)
794 +{
795 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
796 +
797 + unsigned int offset = 4 * (pin / 4);
798 + unsigned int shift = 8 * (pin % 4);
799 + u32 dout_mask = info->dout_mask << shift;
800 + u32 done_mask = info->doen_mask << shift;
801 + u32 ival, imask;
802 + void __iomem *reg_dout;
803 + void __iomem *reg_doen;
804 + void __iomem *reg_din;
805 + unsigned long flags;
806 +
807 + reg_dout = sfp->base + info->dout_reg_base + offset;
808 + reg_doen = sfp->base + info->doen_reg_base + offset;
809 + dout <<= shift;
810 + doen <<= shift;
811 + if (din != GPI_NONE) {
812 + unsigned int ioffset = 4 * (din / 4);
813 + unsigned int ishift = 8 * (din % 4);
814 +
815 + reg_din = sfp->base + info->gpi_reg_base + ioffset;
816 + ival = (pin + 2) << ishift;
817 + imask = info->gpi_mask << ishift;
818 + } else {
819 + reg_din = NULL;
820 + }
821 +
822 + raw_spin_lock_irqsave(&sfp->lock, flags);
823 + dout |= readl_relaxed(reg_dout) & ~dout_mask;
824 + writel_relaxed(dout, reg_dout);
825 + doen |= readl_relaxed(reg_doen) & ~done_mask;
826 + writel_relaxed(doen, reg_doen);
827 + if (reg_din) {
828 + ival |= readl_relaxed(reg_din) & ~imask;
829 + writel_relaxed(ival, reg_din);
830 + }
831 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
832 +}
833 +EXPORT_SYMBOL_GPL(jh7110_set_gpiomux);
834 +
835 +static int jh7110_set_mux(struct pinctrl_dev *pctldev,
836 + unsigned int fsel, unsigned int gsel)
837 +{
838 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
839 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
840 + const struct group_desc *group;
841 + const u32 *pinmux;
842 + unsigned int i;
843 +
844 + group = pinctrl_generic_get_group(pctldev, gsel);
845 + if (!group)
846 + return -EINVAL;
847 +
848 + pinmux = group->data;
849 + for (i = 0; i < group->num_pins; i++) {
850 + u32 v = pinmux[i];
851 +
852 + if (info->jh7110_set_one_pin_mux)
853 + info->jh7110_set_one_pin_mux(sfp,
854 + jh7110_pinmux_pin(v),
855 + jh7110_pinmux_din(v),
856 + jh7110_pinmux_dout(v),
857 + jh7110_pinmux_doen(v),
858 + jh7110_pinmux_function(v));
859 + }
860 +
861 + return 0;
862 +}
863 +
864 +static const struct pinmux_ops jh7110_pinmux_ops = {
865 + .get_functions_count = pinmux_generic_get_function_count,
866 + .get_function_name = pinmux_generic_get_function_name,
867 + .get_function_groups = pinmux_generic_get_function_groups,
868 + .set_mux = jh7110_set_mux,
869 + .strict = true,
870 +};
871 +
872 +static const u8 jh7110_drive_strength_mA[4] = { 2, 4, 8, 12 };
873 +
874 +static u32 jh7110_padcfg_ds_to_mA(u32 padcfg)
875 +{
876 + return jh7110_drive_strength_mA[(padcfg >> 1) & 3U];
877 +}
878 +
879 +static u32 jh7110_padcfg_ds_from_mA(u32 v)
880 +{
881 + int i;
882 +
883 + for (i = 0; i < 3; i++) {
884 + if (v <= jh7110_drive_strength_mA[i])
885 + break;
886 + }
887 + return i << 1;
888 +}
889 +
890 +static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp,
891 + unsigned int pin, u32 mask, u32 value)
892 +{
893 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
894 + void __iomem *reg;
895 + unsigned long flags;
896 + int padcfg_base;
897 +
898 + if (!info->jh7110_get_padcfg_base)
899 + return;
900 +
901 + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
902 + if (padcfg_base < 0)
903 + return;
904 +
905 + reg = sfp->base + padcfg_base + 4 * pin;
906 + value &= mask;
907 +
908 + raw_spin_lock_irqsave(&sfp->lock, flags);
909 + value |= readl_relaxed(reg) & ~mask;
910 + writel_relaxed(value, reg);
911 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
912 +}
913 +
914 +static int jh7110_pinconf_get(struct pinctrl_dev *pctldev,
915 + unsigned int pin, unsigned long *config)
916 +{
917 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
918 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
919 + int param = pinconf_to_config_param(*config);
920 + u32 padcfg, arg;
921 + bool enabled;
922 + int padcfg_base;
923 +
924 + if (!info->jh7110_get_padcfg_base)
925 + return 0;
926 +
927 + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
928 + if (padcfg_base < 0)
929 + return 0;
930 +
931 + padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
932 + switch (param) {
933 + case PIN_CONFIG_BIAS_DISABLE:
934 + enabled = !(padcfg & JH7110_PADCFG_BIAS);
935 + arg = 0;
936 + break;
937 + case PIN_CONFIG_BIAS_PULL_DOWN:
938 + enabled = padcfg & JH7110_PADCFG_PD;
939 + arg = 1;
940 + break;
941 + case PIN_CONFIG_BIAS_PULL_UP:
942 + enabled = padcfg & JH7110_PADCFG_PU;
943 + arg = 1;
944 + break;
945 + case PIN_CONFIG_DRIVE_STRENGTH:
946 + enabled = true;
947 + arg = jh7110_padcfg_ds_to_mA(padcfg);
948 + break;
949 + case PIN_CONFIG_INPUT_ENABLE:
950 + enabled = padcfg & JH7110_PADCFG_IE;
951 + arg = enabled;
952 + break;
953 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
954 + enabled = padcfg & JH7110_PADCFG_SMT;
955 + arg = enabled;
956 + break;
957 + case PIN_CONFIG_SLEW_RATE:
958 + enabled = true;
959 + arg = !!(padcfg & JH7110_PADCFG_SLEW);
960 + break;
961 + default:
962 + return -ENOTSUPP;
963 + }
964 +
965 + *config = pinconf_to_config_packed(param, arg);
966 + return enabled ? 0 : -EINVAL;
967 +}
968 +
969 +static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev,
970 + unsigned int gsel,
971 + unsigned long *config)
972 +{
973 + const struct group_desc *group;
974 +
975 + group = pinctrl_generic_get_group(pctldev, gsel);
976 + if (!group)
977 + return -EINVAL;
978 +
979 + return jh7110_pinconf_get(pctldev, group->pins[0], config);
980 +}
981 +
982 +static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,
983 + unsigned int gsel,
984 + unsigned long *configs,
985 + unsigned int num_configs)
986 +{
987 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
988 + const struct group_desc *group;
989 + u16 mask, value;
990 + int i;
991 +
992 + group = pinctrl_generic_get_group(pctldev, gsel);
993 + if (!group)
994 + return -EINVAL;
995 +
996 + mask = 0;
997 + value = 0;
998 + for (i = 0; i < num_configs; i++) {
999 + int param = pinconf_to_config_param(configs[i]);
1000 + u32 arg = pinconf_to_config_argument(configs[i]);
1001 +
1002 + switch (param) {
1003 + case PIN_CONFIG_BIAS_DISABLE:
1004 + mask |= JH7110_PADCFG_BIAS;
1005 + value &= ~JH7110_PADCFG_BIAS;
1006 + break;
1007 + case PIN_CONFIG_BIAS_PULL_DOWN:
1008 + if (arg == 0)
1009 + return -ENOTSUPP;
1010 + mask |= JH7110_PADCFG_BIAS;
1011 + value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PD;
1012 + break;
1013 + case PIN_CONFIG_BIAS_PULL_UP:
1014 + if (arg == 0)
1015 + return -ENOTSUPP;
1016 + mask |= JH7110_PADCFG_BIAS;
1017 + value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PU;
1018 + break;
1019 + case PIN_CONFIG_DRIVE_STRENGTH:
1020 + mask |= JH7110_PADCFG_DS_MASK;
1021 + value = (value & ~JH7110_PADCFG_DS_MASK) |
1022 + jh7110_padcfg_ds_from_mA(arg);
1023 + break;
1024 + case PIN_CONFIG_INPUT_ENABLE:
1025 + mask |= JH7110_PADCFG_IE;
1026 + if (arg)
1027 + value |= JH7110_PADCFG_IE;
1028 + else
1029 + value &= ~JH7110_PADCFG_IE;
1030 + break;
1031 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1032 + mask |= JH7110_PADCFG_SMT;
1033 + if (arg)
1034 + value |= JH7110_PADCFG_SMT;
1035 + else
1036 + value &= ~JH7110_PADCFG_SMT;
1037 + break;
1038 + case PIN_CONFIG_SLEW_RATE:
1039 + mask |= JH7110_PADCFG_SLEW;
1040 + if (arg)
1041 + value |= JH7110_PADCFG_SLEW;
1042 + else
1043 + value &= ~JH7110_PADCFG_SLEW;
1044 + break;
1045 + default:
1046 + return -ENOTSUPP;
1047 + }
1048 + }
1049 +
1050 + for (i = 0; i < group->num_pins; i++)
1051 + jh7110_padcfg_rmw(sfp, group->pins[i], mask, value);
1052 +
1053 + return 0;
1054 +}
1055 +
1056 +#ifdef CONFIG_DEBUG_FS
1057 +static void jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1058 + struct seq_file *s, unsigned int pin)
1059 +{
1060 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
1061 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1062 + u32 value;
1063 + int padcfg_base;
1064 +
1065 + if (!info->jh7110_get_padcfg_base)
1066 + return;
1067 +
1068 + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
1069 + if (padcfg_base < 0)
1070 + return;
1071 +
1072 + value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
1073 + seq_printf(s, " (0x%02x)", value);
1074 +}
1075 +#else
1076 +#define jh7110_pinconf_dbg_show NULL
1077 +#endif
1078 +
1079 +static const struct pinconf_ops jh7110_pinconf_ops = {
1080 + .pin_config_get = jh7110_pinconf_get,
1081 + .pin_config_group_get = jh7110_pinconf_group_get,
1082 + .pin_config_group_set = jh7110_pinconf_group_set,
1083 + .pin_config_dbg_show = jh7110_pinconf_dbg_show,
1084 + .is_generic = true,
1085 +};
1086 +
1087 +static int jh7110_gpio_request(struct gpio_chip *gc, unsigned int gpio)
1088 +{
1089 + return pinctrl_gpio_request(gc->base + gpio);
1090 +}
1091 +
1092 +static void jh7110_gpio_free(struct gpio_chip *gc, unsigned int gpio)
1093 +{
1094 + pinctrl_gpio_free(gc->base + gpio);
1095 +}
1096 +
1097 +static int jh7110_gpio_get_direction(struct gpio_chip *gc,
1098 + unsigned int gpio)
1099 +{
1100 + struct jh7110_pinctrl *sfp = container_of(gc,
1101 + struct jh7110_pinctrl, gc);
1102 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1103 + unsigned int offset = 4 * (gpio / 4);
1104 + unsigned int shift = 8 * (gpio % 4);
1105 + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
1106 +
1107 + doen = (doen >> shift) & info->doen_mask;
1108 +
1109 + return doen == GPOEN_ENABLE ?
1110 + GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1111 +}
1112 +
1113 +static int jh7110_gpio_direction_input(struct gpio_chip *gc,
1114 + unsigned int gpio)
1115 +{
1116 + struct jh7110_pinctrl *sfp = container_of(gc,
1117 + struct jh7110_pinctrl, gc);
1118 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1119 +
1120 + /* enable input and schmitt trigger */
1121 + jh7110_padcfg_rmw(sfp, gpio,
1122 + JH7110_PADCFG_IE | JH7110_PADCFG_SMT,
1123 + JH7110_PADCFG_IE | JH7110_PADCFG_SMT);
1124 +
1125 + if (info->jh7110_set_one_pin_mux)
1126 + info->jh7110_set_one_pin_mux(sfp, gpio,
1127 + GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
1128 +
1129 + return 0;
1130 +}
1131 +
1132 +static int jh7110_gpio_direction_output(struct gpio_chip *gc,
1133 + unsigned int gpio, int value)
1134 +{
1135 + struct jh7110_pinctrl *sfp = container_of(gc,
1136 + struct jh7110_pinctrl, gc);
1137 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1138 +
1139 + if (info->jh7110_set_one_pin_mux)
1140 + info->jh7110_set_one_pin_mux(sfp, gpio,
1141 + GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW,
1142 + GPOEN_ENABLE, 0);
1143 +
1144 + /* disable input, schmitt trigger and bias */
1145 + jh7110_padcfg_rmw(sfp, gpio,
1146 + JH7110_PADCFG_IE | JH7110_PADCFG_SMT |
1147 + JH7110_PADCFG_BIAS, 0);
1148 + return 0;
1149 +}
1150 +
1151 +static int jh7110_gpio_get(struct gpio_chip *gc, unsigned int gpio)
1152 +{
1153 + struct jh7110_pinctrl *sfp = container_of(gc,
1154 + struct jh7110_pinctrl, gc);
1155 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1156 + void __iomem *reg = sfp->base + info->gpioin_reg_base
1157 + + 4 * (gpio / 32);
1158 +
1159 + return !!(readl_relaxed(reg) & BIT(gpio % 32));
1160 +}
1161 +
1162 +static void jh7110_gpio_set(struct gpio_chip *gc,
1163 + unsigned int gpio, int value)
1164 +{
1165 + struct jh7110_pinctrl *sfp = container_of(gc,
1166 + struct jh7110_pinctrl, gc);
1167 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1168 + unsigned int offset = 4 * (gpio / 4);
1169 + unsigned int shift = 8 * (gpio % 4);
1170 + void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;
1171 + u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift;
1172 + u32 mask = info->dout_mask << shift;
1173 + unsigned long flags;
1174 +
1175 + raw_spin_lock_irqsave(&sfp->lock, flags);
1176 + dout |= readl_relaxed(reg_dout) & ~mask;
1177 + writel_relaxed(dout, reg_dout);
1178 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1179 +}
1180 +
1181 +static int jh7110_gpio_set_config(struct gpio_chip *gc,
1182 + unsigned int gpio, unsigned long config)
1183 +{
1184 + struct jh7110_pinctrl *sfp = container_of(gc,
1185 + struct jh7110_pinctrl, gc);
1186 + u32 arg = pinconf_to_config_argument(config);
1187 + u32 value;
1188 + u32 mask;
1189 +
1190 + switch (pinconf_to_config_param(config)) {
1191 + case PIN_CONFIG_BIAS_DISABLE:
1192 + mask = JH7110_PADCFG_BIAS;
1193 + value = 0;
1194 + break;
1195 + case PIN_CONFIG_BIAS_PULL_DOWN:
1196 + if (arg == 0)
1197 + return -ENOTSUPP;
1198 + mask = JH7110_PADCFG_BIAS;
1199 + value = JH7110_PADCFG_PD;
1200 + break;
1201 + case PIN_CONFIG_BIAS_PULL_UP:
1202 + if (arg == 0)
1203 + return -ENOTSUPP;
1204 + mask = JH7110_PADCFG_BIAS;
1205 + value = JH7110_PADCFG_PU;
1206 + break;
1207 + case PIN_CONFIG_DRIVE_PUSH_PULL:
1208 + return 0;
1209 + case PIN_CONFIG_INPUT_ENABLE:
1210 + mask = JH7110_PADCFG_IE;
1211 + value = arg ? JH7110_PADCFG_IE : 0;
1212 + break;
1213 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1214 + mask = JH7110_PADCFG_SMT;
1215 + value = arg ? JH7110_PADCFG_SMT : 0;
1216 + break;
1217 + default:
1218 + return -ENOTSUPP;
1219 + }
1220 +
1221 + jh7110_padcfg_rmw(sfp, gpio, mask, value);
1222 + return 0;
1223 +}
1224 +
1225 +static int jh7110_gpio_add_pin_ranges(struct gpio_chip *gc)
1226 +{
1227 + struct jh7110_pinctrl *sfp = container_of(gc,
1228 + struct jh7110_pinctrl, gc);
1229 +
1230 + sfp->gpios.name = sfp->gc.label;
1231 + sfp->gpios.base = sfp->gc.base;
1232 + sfp->gpios.pin_base = 0;
1233 + sfp->gpios.npins = sfp->gc.ngpio;
1234 + sfp->gpios.gc = &sfp->gc;
1235 + pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
1236 + return 0;
1237 +}
1238 +
1239 +static void jh7110_irq_ack(struct irq_data *d)
1240 +{
1241 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1242 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1243 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1244 + void __iomem *ic = sfp->base + irq_reg->ic_reg_base
1245 + + 4 * (gpio / 32);
1246 + u32 mask = BIT(gpio % 32);
1247 + unsigned long flags;
1248 + u32 value;
1249 +
1250 + raw_spin_lock_irqsave(&sfp->lock, flags);
1251 + value = readl_relaxed(ic) & ~mask;
1252 + writel_relaxed(value, ic);
1253 + writel_relaxed(value | mask, ic);
1254 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1255 +}
1256 +
1257 +static void jh7110_irq_mask(struct irq_data *d)
1258 +{
1259 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1260 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1261 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1262 + void __iomem *ie = sfp->base + irq_reg->ie_reg_base
1263 + + 4 * (gpio / 32);
1264 + u32 mask = BIT(gpio % 32);
1265 + unsigned long flags;
1266 + u32 value;
1267 +
1268 + raw_spin_lock_irqsave(&sfp->lock, flags);
1269 + value = readl_relaxed(ie) & ~mask;
1270 + writel_relaxed(value, ie);
1271 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1272 +
1273 + gpiochip_disable_irq(&sfp->gc, d->hwirq);
1274 +}
1275 +
1276 +static void jh7110_irq_mask_ack(struct irq_data *d)
1277 +{
1278 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1279 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1280 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1281 + void __iomem *ie = sfp->base + irq_reg->ie_reg_base
1282 + + 4 * (gpio / 32);
1283 + void __iomem *ic = sfp->base + irq_reg->ic_reg_base
1284 + + 4 * (gpio / 32);
1285 + u32 mask = BIT(gpio % 32);
1286 + unsigned long flags;
1287 + u32 value;
1288 +
1289 + raw_spin_lock_irqsave(&sfp->lock, flags);
1290 + value = readl_relaxed(ie) & ~mask;
1291 + writel_relaxed(value, ie);
1292 +
1293 + value = readl_relaxed(ic) & ~mask;
1294 + writel_relaxed(value, ic);
1295 + writel_relaxed(value | mask, ic);
1296 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1297 +}
1298 +
1299 +static void jh7110_irq_unmask(struct irq_data *d)
1300 +{
1301 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1302 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1303 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1304 + void __iomem *ie = sfp->base + irq_reg->ie_reg_base
1305 + + 4 * (gpio / 32);
1306 + u32 mask = BIT(gpio % 32);
1307 + unsigned long flags;
1308 + u32 value;
1309 +
1310 + gpiochip_enable_irq(&sfp->gc, d->hwirq);
1311 +
1312 + raw_spin_lock_irqsave(&sfp->lock, flags);
1313 + value = readl_relaxed(ie) | mask;
1314 + writel_relaxed(value, ie);
1315 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1316 +}
1317 +
1318 +static int jh7110_irq_set_type(struct irq_data *d, unsigned int trigger)
1319 +{
1320 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1321 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1322 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1323 + void __iomem *base = sfp->base + 4 * (gpio / 32);
1324 + u32 mask = BIT(gpio % 32);
1325 + u32 irq_type, edge_both, polarity;
1326 + unsigned long flags;
1327 +
1328 + switch (trigger) {
1329 + case IRQ_TYPE_EDGE_RISING:
1330 + irq_type = mask; /* 1: edge triggered */
1331 + edge_both = 0; /* 0: single edge */
1332 + polarity = mask; /* 1: rising edge */
1333 + break;
1334 + case IRQ_TYPE_EDGE_FALLING:
1335 + irq_type = mask; /* 1: edge triggered */
1336 + edge_both = 0; /* 0: single edge */
1337 + polarity = 0; /* 0: falling edge */
1338 + break;
1339 + case IRQ_TYPE_EDGE_BOTH:
1340 + irq_type = mask; /* 1: edge triggered */
1341 + edge_both = mask; /* 1: both edges */
1342 + polarity = 0; /* 0: ignored */
1343 + break;
1344 + case IRQ_TYPE_LEVEL_HIGH:
1345 + irq_type = 0; /* 0: level triggered */
1346 + edge_both = 0; /* 0: ignored */
1347 + polarity = mask; /* 1: high level */
1348 + break;
1349 + case IRQ_TYPE_LEVEL_LOW:
1350 + irq_type = 0; /* 0: level triggered */
1351 + edge_both = 0; /* 0: ignored */
1352 + polarity = 0; /* 0: low level */
1353 + break;
1354 + default:
1355 + return -EINVAL;
1356 + }
1357 +
1358 + if (trigger & IRQ_TYPE_EDGE_BOTH)
1359 + irq_set_handler_locked(d, handle_edge_irq);
1360 + else
1361 + irq_set_handler_locked(d, handle_level_irq);
1362 +
1363 + raw_spin_lock_irqsave(&sfp->lock, flags);
1364 + irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask;
1365 + writel_relaxed(irq_type, base + irq_reg->is_reg_base);
1366 +
1367 + edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask;
1368 + writel_relaxed(edge_both, base + irq_reg->ibe_reg_base);
1369 +
1370 + polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask;
1371 + writel_relaxed(polarity, base + irq_reg->iev_reg_base);
1372 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1373 + return 0;
1374 +}
1375 +
1376 +static struct irq_chip jh7110_irq_chip = {
1377 + .irq_ack = jh7110_irq_ack,
1378 + .irq_mask = jh7110_irq_mask,
1379 + .irq_mask_ack = jh7110_irq_mask_ack,
1380 + .irq_unmask = jh7110_irq_unmask,
1381 + .irq_set_type = jh7110_irq_set_type,
1382 + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
1383 + GPIOCHIP_IRQ_RESOURCE_HELPERS,
1384 +};
1385 +
1386 +static void jh7110_disable_clock(void *data)
1387 +{
1388 + clk_disable_unprepare(data);
1389 +}
1390 +
1391 +int jh7110_pinctrl_probe(struct platform_device *pdev)
1392 +{
1393 + struct device *dev = &pdev->dev;
1394 + const struct jh7110_pinctrl_soc_info *info;
1395 + struct jh7110_pinctrl *sfp;
1396 + struct pinctrl_desc *jh7110_pinctrl_desc;
1397 + struct reset_control *rst;
1398 + struct clk *clk;
1399 + int ret;
1400 +
1401 + info = of_device_get_match_data(&pdev->dev);
1402 + if (!info)
1403 + return -ENODEV;
1404 +
1405 + if (!info->pins || !info->npins) {
1406 + dev_err(dev, "wrong pinctrl info\n");
1407 + return -EINVAL;
1408 + }
1409 +
1410 + sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
1411 + if (!sfp)
1412 + return -ENOMEM;
1413 +
1414 + sfp->base = devm_platform_ioremap_resource(pdev, 0);
1415 + if (IS_ERR(sfp->base))
1416 + return PTR_ERR(sfp->base);
1417 +
1418 + clk = devm_clk_get_optional(dev, NULL);
1419 + if (IS_ERR(clk))
1420 + return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
1421 +
1422 + rst = devm_reset_control_get_exclusive(dev, NULL);
1423 + if (IS_ERR(rst))
1424 + return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
1425 +
1426 + /*
1427 + * we don't want to assert reset and risk undoing pin muxing for the
1428 + * early boot serial console, but let's make sure the reset line is
1429 + * deasserted in case someone runs a really minimal bootloader.
1430 + */
1431 + ret = reset_control_deassert(rst);
1432 + if (ret)
1433 + return dev_err_probe(dev, ret, "could not deassert reset\n");
1434 +
1435 + if (clk) {
1436 + ret = clk_prepare_enable(clk);
1437 + if (ret)
1438 + return dev_err_probe(dev, ret, "could not enable clock\n");
1439 +
1440 + ret = devm_add_action_or_reset(dev, jh7110_disable_clock, clk);
1441 + if (ret)
1442 + return ret;
1443 + }
1444 +
1445 + jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev,
1446 + sizeof(*jh7110_pinctrl_desc),
1447 + GFP_KERNEL);
1448 + if (!jh7110_pinctrl_desc)
1449 + return -ENOMEM;
1450 +
1451 + jh7110_pinctrl_desc->name = dev_name(dev);
1452 + jh7110_pinctrl_desc->pins = info->pins;
1453 + jh7110_pinctrl_desc->npins = info->npins;
1454 + jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops;
1455 + jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops;
1456 + jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops;
1457 + jh7110_pinctrl_desc->owner = THIS_MODULE;
1458 +
1459 + sfp->info = info;
1460 + sfp->dev = dev;
1461 + platform_set_drvdata(pdev, sfp);
1462 + sfp->gc.parent = dev;
1463 + raw_spin_lock_init(&sfp->lock);
1464 + mutex_init(&sfp->mutex);
1465 +
1466 + ret = devm_pinctrl_register_and_init(dev,
1467 + jh7110_pinctrl_desc,
1468 + sfp, &sfp->pctl);
1469 + if (ret)
1470 + return dev_err_probe(dev, ret,
1471 + "could not register pinctrl driver\n");
1472 +
1473 + sfp->gc.label = dev_name(dev);
1474 + sfp->gc.owner = THIS_MODULE;
1475 + sfp->gc.request = jh7110_gpio_request;
1476 + sfp->gc.free = jh7110_gpio_free;
1477 + sfp->gc.get_direction = jh7110_gpio_get_direction;
1478 + sfp->gc.direction_input = jh7110_gpio_direction_input;
1479 + sfp->gc.direction_output = jh7110_gpio_direction_output;
1480 + sfp->gc.get = jh7110_gpio_get;
1481 + sfp->gc.set = jh7110_gpio_set;
1482 + sfp->gc.set_config = jh7110_gpio_set_config;
1483 + sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
1484 + sfp->gc.base = info->gc_base;
1485 + sfp->gc.ngpio = info->ngpios;
1486 +
1487 + jh7110_irq_chip.name = sfp->gc.label;
1488 + gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip);
1489 + sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler;
1490 + sfp->gc.irq.num_parents = 1;
1491 + sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
1492 + sizeof(*sfp->gc.irq.parents),
1493 + GFP_KERNEL);
1494 + if (!sfp->gc.irq.parents)
1495 + return -ENOMEM;
1496 + sfp->gc.irq.default_type = IRQ_TYPE_NONE;
1497 + sfp->gc.irq.handler = handle_bad_irq;
1498 + sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw;
1499 +
1500 + ret = platform_get_irq(pdev, 0);
1501 + if (ret < 0)
1502 + return ret;
1503 + sfp->gc.irq.parents[0] = ret;
1504 +
1505 + ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
1506 + if (ret)
1507 + return dev_err_probe(dev, ret, "could not register gpiochip\n");
1508 +
1509 + irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
1510 +
1511 + dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);
1512 +
1513 + return pinctrl_enable(sfp->pctl);
1514 +}
1515 +EXPORT_SYMBOL_GPL(jh7110_pinctrl_probe);
1516 +
1517 +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC");
1518 +MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1519 +MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
1520 +MODULE_LICENSE("GPL");
1521 diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h
1522 new file mode 100644
1523 index 000000000000..3f20b7ff96dd
1524 --- /dev/null
1525 +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h
1526 @@ -0,0 +1,70 @@
1527 +/* SPDX-License-Identifier: GPL-2.0 */
1528 +/*
1529 + * Pinctrl / GPIO driver for StarFive JH7110 SoC
1530 + *
1531 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
1532 + */
1533 +
1534 +#ifndef __PINCTRL_STARFIVE_JH7110_H__
1535 +#define __PINCTRL_STARFIVE_JH7110_H__
1536 +
1537 +#include <linux/pinctrl/pinconf-generic.h>
1538 +#include <linux/pinctrl/pinmux.h>
1539 +
1540 +struct jh7110_pinctrl {
1541 + struct device *dev;
1542 + struct gpio_chip gc;
1543 + struct pinctrl_gpio_range gpios;
1544 + raw_spinlock_t lock;
1545 + void __iomem *base;
1546 + struct pinctrl_dev *pctl;
1547 + /* register read/write mutex */
1548 + struct mutex mutex;
1549 + const struct jh7110_pinctrl_soc_info *info;
1550 +};
1551 +
1552 +struct jh7110_gpio_irq_reg {
1553 + unsigned int is_reg_base;
1554 + unsigned int ic_reg_base;
1555 + unsigned int ibe_reg_base;
1556 + unsigned int iev_reg_base;
1557 + unsigned int ie_reg_base;
1558 + unsigned int ris_reg_base;
1559 + unsigned int mis_reg_base;
1560 +};
1561 +
1562 +struct jh7110_pinctrl_soc_info {
1563 + const struct pinctrl_pin_desc *pins;
1564 + unsigned int npins;
1565 + unsigned int ngpios;
1566 + unsigned int gc_base;
1567 +
1568 + /* gpio dout/doen/din/gpioinput register */
1569 + unsigned int dout_reg_base;
1570 + unsigned int dout_mask;
1571 + unsigned int doen_reg_base;
1572 + unsigned int doen_mask;
1573 + unsigned int gpi_reg_base;
1574 + unsigned int gpi_mask;
1575 + unsigned int gpioin_reg_base;
1576 +
1577 + const struct jh7110_gpio_irq_reg *irq_reg;
1578 +
1579 + /* generic pinmux */
1580 + int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp,
1581 + unsigned int pin,
1582 + unsigned int din, u32 dout,
1583 + u32 doen, u32 func);
1584 + /* gpio chip */
1585 + int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp,
1586 + unsigned int pin);
1587 + void (*jh7110_gpio_irq_handler)(struct irq_desc *desc);
1588 + int (*jh7110_gpio_init_hw)(struct gpio_chip *gc);
1589 +};
1590 +
1591 +void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
1592 + unsigned int din, u32 dout, u32 doen);
1593 +int jh7110_pinctrl_probe(struct platform_device *pdev);
1594 +struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc);
1595 +
1596 +#endif /* __PINCTRL_STARFIVE_JH7110_H__ */
1597 --
1598 2.20.1
1599
Staging tree of Zoltan Herpai