target/linux/jh71x0/patches-6.1/0010-reset-starfive-Extract-the-common-JH71X0-reset-code.patch

   1 From dbee38aac9811a25e3e3204f813048bf64155248 Mon Sep 17 00:00:00 2001
   2 From: Emil Renner Berthing <kernel@esmil.dk>
   3 Date: Sat, 1 Apr 2023 19:19:22 +0800
   4 Subject: [PATCH 010/122] reset: starfive: Extract the common JH71X0 reset code
   5
   6 Extract the common JH71X0 reset code for reusing them to
   7 support JH7110 SoC.
   8
   9 Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
  10 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
  11 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
  12 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
  13 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
  14 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
  15 ---
  16  .../reset/starfive/reset-starfive-jh7100.c    | 49 ++++++++++++
  17  .../reset/starfive/reset-starfive-jh71x0.c    | 76 ++++++-------------
  18  .../reset/starfive/reset-starfive-jh71x0.h    |  5 +-
  19  3 files changed, 76 insertions(+), 54 deletions(-)
  20
  21 diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
  22 index 5a68327c1f6a..9d7cb4ed8869 100644
  23 --- a/drivers/reset/starfive/reset-starfive-jh7100.c
  24 +++ b/drivers/reset/starfive/reset-starfive-jh7100.c
  25 @@ -10,6 +10,55 @@
  26
  27  #include "reset-starfive-jh71x0.h"
  28
  29 +#include <dt-bindings/reset/starfive-jh7100.h>
  30 +
  31 +/* register offsets */
  32 +#define JH7100_RESET_ASSERT0   0x00
  33 +#define JH7100_RESET_ASSERT1   0x04
  34 +#define JH7100_RESET_ASSERT2   0x08
  35 +#define JH7100_RESET_ASSERT3   0x0c
  36 +#define JH7100_RESET_STATUS0   0x10
  37 +#define JH7100_RESET_STATUS1   0x14
  38 +#define JH7100_RESET_STATUS2   0x18
  39 +#define JH7100_RESET_STATUS3   0x1c
  40 +
  41 +/*
  42 + * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
  43 + * line 32m + n, and writing a 0 deasserts the same line.
  44 + * Most reset lines have their status inverted so a 0 bit in the STATUS
  45 + * register means the line is asserted and a 1 means it's deasserted. A few
  46 + * lines don't though, so store the expected value of the status registers when
  47 + * all lines are asserted.
  48 + */
  49 +static const u64 jh7100_reset_asserted[2] = {
  50 +       /* STATUS0 */
  51 +       BIT_ULL_MASK(JH7100_RST_U74) |
  52 +       BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
  53 +       BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
  54 +       /* STATUS1 */
  55 +       BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
  56 +       BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
  57 +       /* STATUS2 */
  58 +       BIT_ULL_MASK(JH7100_RST_E24) |
  59 +       /* STATUS3 */
  60 +       0,
  61 +};
  62 +
  63 +static int __init jh7100_reset_probe(struct platform_device *pdev)
  64 +{
  65 +       void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
  66 +
  67 +       if (IS_ERR(base))
  68 +               return PTR_ERR(base);
  69 +
  70 +       return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
  71 +                                             base + JH7100_RESET_ASSERT0,
  72 +                                             base + JH7100_RESET_STATUS0,
  73 +                                             jh7100_reset_asserted,
  74 +                                             JH7100_RSTN_END,
  75 +                                             THIS_MODULE);
  76 +}
  77 +
  78  static const struct of_device_id jh7100_reset_dt_ids[] = {
  79         { .compatible = "starfive,jh7100-reset" },
  80         { /* sentinel */ }
  81 diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
  82 index 114a13c4b8a6..3577444a89c6 100644
  83 --- a/drivers/reset/starfive/reset-starfive-jh71x0.c
  84 +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
  85 @@ -10,51 +10,18 @@
  86  #include <linux/io.h>
  87  #include <linux/io-64-nonatomic-lo-hi.h>
  88  #include <linux/iopoll.h>
  89 -#include <linux/platform_device.h>
  90  #include <linux/reset-controller.h>
  91  #include <linux/spinlock.h>
  92
  93  #include "reset-starfive-jh71x0.h"
  94
  95 -#include <dt-bindings/reset/starfive-jh7100.h>
  96 -
  97 -/* register offsets */
  98 -#define JH7100_RESET_ASSERT0   0x00
  99 -#define JH7100_RESET_ASSERT1   0x04
 100 -#define JH7100_RESET_ASSERT2   0x08
 101 -#define JH7100_RESET_ASSERT3   0x0c
 102 -#define JH7100_RESET_STATUS0   0x10
 103 -#define JH7100_RESET_STATUS1   0x14
 104 -#define JH7100_RESET_STATUS2   0x18
 105 -#define JH7100_RESET_STATUS3   0x1c
 106 -
 107 -/*
 108 - * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
 109 - * line 32m + n, and writing a 0 deasserts the same line.
 110 - * Most reset lines have their status inverted so a 0 bit in the STATUS
 111 - * register means the line is asserted and a 1 means it's deasserted. A few
 112 - * lines don't though, so store the expected value of the status registers when
 113 - * all lines are asserted.
 114 - */
 115 -static const u64 jh7100_reset_asserted[2] = {
 116 -       /* STATUS0 */
 117 -       BIT_ULL_MASK(JH7100_RST_U74) |
 118 -       BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
 119 -       BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
 120 -       /* STATUS1 */
 121 -       BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
 122 -       BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
 123 -       /* STATUS2 */
 124 -       BIT_ULL_MASK(JH7100_RST_E24) |
 125 -       /* STATUS3 */
 126 -       0,
 127 -};
 128 -
 129  struct jh7100_reset {
 130         struct reset_controller_dev rcdev;
 131         /* protect registers against concurrent read-modify-write */
 132         spinlock_t lock;
 133 -       void __iomem *base;
 134 +       void __iomem *assert;
 135 +       void __iomem *status;
 136 +       const u64 *asserted;
 137  };
 138
 139  static inline struct jh7100_reset *
 140 @@ -69,9 +36,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
 141         struct jh7100_reset *data = jh7100_reset_from(rcdev);
 142         unsigned long offset = BIT_ULL_WORD(id);
 143         u64 mask = BIT_ULL_MASK(id);
 144 -       void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
 145 -       void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
 146 -       u64 done = jh7100_reset_asserted[offset] & mask;
 147 +       void __iomem *reg_assert = data->assert + offset * sizeof(u64);
 148 +       void __iomem *reg_status = data->status + offset * sizeof(u64);
 149 +       u64 done = data->asserted ? data->asserted[offset] & mask : 0;
 150         u64 value;
 151         unsigned long flags;
 152         int ret;
 153 @@ -125,10 +92,10 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
 154         struct jh7100_reset *data = jh7100_reset_from(rcdev);
 155         unsigned long offset = BIT_ULL_WORD(id);
 156         u64 mask = BIT_ULL_MASK(id);
 157 -       void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
 158 +       void __iomem *reg_status = data->status + offset * sizeof(u64);
 159         u64 value = readq(reg_status);
 160
 161 -       return !((value ^ jh7100_reset_asserted[offset]) & mask);
 162 +       return !((value ^ data->asserted[offset]) & mask);
 163  }
 164
 165  static const struct reset_control_ops jh7100_reset_ops = {
 166 @@ -138,25 +105,28 @@ static const struct reset_control_ops jh7100_reset_ops = {
 167         .status         = jh7100_reset_status,
 168  };
 169
 170 -int jh7100_reset_probe(struct platform_device *pdev)
 171 +int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
 172 +                                  void __iomem *assert, void __iomem *status,
 173 +                                  const u64 *asserted, unsigned int nr_resets,
 174 +                                  struct module *owner)
 175  {
 176         struct jh7100_reset *data;
 177
 178 -       data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 179 +       data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 180         if (!data)
 181                 return -ENOMEM;
 182
 183 -       data->base = devm_platform_ioremap_resource(pdev, 0);
 184 -       if (IS_ERR(data->base))
 185 -               return PTR_ERR(data->base);
 186 -
 187         data->rcdev.ops = &jh7100_reset_ops;
 188 -       data->rcdev.owner = THIS_MODULE;
 189 -       data->rcdev.nr_resets = JH7100_RSTN_END;
 190 -       data->rcdev.dev = &pdev->dev;
 191 -       data->rcdev.of_node = pdev->dev.of_node;
 192 +       data->rcdev.owner = owner;
 193 +       data->rcdev.nr_resets = nr_resets;
 194 +       data->rcdev.dev = dev;
 195 +       data->rcdev.of_node = of_node;
 196 +
 197         spin_lock_init(&data->lock);
 198 +       data->assert = assert;
 199 +       data->status = status;
 200 +       data->asserted = asserted;
 201
 202 -       return devm_reset_controller_register(&pdev->dev, &data->rcdev);
 203 +       return devm_reset_controller_register(dev, &data->rcdev);
 204  }
 205 -EXPORT_SYMBOL_GPL(jh7100_reset_probe);
 206 +EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
 207 diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
 208 index 318d7a0e096a..1fc5a648c8d8 100644
 209 --- a/drivers/reset/starfive/reset-starfive-jh71x0.h
 210 +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
 211 @@ -6,6 +6,9 @@
 212  #ifndef __RESET_STARFIVE_JH71X0_H
 213  #define __RESET_STARFIVE_JH71X0_H
 214
 215 -int jh7100_reset_probe(struct platform_device *pdev);
 216 +int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
 217 +                                  void __iomem *assert, void __iomem *status,
 218 +                                  const u64 *asserted, unsigned int nr_resets,
 219 +                                  struct module *owner);
 220
 221  #endif /* __RESET_STARFIVE_JH71X0_H */
 222 --
 223 2.20.1
 224