target/linux/jh71x0/patches-6.1/0002-dt-bindings-clock-Add-StarFive-JH7110-always-on-cloc.patch

   1 From cd833f484009f37be57a2aa09257af6e8c1b25b6 Mon Sep 17 00:00:00 2001
   2 From: Emil Renner Berthing <kernel@esmil.dk>
   3 Date: Sat, 1 Apr 2023 19:19:14 +0800
   4 Subject: [PATCH 002/122] dt-bindings: clock: Add StarFive JH7110 always-on
   5  clock and reset generator
   6
   7 Add bindings for the always-on clock and reset generator (AONCRG) on the
   8 JH7110 RISC-V SoC by StarFive Ltd.
   9
  10 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
  11 Reviewed-by: Rob Herring <robh@kernel.org>
  12 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
  13 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
  14 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
  15 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
  16 ---
  17  .../clock/starfive,jh7110-aoncrg.yaml         | 107 ++++++++++++++++++
  18  .../dt-bindings/clock/starfive,jh7110-crg.h   |  18 +++
  19  .../dt-bindings/reset/starfive,jh7110-crg.h   |  12 ++
  20  3 files changed, 137 insertions(+)
  21  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
  22
  23 diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
  24 new file mode 100644
  25 index 000000000000..923680a44aef
  26 --- /dev/null
  27 +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
  28 @@ -0,0 +1,107 @@
  29 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  30 +%YAML 1.2
  31 +---
  32 +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
  33 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  34 +
  35 +title: StarFive JH7110 Always-On Clock and Reset Generator
  36 +
  37 +maintainers:
  38 +  - Emil Renner Berthing <kernel@esmil.dk>
  39 +
  40 +properties:
  41 +  compatible:
  42 +    const: starfive,jh7110-aoncrg
  43 +
  44 +  reg:
  45 +    maxItems: 1
  46 +
  47 +  clocks:
  48 +    oneOf:
  49 +      - items:
  50 +          - description: Main Oscillator (24 MHz)
  51 +          - description: GMAC0 RMII reference or GMAC0 RGMII RX
  52 +          - description: STG AXI/AHB
  53 +          - description: APB Bus
  54 +          - description: GMAC0 GTX
  55 +
  56 +      - items:
  57 +          - description: Main Oscillator (24 MHz)
  58 +          - description: GMAC0 RMII reference or GMAC0 RGMII RX
  59 +          - description: STG AXI/AHB or GMAC0 RGMII RX
  60 +          - description: APB Bus or STG AXI/AHB
  61 +          - description: GMAC0 GTX or APB Bus
  62 +          - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
  63 +
  64 +      - items:
  65 +          - description: Main Oscillator (24 MHz)
  66 +          - description: GMAC0 RMII reference
  67 +          - description: GMAC0 RGMII RX
  68 +          - description: STG AXI/AHB
  69 +          - description: APB Bus
  70 +          - description: GMAC0 GTX
  71 +          - description: RTC Oscillator (32.768 kHz)
  72 +
  73 +  clock-names:
  74 +    oneOf:
  75 +      - minItems: 5
  76 +        items:
  77 +          - const: osc
  78 +          - enum:
  79 +              - gmac0_rmii_refin
  80 +              - gmac0_rgmii_rxin
  81 +          - const: stg_axiahb
  82 +          - const: apb_bus
  83 +          - const: gmac0_gtxclk
  84 +          - const: rtc_osc
  85 +
  86 +      - minItems: 6
  87 +        items:
  88 +          - const: osc
  89 +          - const: gmac0_rmii_refin
  90 +          - const: gmac0_rgmii_rxin
  91 +          - const: stg_axiahb
  92 +          - const: apb_bus
  93 +          - const: gmac0_gtxclk
  94 +          - const: rtc_osc
  95 +
  96 +  '#clock-cells':
  97 +    const: 1
  98 +    description:
  99 +      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
 100 +
 101 +  '#reset-cells':
 102 +    const: 1
 103 +    description:
 104 +      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
 105 +
 106 +required:
 107 +  - compatible
 108 +  - reg
 109 +  - clocks
 110 +  - clock-names
 111 +  - '#clock-cells'
 112 +  - '#reset-cells'
 113 +
 114 +additionalProperties: false
 115 +
 116 +examples:
 117 +  - |
 118 +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
 119 +
 120 +    clock-controller@17000000 {
 121 +        compatible = "starfive,jh7110-aoncrg";
 122 +        reg = <0x17000000 0x10000>;
 123 +        clocks = <&osc>, <&gmac0_rmii_refin>,
 124 +                 <&gmac0_rgmii_rxin>,
 125 +                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 126 +                 <&syscrg JH7110_SYSCLK_APB_BUS>,
 127 +                 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
 128 +                 <&rtc_osc>;
 129 +        clock-names = "osc", "gmac0_rmii_refin",
 130 +                      "gmac0_rgmii_rxin", "stg_axiahb",
 131 +                      "apb_bus", "gmac0_gtxclk",
 132 +                      "rtc_osc";
 133 +        #clock-cells = <1>;
 134 +        #reset-cells = <1>;
 135 +    };
 136 diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
 137 index fdd1852e34cc..06257bfd9ac1 100644
 138 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
 139 +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
 140 @@ -200,4 +200,22 @@
 141
 142  #define JH7110_SYSCLK_END                      190
 143
 144 +/* AONCRG clocks */
 145 +#define JH7110_AONCLK_OSC_DIV4                 0
 146 +#define JH7110_AONCLK_APB_FUNC                 1
 147 +#define JH7110_AONCLK_GMAC0_AHB                        2
 148 +#define JH7110_AONCLK_GMAC0_AXI                        3
 149 +#define JH7110_AONCLK_GMAC0_RMII_RTX           4
 150 +#define JH7110_AONCLK_GMAC0_TX                 5
 151 +#define JH7110_AONCLK_GMAC0_TX_INV             6
 152 +#define JH7110_AONCLK_GMAC0_RX                 7
 153 +#define JH7110_AONCLK_GMAC0_RX_INV             8
 154 +#define JH7110_AONCLK_OTPC_APB                 9
 155 +#define JH7110_AONCLK_RTC_APB                  10
 156 +#define JH7110_AONCLK_RTC_INTERNAL             11
 157 +#define JH7110_AONCLK_RTC_32K                  12
 158 +#define JH7110_AONCLK_RTC_CAL                  13
 159 +
 160 +#define JH7110_AONCLK_END                      14
 161 +
 162  #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
 163 diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
 164 index b88216a4fe40..d78e38690ceb 100644
 165 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
 166 +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
 167 @@ -139,4 +139,16 @@
 168
 169  #define JH7110_SYSRST_END                      126
 170
 171 +/* AONCRG resets */
 172 +#define JH7110_AONRST_GMAC0_AXI                        0
 173 +#define JH7110_AONRST_GMAC0_AHB                        1
 174 +#define JH7110_AONRST_IOMUX                    2
 175 +#define JH7110_AONRST_PMU_APB                  3
 176 +#define JH7110_AONRST_PMU_WKUP                 4
 177 +#define JH7110_AONRST_RTC_APB                  5
 178 +#define JH7110_AONRST_RTC_CAL                  6
 179 +#define JH7110_AONRST_RTC_32K                  7
 180 +
 181 +#define JH7110_AONRST_END                      8
 182 +
 183  #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
 184 --
 185 2.20.1
 186