plat/arm/css/common/css_pm.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch_helpers.h>
   8 #include <assert.h>
   9 #include <cassert.h>
  10 #include <css_pm.h>
  11 #include <debug.h>
  12 #include <errno.h>
  13 #include <plat_arm.h>
  14 #include <platform.h>
  15 #include <platform_def.h>
  16 #include "../drivers/scp/css_scp.h"
  17
  18 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
  19 #pragma weak plat_arm_psci_pm_ops
  20
  21 #if ARM_RECOM_STATE_ID_ENC
  22 /*
  23  *  The table storing the valid idle power states. Ensure that the
  24  *  array entries are populated in ascending order of state-id to
  25  *  enable us to use binary search during power state validation.
  26  *  The table must be terminated by a NULL entry.
  27  */
  28 const unsigned int arm_pm_idle_states[] = {
  29         /* State-id - 0x001 */
  30         arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
  31                 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
  32         /* State-id - 0x002 */
  33         arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
  34                 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
  35         /* State-id - 0x022 */
  36         arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
  37                 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
  38 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
  39         /* State-id - 0x222 */
  40         arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
  41                 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
  42 #endif
  43         0,
  44 };
  45 #endif /* __ARM_RECOM_STATE_ID_ENC__ */
  46
  47 /*
  48  * All the power management helpers in this file assume at least cluster power
  49  * level is supported.
  50  */
  51 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
  52                 assert_max_pwr_lvl_supported_mismatch);
  53
  54 /*
  55  * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL
  56  * assumed by the CSS layer.
  57  */
  58 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
  59                 assert_max_pwr_lvl_higher_than_css_sys_lvl);
  60
  61 /*******************************************************************************
  62  * Handler called when a power domain is about to be turned on. The
  63  * level and mpidr determine the affinity instance.
  64  ******************************************************************************/
  65 int css_pwr_domain_on(u_register_t mpidr)
  66 {
  67         css_scp_on(mpidr);
  68
  69         return PSCI_E_SUCCESS;
  70 }
  71
  72 static void css_pwr_domain_on_finisher_common(
  73                 const psci_power_state_t *target_state)
  74 {
  75         assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
  76
  77         /* Enable the gic cpu interface */
  78         plat_arm_gic_cpuif_enable();
  79
  80         /*
  81          * Perform the common cluster specific operations i.e enable coherency
  82          * if this cluster was off.
  83          */
  84         if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
  85                 plat_arm_interconnect_enter_coherency();
  86 }
  87
  88 /*******************************************************************************
  89  * Handler called when a power level has just been powered on after
  90  * being turned off earlier. The target_state encodes the low power state that
  91  * each level has woken up from. This handler would never be invoked with
  92  * the system power domain uninitialized as either the primary would have taken
  93  * care of it as part of cold boot or the first core awakened from system
  94  * suspend would have already initialized it.
  95  ******************************************************************************/
  96 void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
  97 {
  98         /* Assert that the system power domain need not be initialized */
  99         assert(CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_RUN);
 100
 101         /* Program the gic per-cpu distributor or re-distributor interface */
 102         plat_arm_gic_pcpu_init();
 103
 104         css_pwr_domain_on_finisher_common(target_state);
 105 }
 106
 107 /*******************************************************************************
 108  * Common function called while turning a cpu off or suspending it. It is called
 109  * from css_off() or css_suspend() when these functions in turn are called for
 110  * power domain at the highest power level which will be powered down. It
 111  * performs the actions common to the OFF and SUSPEND calls.
 112  ******************************************************************************/
 113 static void css_power_down_common(const psci_power_state_t *target_state)
 114 {
 115         /* Prevent interrupts from spuriously waking up this cpu */
 116         plat_arm_gic_cpuif_disable();
 117
 118         /* Cluster is to be turned off, so disable coherency */
 119         if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
 120                 plat_arm_interconnect_exit_coherency();
 121 }
 122
 123 /*******************************************************************************
 124  * Handler called when a power domain is about to be turned off. The
 125  * target_state encodes the power state that each level should transition to.
 126  ******************************************************************************/
 127 void css_pwr_domain_off(const psci_power_state_t *target_state)
 128 {
 129         assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
 130         css_power_down_common(target_state);
 131         css_scp_off(target_state);
 132 }
 133
 134 /*******************************************************************************
 135  * Handler called when a power domain is about to be suspended. The
 136  * target_state encodes the power state that each level should transition to.
 137  ******************************************************************************/
 138 void css_pwr_domain_suspend(const psci_power_state_t *target_state)
 139 {
 140         /*
 141          * CSS currently supports retention only at cpu level. Just return
 142          * as nothing is to be done for retention.
 143          */
 144         if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
 145                 return;
 146
 147
 148         assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
 149         css_power_down_common(target_state);
 150
 151         /* Perform system domain state saving if issuing system suspend */
 152         if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
 153                 arm_system_pwr_domain_save();
 154
 155                 /* Power off the Redistributor after having saved its context */
 156                 plat_arm_gic_redistif_off();
 157         }
 158
 159         css_scp_suspend(target_state);
 160 }
 161
 162 /*******************************************************************************
 163  * Handler called when a power domain has just been powered on after
 164  * having been suspended earlier. The target_state encodes the low power state
 165  * that each level has woken up from.
 166  * TODO: At the moment we reuse the on finisher and reinitialize the secure
 167  * context. Need to implement a separate suspend finisher.
 168  ******************************************************************************/
 169 void css_pwr_domain_suspend_finish(
 170                                 const psci_power_state_t *target_state)
 171 {
 172         /* Return as nothing is to be done on waking up from retention. */
 173         if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
 174                 return;
 175
 176         /* Perform system domain restore if woken up from system suspend */
 177         if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
 178                 /*
 179                  * At this point, the Distributor must be powered on to be ready
 180                  * to have its state restored. The Redistributor will be powered
 181                  * on as part of gicv3_rdistif_init_restore.
 182                  */
 183                 arm_system_pwr_domain_resume();
 184
 185         css_pwr_domain_on_finisher_common(target_state);
 186 }
 187
 188 /*******************************************************************************
 189  * Handlers to shutdown/reboot the system
 190  ******************************************************************************/
 191 void __dead2 css_system_off(void)
 192 {
 193         css_scp_sys_shutdown();
 194 }
 195
 196 void __dead2 css_system_reset(void)
 197 {
 198         css_scp_sys_reboot();
 199 }
 200
 201 /*******************************************************************************
 202  * Handler called when the CPU power domain is about to enter standby.
 203  ******************************************************************************/
 204 void css_cpu_standby(plat_local_state_t cpu_state)
 205 {
 206         unsigned int scr;
 207
 208         assert(cpu_state == ARM_LOCAL_STATE_RET);
 209
 210         scr = read_scr_el3();
 211         /*
 212          * Enable the Non secure interrupt to wake the CPU.
 213          * In GICv3 affinity routing mode, the non secure group1 interrupts use
 214          * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ.
 215          * Enabling both the bits works for both GICv2 mode and GICv3 affinity
 216          * routing mode.
 217          */
 218         write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
 219         isb();
 220         dsb();
 221         wfi();
 222
 223         /*
 224          * Restore SCR to the original value, synchronisation of scr_el3 is
 225          * done by eret while el3_exit to save some execution cycles.
 226          */
 227         write_scr_el3(scr);
 228 }
 229
 230 /*******************************************************************************
 231  * Handler called to return the 'req_state' for system suspend.
 232  ******************************************************************************/
 233 void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
 234 {
 235         unsigned int i;
 236
 237         /*
 238          * System Suspend is supported only if the system power domain node
 239          * is implemented.
 240          */
 241         assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL);
 242
 243         for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
 244                 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
 245 }
 246
 247 /*******************************************************************************
 248  * Handler to query CPU/cluster power states from SCP
 249  ******************************************************************************/
 250 int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
 251 {
 252         return css_scp_get_power_state(mpidr, power_level);
 253 }
 254
 255 /*
 256  * The system power domain suspend is only supported only via
 257  * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
 258  * will be downgraded to the lower level.
 259  */
 260 static int css_validate_power_state(unsigned int power_state,
 261                             psci_power_state_t *req_state)
 262 {
 263         int rc;
 264         rc = arm_validate_power_state(power_state, req_state);
 265
 266         /*
 267          * Ensure that the system power domain level is never suspended
 268          * via PSCI CPU SUSPEND API. Currently system suspend is only
 269          * supported via PSCI SYSTEM SUSPEND API.
 270          */
 271         req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = ARM_LOCAL_STATE_RUN;
 272         return rc;
 273 }
 274
 275 /*
 276  * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the
 277  * `css_validate_power_state`, we do not downgrade the system power
 278  * domain level request in `power_state` as it will be used to query the
 279  * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
 280  */
 281 static int css_translate_power_state_by_mpidr(u_register_t mpidr,
 282                 unsigned int power_state,
 283                 psci_power_state_t *output_state)
 284 {
 285         return arm_validate_power_state(power_state, output_state);
 286 }
 287
 288 /*******************************************************************************
 289  * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
 290  * platform will take care of registering the handlers with PSCI.
 291  ******************************************************************************/
 292 plat_psci_ops_t plat_arm_psci_pm_ops = {
 293         .pwr_domain_on          = css_pwr_domain_on,
 294         .pwr_domain_on_finish   = css_pwr_domain_on_finish,
 295         .pwr_domain_off         = css_pwr_domain_off,
 296         .cpu_standby            = css_cpu_standby,
 297         .pwr_domain_suspend     = css_pwr_domain_suspend,
 298         .pwr_domain_suspend_finish      = css_pwr_domain_suspend_finish,
 299         .system_off             = css_system_off,
 300         .system_reset           = css_system_reset,
 301         .validate_power_state   = css_validate_power_state,
 302         .validate_ns_entrypoint = arm_validate_psci_entrypoint,
 303         .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr,
 304         .get_node_hw_state      = css_node_hw_state,
 305         .get_sys_suspend_power_state = css_get_sys_suspend_power_state,
 306
 307 #if defined(PLAT_ARM_MEM_PROT_ADDR)
 308         .mem_protect_chk        = arm_psci_mem_protect_chk,
 309         .read_mem_protect       = arm_psci_read_mem_protect,
 310         .write_mem_protect      = arm_nor_psci_write_mem_protect,
 311 #endif
 312 #if CSS_USE_SCMI_SDS_DRIVER
 313         .system_reset2          = css_system_reset2,
 314 #endif
 315 };