package/boot/uboot-sunxi/patches/4201-myir-spi.patch

   1 diff -ruN u-boot-2023.04/arch/arm/dts/Makefile spi/arch/arm/dts/Makefile
   2 --- u-boot-2023.04/arch/arm/dts/Makefile        2023-07-20 13:58:39.714010154 +0200
   3 +++ spi/arch/arm/dts/Makefile   2023-07-20 14:46:44.403569974 +0200
   4 @@ -715,6 +715,7 @@
   5         sun8i-t113s-mangopi-mq-r-t113.dtb \
   6         sun8i-t113s-mangopi-mqdual-t113.dtb \
   7         sun8i-t113s-myir-myd-yt113x.dtb \
   8 +       sun8i-t113s-myir-myd-yt113x-spi.dtb \
   9         sun8i-t113s-rongpin-rp-t113.dtb
  10  dtb-$(CONFIG_MACH_SUN50I_H5) += \
  11         sun50i-h5-bananapi-m2-plus.dtb \
  12 diff -ruN u-boot-2023.04/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts spi/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
  13 --- u-boot-2023.04/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts     1970-01-01 01:00:00.000000000 +0100
  14 +++ spi/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts        2023-07-20 14:52:36.468334540 +0200
  15 @@ -0,0 +1,59 @@
  16 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  17 +// Copyright (C) 2022 Arm Ltd.
  18 +
  19 +#include <dt-bindings/interrupt-controller/irq.h>
  20 +
  21 +/dts-v1/;
  22 +
  23 +#include "sun8i-t113s.dtsi"
  24 +#include "sunxi-d1s-t113-mangopi-mq-r.dtsi"
  25 +
  26 +/ {
  27 +       model = "MYIR MYD-YT113X (SPI)";
  28 +       compatible = "myir,myd-yt113x", "myir,myc-yt113x", "allwinner,sun8i-t113s";
  29 +
  30 +       aliases {
  31 +               serial5 = &uart5;
  32 +       };
  33 +
  34 +       chosen {
  35 +               stdout-path = "serial5:115200n8";
  36 +       };
  37 +};
  38 +
  39 +&cpu0 {
  40 +       cpu-supply = <&reg_vcc_core>;
  41 +};
  42 +
  43 +&cpu1 {
  44 +       cpu-supply = <&reg_vcc_core>;
  45 +};
  46 +
  47 +&pio {
  48 +       /omit-if-no-ref/
  49 +       uart5_pins: uart5-pins {
  50 +               pins = "PE6", "PE7";
  51 +               function = "uart5";
  52 +       };
  53 +};
  54 +
  55 +&uart5 {
  56 +       pinctrl-names = "default";
  57 +       pinctrl-0 = <&uart5_pins>;
  58 +       status = "okay";
  59 +};
  60 +
  61 +&uart3 {
  62 +       status = "disabled";
  63 +};
  64 +
  65 +&spi0 {
  66 +       pinctrl-names = "default";
  67 +       pinctrl-0 = <&spi0_pins>;
  68 +       status = "okay";
  69 +       spi_nand@0 {
  70 +               compatible = "spi-nand";
  71 +               reg = <0>;
  72 +                spi-max-frequency = <52000000>;
  73 +       };
  74 +};
  75 diff -ruN u-boot-2023.04/configs/myir_myd_t113x-spi_defconfig spi/configs/myir_myd_t113x-spi_defconfig
  76 --- u-boot-2023.04/configs/myir_myd_t113x-spi_defconfig 1970-01-01 01:00:00.000000000 +0100
  77 +++ spi/configs/myir_myd_t113x-spi_defconfig    2023-07-20 14:33:59.790587258 +0200
  78 @@ -0,0 +1,37 @@
  79 +CONFIG_ARM=y
  80 +CONFIG_ARCH_SUNXI=y
  81 +CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-myir-myd-yt113x-spi"
  82 +CONFIG_SUNXI_MINIMUM_DRAM_MB=128
  83 +CONFIG_SPL=y
  84 +CONFIG_SPL_SPI_SUNXI=y
  85 +CONFIG_MTD_SPI_NAND=y
  86 +CONFIG_MACH_SUN8I_R528=y
  87 +CONFIG_CONS_INDEX=6
  88 +CONFIG_MMC0_CD_PIN="PF6"
  89 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
  90 +CONFIG_SYS_MONITOR_LEN=786432
  91 +CONFIG_DRAM_CLK=792
  92 +CONFIG_DRAM_ZQ=8092667
  93 +CONFIG_DRAM_SUNXI_ODT_EN=0
  94 +CONFIG_DRAM_SUNXI_TPR0=0x004a2195
  95 +CONFIG_DRAM_SUNXI_TPR11=0x340000
  96 +CONFIG_DRAM_SUNXI_TPR12=0x46
  97 +CONFIG_DRAM_SUNXI_TPR13=0x34000100
  98 +CONFIG_PHY_MOTORCOMM=y
  99 +CONFIG_SUN8I_EMAC=y
 100 +CONFIG_RGMII=y
 101 +CONFIG_RMII=y
 102 +CONFIG_MTD=y
 103 +CONFIG_DM_MTD=y
 104 +CONFIG_SYS_MTDPARTS_RUNTIME=y
 105 +CONFIG_NAND_STM32_FMC2=y
 106 +CONFIG_SYS_NAND_ONFI_DETECTION=y
 107 +CONFIG_MTD_SPI_NAND=y
 108 +CONFIG_DM_SPI_FLASH=y
 109 +CONFIG_SPI_FLASH_MACRONIX=y
 110 +CONFIG_SPI_FLASH_SPANSION=y
 111 +CONFIG_SPI_FLASH_STMICRO=y
 112 +CONFIG_SPI_FLASH_WINBOND=y
 113 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 114 +CONFIG_SPI_FLASH_MTD=y
 115 +CONFIG_SPI=y