package/boot/uboot-sunxi/patches/4102-sunxi-psci-refactor-register-access-to-separate-func.patch

   1 From 1422f560d647d466f2b99fbc917ac4f6a1d3af38 Mon Sep 17 00:00:00 2001
   2 From: Sam Edwards <cfsworks@gmail.com>
   3 Date: Thu, 1 Jun 2023 15:48:13 -0600
   4 Subject: [PATCH 4102/4103] sunxi: psci: refactor register access to separate
   5  functions
   6
   7 This is to prepare for R528, which does not have the typical
   8 "CPUCFG" block; it has a "CPUX" block which provides these
   9 same functions but is organized differently.
  10
  11 Moving the hardware-access bits to their own functions separates the
  12 logic from the hardware so we can reuse the same logic.
  13
  14 Signed-off-by: Sam Edwards <CFSworks@gmail.com>
  15 ---
  16  arch/arm/cpu/armv7/sunxi/psci.c | 66 +++++++++++++++++++++++----------
  17  1 file changed, 47 insertions(+), 19 deletions(-)
  18
  19 diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
  20 index 7809b074f8..94120e7526 100644
  21 --- a/arch/arm/cpu/armv7/sunxi/psci.c
  22 +++ b/arch/arm/cpu/armv7/sunxi/psci.c
  23 @@ -114,7 +114,7 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
  24         }
  25  }
  26
  27 -static void __secure sunxi_set_entry_address(void *entry)
  28 +static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry)
  29  {
  30         /* secondary core entry address is programmed differently on R40 */
  31         if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
  32 @@ -154,30 +154,60 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
  33         }
  34  }
  35
  36 -void __secure sunxi_cpu_power_off(u32 cpuid)
  37 +static void __secure sunxi_cpu_set_reset(int cpu, bool reset)
  38 +{
  39 +       struct sunxi_cpucfg_reg *cpucfg =
  40 +               (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  41 +
  42 +       writel(reset ? 0b00 : 0b11, &cpucfg->cpu[cpu].rst);
  43 +}
  44 +
  45 +static void __secure sunxi_cpu_set_locking(int cpu, bool lock)
  46  {
  47         struct sunxi_cpucfg_reg *cpucfg =
  48                 (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  49 +
  50 +       if (lock)
  51 +               clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
  52 +       else
  53 +               setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
  54 +}
  55 +
  56 +static bool __secure sunxi_cpu_poll_wfi(int cpu)
  57 +{
  58 +       struct sunxi_cpucfg_reg *cpucfg =
  59 +               (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  60 +
  61 +       return !!(readl(&cpucfg->cpu[cpu].status) & BIT(2));
  62 +}
  63 +
  64 +static void __secure sunxi_cpu_invalidate_cache(int cpu)
  65 +{
  66 +       struct sunxi_cpucfg_reg *cpucfg =
  67 +               (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  68 +
  69 +       clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
  70 +}
  71 +
  72 +void __secure sunxi_cpu_power_off(u32 cpuid)
  73 +{
  74         u32 cpu = cpuid & 0x3;
  75
  76         /* Wait for the core to enter WFI */
  77 -       while (1) {
  78 -               if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
  79 -                       break;
  80 +       while (!sunxi_cpu_poll_wfi(cpu))
  81                 __mdelay(1);
  82 -       }
  83
  84         /* Assert reset on target CPU */
  85 -       writel(0, &cpucfg->cpu[cpu].rst);
  86 +       sunxi_cpu_set_reset(cpu, true);
  87
  88         /* Lock CPU (Disable external debug access) */
  89 -       clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
  90 +       sunxi_cpu_set_locking(cpu, true);
  91
  92         /* Power down CPU */
  93         sunxi_cpu_set_power(cpuid, false);
  94
  95 -       /* Unlock CPU (Disable external debug access) */
  96 -       setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
  97 +       /* Unlock CPU (Reenable external debug access) */
  98 +       sunxi_cpu_set_locking(cpu, false);
  99  }
 100
 101  static u32 __secure cp15_read_scr(void)
 102 @@ -234,33 +264,31 @@ out:
 103  int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
 104                          u32 context_id)
 105  {
 106 -       struct sunxi_cpucfg_reg *cpucfg =
 107 -               (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 108         u32 cpu = (mpidr & 0x3);
 109
 110         /* store target PC and context id */
 111         psci_save(cpu, pc, context_id);
 112
 113         /* Set secondary core power on PC */
 114 -       sunxi_set_entry_address(&psci_cpu_entry);
 115 +       sunxi_cpu_set_entry(cpu, &psci_cpu_entry);
 116
 117         /* Assert reset on target CPU */
 118 -       writel(0, &cpucfg->cpu[cpu].rst);
 119 +       sunxi_cpu_set_reset(cpu, true);
 120
 121         /* Invalidate L1 cache */
 122 -       clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
 123 +       sunxi_cpu_invalidate_cache(cpu);
 124
 125         /* Lock CPU (Disable external debug access) */
 126 -       clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
 127 +       sunxi_cpu_set_locking(cpu, true);
 128
 129         /* Power up target CPU */
 130         sunxi_cpu_set_power(cpu, true);
 131
 132         /* De-assert reset on target CPU */
 133 -       writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
 134 +       sunxi_cpu_set_reset(cpu, false);
 135
 136 -       /* Unlock CPU (Disable external debug access) */
 137 -       setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
 138 +       /* Unlock CPU (Reenable external debug access) */
 139 +       sunxi_cpu_set_locking(cpu, false);
 140
 141         return ARM_PSCI_RET_SUCCESS;
 142  }
 143 --
 144 2.20.1
 145