package/boot/uboot-sunxi/patches/4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch

   1 From 32020fad9d2fc6ce8f6e67af2ac7c9c6e7c47dec Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@arm.com>
   3 Date: Fri, 21 Jul 2023 14:46:05 +0100
   4 Subject: [PATCH 4025/4044] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi
   5
   6 The Allwinner T113-s SoC is apparently using the same (or at least a very
   7 similar) die as the D1/D1s, but replaces the single RISC-V core with
   8 two Arm Cortex-A7 cores.
   9 Since the D1 core .dtsi already describes all common peripherals, we
  10 just need a DT describing the ARM specific peripherals: the CPU cores,
  11 the Generic Timer, the GIC and the PMU.
  12 We include the core .dtsi directly from the riscv DT directory.
  13
  14 The ARM core version of the DT specifies the CPUX watchdog as
  15 "reserved", which means it won't be recognised by U-Boot. Override this
  16 in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
  17 so that the generic reset driver will work.
  18
  19 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  20 Reviewed-by: Sam Edwards <CFSworks@gmail.com>
  21 Tested-by: Sam Edwards <CFSworks@gmail.com>
  22 ---
  23  arch/arm/dts/sun8i-t113s.dtsi  | 59 ++++++++++++++++++++++++++++++++++
  24  arch/arm/dts/sunxi-u-boot.dtsi |  7 ++++
  25  2 files changed, 66 insertions(+)
  26  create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
  27
  28 diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-t113s.dtsi
  29 new file mode 100644
  30 index 0000000000..ce00883130
  31 --- /dev/null
  32 +++ b/arch/arm/dts/sun8i-t113s.dtsi
  33 @@ -0,0 +1,59 @@
  34 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  35 +// Copyright (C) 2022 Arm Ltd.
  36 +
  37 +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
  38 +
  39 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  40 +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
  41 +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
  42 +
  43 +/ {
  44 +       interrupt-parent = <&gic>;
  45 +
  46 +       cpus {
  47 +               #address-cells = <1>;
  48 +               #size-cells = <0>;
  49 +
  50 +               cpu0: cpu@0 {
  51 +                       compatible = "arm,cortex-a7";
  52 +                       device_type = "cpu";
  53 +                       reg = <0>;
  54 +                       clocks = <&ccu CLK_CPUX>;
  55 +                       clock-names = "cpu";
  56 +               };
  57 +
  58 +               cpu1: cpu@1 {
  59 +                       compatible = "arm,cortex-a7";
  60 +                       device_type = "cpu";
  61 +                       reg = <1>;
  62 +                       clocks = <&ccu CLK_CPUX>;
  63 +                       clock-names = "cpu";
  64 +               };
  65 +       };
  66 +
  67 +       gic: interrupt-controller@1c81000 {
  68 +               compatible = "arm,gic-400";
  69 +               reg = <0x03021000 0x1000>,
  70 +                     <0x03022000 0x2000>,
  71 +                     <0x03024000 0x2000>,
  72 +                     <0x03026000 0x2000>;
  73 +               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  74 +               interrupt-controller;
  75 +               #interrupt-cells = <3>;
  76 +       };
  77 +
  78 +       timer {
  79 +               compatible = "arm,armv7-timer";
  80 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  81 +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  82 +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  83 +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  84 +       };
  85 +
  86 +       pmu {
  87 +               compatible = "arm,cortex-a7-pmu";
  88 +               interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
  89 +                            <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
  90 +               interrupt-affinity = <&cpu0>, <&cpu1>;
  91 +       };
  92 +};
  93 diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
  94 index e959eb2a40..27de5b8eac 100644
  95 --- a/arch/arm/dts/sunxi-u-boot.dtsi
  96 +++ b/arch/arm/dts/sunxi-u-boot.dtsi
  97 @@ -23,6 +23,13 @@
  98         };
  99  };
 100
 101 +/* Let U-Boot be the firmware layer that controls the watchdog. */
 102 +#ifdef CONFIG_MACH_SUN8I_R528
 103 +&wdt {
 104 +       status = "okay";
 105 +};
 106 +#endif
 107 +
 108  &binman {
 109         u-boot-sunxi-with-spl {
 110                 filename = "u-boot-sunxi-with-spl.bin";
 111 --
 112 2.20.1
 113